diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/ptrtoint-ptrtoaddr-p8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/ptrtoint-ptrtoaddr-p8.ll
new file mode 100644
index 0000000000000..e56c99a4316fa
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/ptrtoint-ptrtoaddr-p8.ll
@@ -0,0 +1,424 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -global-isel -verify-machineinstrs < %s | FileCheck %s
+;; Check that we can lower ptrtoaddr differently from ptrtoint.
+;; Includes an ignored argument so the registers actually need to be written
+;; Also all functions are zeroext to show that non-address bits are masked off
+;; instead of filling them with arbitrary data
+
+define zeroext i32 @ptrtoint_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoint_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define zeroext i32 @ptrtoaddr_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoaddr_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define <2 x i32> @ptrtoint_vec_as5(ptr addrspace(5) %ignored, <2 x ptr addrspace(5)> %ptr) {
+; CHECK-LABEL: ptrtoint_vec_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    v_mov_b32_e32 v1, v2
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint <2 x ptr addrspace(5)> %ptr to <2 x i32>
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @ptrtoaddr_vec_as5(ptr addrspace(5) %ignored, <2 x ptr addrspace(5)> %ptr) {
+; CHECK-LABEL: ptrtoaddr_vec_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    v_mov_b32_e32 v1, v2
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr <2 x ptr addrspace(5)> %ptr to <2 x i32>
+  ret <2 x i32> %ret
+}
+
+define zeroext i256 @ptrtoint_ext_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoint_ext_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i256
+  ret i256 %ret
+}
+
+;; Check that we extend the offset to i256 instead of reinterpreting all bits.
+define zeroext i256 @ptrtoaddr_ext_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoaddr_ext_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
+  %ret = zext i32 %addr to i256
+  ret i256 %ret
+}
+
+define zeroext i32 @ptrtoint_trunc_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoint_trunc_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define zeroext i16 @ptrtoaddr_trunc_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoaddr_trunc_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_and_b32_e32 v0, 0xffff, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
+  %ret = trunc i32 %addr to i16
+  ret i16 %ret
+}
+
+define zeroext i128 @ptrtoint_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoint_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_mov_b32_e32 v1, v5
+; CHECK-NEXT:    v_mov_b32_e32 v2, v6
+; CHECK-NEXT:    v_mov_b32_e32 v3, v7
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i128
+  ret i128 %ret
+}
+
+define zeroext i48 @ptrtoaddr_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoaddr_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr ptr addrspace(8) %ptr to i48
+  ret i48 %ret
+}
+
+define <2 x i128> @ptrtoint_vec_as8(ptr addrspace(8) %ignored, <2 x ptr addrspace(8)> %ptr) {
+; CHECK-LABEL: ptrtoint_vec_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_mov_b32_e32 v1, v5
+; CHECK-NEXT:    v_mov_b32_e32 v2, v6
+; CHECK-NEXT:    v_mov_b32_e32 v3, v7
+; CHECK-NEXT:    v_mov_b32_e32 v4, v8
+; CHECK-NEXT:    v_mov_b32_e32 v5, v9
+; CHECK-NEXT:    v_mov_b32_e32 v6, v10
+; CHECK-NEXT:    v_mov_b32_e32 v7, v11
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint <2 x ptr addrspace(8)> %ptr to <2 x i128>
+  ret <2 x i128> %ret
+}
+
+;; Note: needs to be 2 x i64 instead of 2 x i48 since the latter is not supported.
+define <2 x i64> @ptrtoaddr_vec_as8(ptr addrspace(8) %ignored, <2 x ptr addrspace(8)> %ptr) {
+; CHECK-LABEL: ptrtoaddr_vec_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_mov_b32_e32 v2, v8
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
+; CHECK-NEXT:    v_and_b32_e32 v3, 0xffff, v9
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr <2 x ptr addrspace(8)> %ptr to <2 x i48>
+  %ret = zext <2 x i48> %addr to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+define zeroext i256 @ptrtoint_ext_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoint_ext_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_mov_b32_e32 v1, v5
+; CHECK-NEXT:    v_mov_b32_e32 v2, v6
+; CHECK-NEXT:    v_mov_b32_e32 v3, v7
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i256
+  ret i256 %ret
+}
+
+;; Check that we extend the offset to i256 instead of reinterpreting all bits.
+define zeroext i256 @ptrtoaddr_ext_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoaddr_ext_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
+  %ret = zext i48 %addr to i256
+  ret i256 %ret
+}
+
+define zeroext i64 @ptrtoint_trunc_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoint_trunc_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_mov_b32_e32 v1, v5
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i64
+  ret i64 %ret
+}
+
+define zeroext i16 @ptrtoaddr_trunc_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoaddr_trunc_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_and_b32_e32 v0, 0xffff, v4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
+  %ret = trunc i48 %addr to i16
+  ret i16 %ret
+}
+
+;; SGPR variants:
+define zeroext i32 @ptrtoint_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define zeroext i32 @ptrtoaddr_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define <2 x i32> @ptrtoint_vec_as5_sgpr(ptr addrspace(5) inreg %ignored, <2 x ptr addrspace(5)> %ptr) {
+; CHECK-LABEL: ptrtoint_vec_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint <2 x ptr addrspace(5)> %ptr to <2 x i32>
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @ptrtoaddr_vec_as5_sgpr(ptr addrspace(5) inreg %ignored, <2 x ptr addrspace(5)> %ptr) {
+; CHECK-LABEL: ptrtoaddr_vec_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr <2 x ptr addrspace(5)> %ptr to <2 x i32>
+  ret <2 x i32> %ret
+}
+
+define zeroext i256 @ptrtoint_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_ext_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i256
+  ret i256 %ret
+}
+
+;; Check that we extend the offset to i256 instead of reinterpreting all bits.
+define zeroext i256 @ptrtoaddr_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_ext_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
+  %ret = zext i32 %addr to i256
+  ret i256 %ret
+}
+
+define zeroext i32 @ptrtoint_trunc_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_trunc_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define zeroext i16 @ptrtoaddr_trunc_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_trunc_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_and_b32 s4, s17, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
+  %ret = trunc i32 %addr to i16
+  ret i16 %ret
+}
+
+define zeroext i128 @ptrtoint_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s21
+; CHECK-NEXT:    v_mov_b32_e32 v2, s22
+; CHECK-NEXT:    v_mov_b32_e32 v3, s23
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i128
+  ret i128 %ret
+}
+
+define zeroext i48 @ptrtoaddr_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_and_b32 s4, s21, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr ptr addrspace(8) %ptr to i48
+  ret i48 %ret
+}
+
+define <2 x i128> @ptrtoint_vec_as8_sgpr(ptr addrspace(8) inreg %ignored, <2 x ptr addrspace(8)> %ptr) {
+; CHECK-LABEL: ptrtoint_vec_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint <2 x ptr addrspace(8)> %ptr to <2 x i128>
+  ret <2 x i128> %ret
+}
+
+;; Note: needs to be 2 x i64 instead of 2 x i48 since the latter is not supported.
+define <2 x i64> @ptrtoaddr_vec_as8_sgpr(ptr addrspace(8) inreg %ignored, <2 x ptr addrspace(8)> %ptr) {
+; CHECK-LABEL: ptrtoaddr_vec_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v2, v4
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; CHECK-NEXT:    v_and_b32_e32 v3, 0xffff, v5
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr <2 x ptr addrspace(8)> %ptr to <2 x i48>
+  %ret = zext <2 x i48> %addr to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+define zeroext i256 @ptrtoint_ext_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_ext_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s21
+; CHECK-NEXT:    v_mov_b32_e32 v2, s22
+; CHECK-NEXT:    v_mov_b32_e32 v3, s23
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i256
+  ret i256 %ret
+}
+
+;; Check that we extend the offset to i256 instead of reinterpreting all bits.
+define zeroext i256 @ptrtoaddr_ext_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_ext_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_and_b32 s4, s21, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
+  %ret = zext i48 %addr to i256
+  ret i256 %ret
+}
+
+define zeroext i64 @ptrtoint_trunc_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_trunc_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s21
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i64
+  ret i64 %ret
+}
+
+define zeroext i16 @ptrtoaddr_trunc_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_trunc_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_and_b32 s4, s20, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
+  %ret = trunc i48 %addr to i16
+  ret i16 %ret
+}
diff --git a/llvm/test/CodeGen/AMDGPU/ptrtoint-ptrtoaddr.ll b/llvm/test/CodeGen/AMDGPU/ptrtoint-ptrtoaddr.ll
new file mode 100644
index 0000000000000..913a5748a6c43
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/ptrtoint-ptrtoaddr.ll
@@ -0,0 +1,424 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
+;; Check that we can lower ptrtoaddr differently from ptrtoint.
+;; Includes an ignored argument so the registers actually need to be written
+;; Also all functions are zeroext to show that non-address bits are masked off
+;; instead of filling them with arbitrary data
+
+define zeroext i32 @ptrtoint_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoint_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define zeroext i32 @ptrtoaddr_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoaddr_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define <2 x i32> @ptrtoint_vec_as5(ptr addrspace(5) %ignored, <2 x ptr addrspace(5)> %ptr) {
+; CHECK-LABEL: ptrtoint_vec_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    v_mov_b32_e32 v1, v2
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint <2 x ptr addrspace(5)> %ptr to <2 x i32>
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @ptrtoaddr_vec_as5(ptr addrspace(5) %ignored, <2 x ptr addrspace(5)> %ptr) {
+; CHECK-LABEL: ptrtoaddr_vec_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    v_mov_b32_e32 v1, v2
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr <2 x ptr addrspace(5)> %ptr to <2 x i32>
+  ret <2 x i32> %ret
+}
+
+define zeroext i256 @ptrtoint_ext_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoint_ext_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i256
+  ret i256 %ret
+}
+
+;; Check that we extend the offset to i256 instead of reinterpreting all bits.
+define zeroext i256 @ptrtoaddr_ext_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoaddr_ext_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
+  %ret = zext i32 %addr to i256
+  ret i256 %ret
+}
+
+define zeroext i32 @ptrtoint_trunc_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoint_trunc_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define zeroext i16 @ptrtoaddr_trunc_as5(ptr addrspace(5) %ignored, ptr addrspace(5) %ptr) {
+; CHECK-LABEL: ptrtoaddr_trunc_as5:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_and_b32_e32 v0, 0xffff, v1
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
+  %ret = trunc i32 %addr to i16
+  ret i16 %ret
+}
+
+define zeroext i128 @ptrtoint_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoint_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v3, v7
+; CHECK-NEXT:    v_mov_b32_e32 v2, v6
+; CHECK-NEXT:    v_mov_b32_e32 v1, v5
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i128
+  ret i128 %ret
+}
+
+define zeroext i48 @ptrtoaddr_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoaddr_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr ptr addrspace(8) %ptr to i48
+  ret i48 %ret
+}
+
+define <2 x i128> @ptrtoint_vec_as8(ptr addrspace(8) %ignored, <2 x ptr addrspace(8)> %ptr) {
+; CHECK-LABEL: ptrtoint_vec_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v3, v7
+; CHECK-NEXT:    v_mov_b32_e32 v2, v6
+; CHECK-NEXT:    v_mov_b32_e32 v1, v5
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_mov_b32_e32 v4, v8
+; CHECK-NEXT:    v_mov_b32_e32 v5, v9
+; CHECK-NEXT:    v_mov_b32_e32 v6, v10
+; CHECK-NEXT:    v_mov_b32_e32 v7, v11
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint <2 x ptr addrspace(8)> %ptr to <2 x i128>
+  ret <2 x i128> %ret
+}
+
+;; Note: needs to be 2 x i64 instead of 2 x i48 since the latter is not supported.
+define <2 x i64> @ptrtoaddr_vec_as8(ptr addrspace(8) %ignored, <2 x ptr addrspace(8)> %ptr) {
+; CHECK-LABEL: ptrtoaddr_vec_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v2, v8
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
+; CHECK-NEXT:    v_and_b32_e32 v3, 0xffff, v9
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr <2 x ptr addrspace(8)> %ptr to <2 x i48>
+  %ret = zext <2 x i48> %addr to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+define zeroext i256 @ptrtoint_ext_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoint_ext_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v3, v7
+; CHECK-NEXT:    v_mov_b32_e32 v2, v6
+; CHECK-NEXT:    v_mov_b32_e32 v1, v5
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i256
+  ret i256 %ret
+}
+
+;; Check that we extend the offset to i256 instead of reinterpreting all bits.
+define zeroext i256 @ptrtoaddr_ext_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoaddr_ext_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v5
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
+  %ret = zext i48 %addr to i256
+  ret i256 %ret
+}
+
+define zeroext i64 @ptrtoint_trunc_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoint_trunc_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v1, v5
+; CHECK-NEXT:    v_mov_b32_e32 v0, v4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i64
+  ret i64 %ret
+}
+
+define zeroext i16 @ptrtoaddr_trunc_as8(ptr addrspace(8) %ignored, ptr addrspace(8) %ptr) {
+; CHECK-LABEL: ptrtoaddr_trunc_as8:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_and_b32_e32 v0, 0xffff, v4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
+  %ret = trunc i48 %addr to i16
+  ret i16 %ret
+}
+
+;; SGPR variants:
+define zeroext i32 @ptrtoint_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define zeroext i32 @ptrtoaddr_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define <2 x i32> @ptrtoint_vec_as5_sgpr(ptr addrspace(5) inreg %ignored, <2 x ptr addrspace(5)> %ptr) {
+; CHECK-LABEL: ptrtoint_vec_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint <2 x ptr addrspace(5)> %ptr to <2 x i32>
+  ret <2 x i32> %ret
+}
+
+define <2 x i32> @ptrtoaddr_vec_as5_sgpr(ptr addrspace(5) inreg %ignored, <2 x ptr addrspace(5)> %ptr) {
+; CHECK-LABEL: ptrtoaddr_vec_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr <2 x ptr addrspace(5)> %ptr to <2 x i32>
+  ret <2 x i32> %ret
+}
+
+define zeroext i256 @ptrtoint_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_ext_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i256
+  ret i256 %ret
+}
+
+;; Check that we extend the offset to i256 instead of reinterpreting all bits.
+define zeroext i256 @ptrtoaddr_ext_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_ext_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    v_mov_b32_e32 v1, 0
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
+  %ret = zext i32 %addr to i256
+  ret i256 %ret
+}
+
+define zeroext i32 @ptrtoint_trunc_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_trunc_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s17
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(5) %ptr to i32
+  ret i32 %ret
+}
+
+define zeroext i16 @ptrtoaddr_trunc_as5_sgpr(ptr addrspace(5) inreg %ignored, ptr addrspace(5) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_trunc_as5_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_and_b32 s4, s17, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(5) %ptr to i32
+  %ret = trunc i32 %addr to i16
+  ret i16 %ret
+}
+
+define zeroext i128 @ptrtoint_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s21
+; CHECK-NEXT:    v_mov_b32_e32 v2, s22
+; CHECK-NEXT:    v_mov_b32_e32 v3, s23
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i128
+  ret i128 %ret
+}
+
+define zeroext i48 @ptrtoaddr_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_and_b32 s4, s21, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoaddr ptr addrspace(8) %ptr to i48
+  ret i48 %ret
+}
+
+define <2 x i128> @ptrtoint_vec_as8_sgpr(ptr addrspace(8) inreg %ignored, <2 x ptr addrspace(8)> %ptr) {
+; CHECK-LABEL: ptrtoint_vec_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint <2 x ptr addrspace(8)> %ptr to <2 x i128>
+  ret <2 x i128> %ret
+}
+
+;; Note: needs to be 2 x i64 instead of 2 x i48 since the latter is not supported.
+define <2 x i64> @ptrtoaddr_vec_as8_sgpr(ptr addrspace(8) inreg %ignored, <2 x ptr addrspace(8)> %ptr) {
+; CHECK-LABEL: ptrtoaddr_vec_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v2, v4
+; CHECK-NEXT:    v_and_b32_e32 v1, 0xffff, v1
+; CHECK-NEXT:    v_and_b32_e32 v3, 0xffff, v5
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr <2 x ptr addrspace(8)> %ptr to <2 x i48>
+  %ret = zext <2 x i48> %addr to <2 x i64>
+  ret <2 x i64> %ret
+}
+
+define zeroext i256 @ptrtoint_ext_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_ext_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s21
+; CHECK-NEXT:    v_mov_b32_e32 v2, s22
+; CHECK-NEXT:    v_mov_b32_e32 v3, s23
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i256
+  ret i256 %ret
+}
+
+;; Check that we extend the offset to i256 instead of reinterpreting all bits.
+define zeroext i256 @ptrtoaddr_ext_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_ext_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_and_b32 s4, s21, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s4
+; CHECK-NEXT:    v_mov_b32_e32 v2, 0
+; CHECK-NEXT:    v_mov_b32_e32 v3, 0
+; CHECK-NEXT:    v_mov_b32_e32 v4, 0
+; CHECK-NEXT:    v_mov_b32_e32 v5, 0
+; CHECK-NEXT:    v_mov_b32_e32 v6, 0
+; CHECK-NEXT:    v_mov_b32_e32 v7, 0
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
+  %ret = zext i48 %addr to i256
+  ret i256 %ret
+}
+
+define zeroext i64 @ptrtoint_trunc_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoint_trunc_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_mov_b32_e32 v0, s20
+; CHECK-NEXT:    v_mov_b32_e32 v1, s21
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %ret = ptrtoint ptr addrspace(8) %ptr to i64
+  ret i64 %ret
+}
+
+define zeroext i16 @ptrtoaddr_trunc_as8_sgpr(ptr addrspace(8) inreg %ignored, ptr addrspace(8) inreg %ptr) {
+; CHECK-LABEL: ptrtoaddr_trunc_as8_sgpr:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_and_b32 s4, s20, 0xffff
+; CHECK-NEXT:    v_mov_b32_e32 v0, s4
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %addr = ptrtoaddr ptr addrspace(8) %ptr to i48
+  %ret = trunc i48 %addr to i16
+  ret i16 %ret
+}