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[RISCV] Add GetVTypeMinimalPredicates for the operation supported by zvfhmin. NFC. #143847

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tclin914 merged 2 commits into from
Jun 16, 2025
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[RISCV] Add GetVTypeMinimalPredicates for the operation supported by zvfhmin. NFC. #143847

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[RISCV] Add GetVTypeMinimalPredicates for the operation supported by …
tclin914 Jun 12, 2025
aa60b56
Add VPatBinaryV_VI_INT.
tclin914 Jun 13, 2025
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58 changes: 26 additions & 32 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -783,6 +783,15 @@ class GetVTypePredicates<VTypeInfo vti> {
true : [HasVInstructions]);
}

class GetVTypeMinimalPredicates<VTypeInfo vti> {
list<Predicate> Predicates = !cond(!eq(vti.Scalar, f16) : [HasVInstructionsF16Minimal],
!eq(vti.Scalar, bf16) : [HasVInstructionsBF16Minimal],
!eq(vti.Scalar, f32) : [HasVInstructionsAnyF],
!eq(vti.Scalar, f64) : [HasVInstructionsF64],
!eq(vti.SEW, 64) : [HasVInstructionsI64],
true : [HasVInstructions]);
}

Comment on lines +786 to +794
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@lukel97 lukel97 Jun 13, 2025

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Maybe for a separate PR, I think for anything that's not a widening/converting instruction e.g. vmerge/vrgather/vcompress/vle/vse, we can just use the integer predicate, maybe something like:

class GetVTypeIntPredicates<VTypeInfo vti> {
   defvar ivti = GetIntVTypeInfo<vti>;
   list<Predicate> Predicates = GetVTypePredicates<ivti>;
 }

Since vmerge.vvm with a fp16 vector isn't really a zvfhmin instruction, it only requires zve32x.

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@lukel97 lukel97 Jun 13, 2025

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I think this is somewhat related to #143975

class VPseudoUSLoadNoMask<VReg RetClass,
int EEW,
DAGOperand sewop = sew> :
Expand Down Expand Up @@ -4568,7 +4577,7 @@ multiclass VPatUnaryS_M<string intrinsic_name,
multiclass VPatUnaryV_V_AnyMask<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in {
let Predicates = GetVTypePredicates<vti>.Predicates in
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
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@topperc topperc Jun 13, 2025

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Why weren't any tests failing if we using the wrong predicate?

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@tclin914 tclin914 Jun 13, 2025

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Why weren't any tests failing if we using the wrong predicate?

Currently, only int_riscv_vcompress uses the multiclass VPatUnaryV_V_AnyMask.
Originally, the predicate for the fp16 vector type was written as:

let Predicates = [HasVInstructionsF16Minimal] in
  defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFP16Vectors>;

I simply moved this predicate into the multiclass VPatUnaryV_V_AnyMask by replacing GetVTypePredicates with GetVTypeMinimalPredicates.

I hope I didn’t misunderstand your concern.

def : VPatUnaryAnyMask<intrinsic, instruction, "VM",
vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.RegClass>;
Expand Down Expand Up @@ -4887,7 +4896,7 @@ multiclass VPatBinaryV_VV_INT<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in {
defvar ivti = GetIntVTypeInfo<vti>.Vti;
let Predicates = GetVTypePredicates<vti>.Predicates in
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
defm : VPatBinary<intrinsic,
instruction # "_VV_" # vti.LMul.MX # "_E" # vti.SEW,
vti.Vector, vti.Vector, ivti.Vector, vti.Mask,
Expand Down Expand Up @@ -4950,7 +4959,7 @@ multiclass VPatBinaryV_VX_RM<string intrinsic, string instruction,
multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in
let Predicates = GetVTypePredicates<vti>.Predicates in
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
defm : VPatBinary<intrinsic, instruction # "_VX_" # vti.LMul.MX,
vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.RegClass,
Expand All @@ -4960,7 +4969,7 @@ multiclass VPatBinaryV_VX_INT<string intrinsic, string instruction,
multiclass VPatBinaryV_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand imm_type> {
foreach vti = vtilist in
let Predicates = GetVTypePredicates<vti>.Predicates in
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
defm : VPatBinary<intrinsic, instruction # "_VI_" # vti.LMul.MX,
vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.RegClass,
Expand Down Expand Up @@ -5887,12 +5896,11 @@ multiclass VPatConversionWF_VF<string intrinsic, string instruction,
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
// Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
!listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates)) in
defm : VPatConversion<intrinsic, instruction, "V",
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
GetVTypeMinimalPredicates<fwti>.Predicates) in
defm : VPatConversion<intrinsic, instruction, "V",
fwti.Vector, fvti.Vector, fwti.Mask, fvti.Log2SEW,
fvti.LMul, fwti.RegClass, fvti.RegClass, isSEWAware>;
}
}

Expand Down Expand Up @@ -5979,8 +5987,9 @@ multiclass VPatConversionVF_WF_RM<string intrinsic, string instruction,
foreach fvtiToFWti = wlist in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates) in
// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
GetVTypeMinimalPredicates<fwti>.Predicates) in
defm : VPatConversionRoundingMode<intrinsic, instruction, "W",
fvti.Vector, fwti.Vector, fvti.Mask, fvti.Log2SEW,
fvti.LMul, fvti.RegClass, fwti.RegClass,
Expand Down Expand Up @@ -7005,8 +7014,7 @@ defm : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">;
// 11.16. Vector Integer Move Instructions
//===----------------------------------------------------------------------===//
foreach vti = AllVectors in {
let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal],
GetVTypePredicates<vti>.Predicates) in {
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in {
def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$passthru),
(vti.Vector vti.RegClass:$rs1),
VLOpFrag)),
Expand Down Expand Up @@ -7201,8 +7209,7 @@ defm : VPatConversionVI_VF<"int_riscv_vfclass", "PseudoVFCLASS">;
// NOTE: Clang previously used int_riscv_vfmerge for vector-vector, but now uses
// int_riscv_vmerge. Support both for compatibility.
foreach vti = AllFloatVectors in {
let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal],
GetVTypePredicates<vti>.Predicates) in
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
defm : VPatBinaryCarryInTAIL<"int_riscv_vmerge", "PseudoVMERGE", "VVM",
vti.Vector,
vti.Vector, vti.Vector, vti.Mask,
Expand Down Expand Up @@ -7281,16 +7288,8 @@ defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_xu_w", "PseudoVFNCVT_F_XU",
isSEWAware=1>;
defm : VPatConversionVF_WI_RM<"int_riscv_vfncvt_f_x_w", "PseudoVFNCVT_F_X",
isSEWAware=1>;
defvar WidenableFloatVectorsExceptF16 = !filter(fvtiToFWti, AllWidenableFloatVectors,
!ne(fvtiToFWti.Vti.Scalar, f16));
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
WidenableFloatVectorsExceptF16, isSEWAware=1>;
// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
defvar F16WidenableFloatVectors = !filter(fvtiToFWti, AllWidenableFloatVectors,
!eq(fvtiToFWti.Vti.Scalar, f16));
let Predicates = [HasVInstructionsF16Minimal] in
defm : VPatConversionVF_WF_RM<"int_riscv_vfncvt_f_f_w", "PseudoVFNCVT_F_F",
F16WidenableFloatVectors, isSEWAware=1>;
AllWidenableFloatVectors, isSEWAware=1>;
defm : VPatConversionVF_WF_BF_RM<"int_riscv_vfncvtbf16_f_f_w",
"PseudoVFNCVTBF16_F_F", isSEWAware=1>;
defm : VPatConversionVF_WF<"int_riscv_vfncvt_rod_f_f_w", "PseudoVFNCVT_ROD_F_F",
Expand Down Expand Up @@ -7425,10 +7424,7 @@ defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
eew=16, vtilist=AllIntegerVectors>;

defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllFloatVectorsExceptFP16, uimm5>;
let Predicates = [HasVInstructionsF16Minimal] in
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllFP16Vectors, uimm5>;
AllFloatVectors, uimm5>;
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllBFloatVectors, uimm5>;
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
Expand All @@ -7437,9 +7433,7 @@ defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
// 16.5. Vector Compress Instruction
//===----------------------------------------------------------------------===//
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllIntegerVectors>;
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFloatVectorsExceptFP16>;
let Predicates = [HasVInstructionsF16Minimal] in
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFP16Vectors>;
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllFloatVectors>;
defm : VPatUnaryV_V_AnyMask<"int_riscv_vcompress", "PseudoVCOMPRESS", AllBFloatVectors>;

// Include the non-intrinsic ISel patterns
Expand Down
8 changes: 3 additions & 5 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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Expand Up @@ -864,8 +864,7 @@ multiclass VPatAVGADD_VV_VX_RM<SDNode vop, int vxrm, string suffix = ""> {

// 7.4. Vector Unit-Stride Instructions
foreach vti = AllVectors in
let Predicates = !if(!eq(vti.Scalar, f16), [HasVInstructionsF16Minimal],
GetVTypePredicates<vti>.Predicates) in
let Predicates = GetVTypeMinimalPredicates<vti>.Predicates in
defm : VPatUSLoadStoreSDNode<vti.Vector, vti.RegClass, vti.Log2SEW, vti.LMul,
vti.AVL, vti.RegClass>;
foreach mti = AllMasks in
Expand Down Expand Up @@ -1449,9 +1448,8 @@ defm : VPatNConvertI2FPSDNode_W_RM<any_uint_to_fp, "PseudoVFNCVT_F_XU_W">;
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
!listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates)) in
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
GetVTypeMinimalPredicates<fwti>.Predicates) in
def : Pat<(fvti.Vector (fpround (fwti.Vector fwti.RegClass:$rs1))),
(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX#"_E"#fvti.SEW)
(fvti.Vector (IMPLICIT_DEF)),
Expand Down
13 changes: 6 additions & 7 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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Expand Up @@ -2687,9 +2687,9 @@ defm : VPatWConvertI2FPVL_V<any_riscv_sint_to_fp_vl, "PseudoVFWCVT_F_X_V">;
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
!listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates)) in
// Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
GetVTypeMinimalPredicates<fwti>.Predicates) in
def : Pat<(fwti.Vector (any_riscv_fpextend_vl
(fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask VMV0:$vm),
Expand Down Expand Up @@ -2730,10 +2730,9 @@ defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_F_X_W">;
foreach fvtiToFWti = AllWidenableFloatVectors in {
defvar fvti = fvtiToFWti.Vti;
defvar fwti = fvtiToFWti.Wti;
// Define vfwcvt.f.f.v for f16 when Zvfhmin is enable.
let Predicates = !if(!eq(fvti.Scalar, f16), [HasVInstructionsF16Minimal],
!listconcat(GetVTypePredicates<fvti>.Predicates,
GetVTypePredicates<fwti>.Predicates)) in {
// Define vfncvt.f.f.w for f16 when Zvfhmin is enable.
let Predicates = !listconcat(GetVTypeMinimalPredicates<fvti>.Predicates,
GetVTypeMinimalPredicates<fwti>.Predicates) in {
def : Pat<(fvti.Vector (any_riscv_fpround_vl
(fwti.Vector fwti.RegClass:$rs1),
(fwti.Mask VMV0:$vm), VLOpFrag)),
Expand Down
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