diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index d7e6c71ea062e..a28761814c2a3 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -292,7 +292,8 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
                                        FeatureStdExtZbb],
                                       SiFiveIntelligenceTuneFeatures>;
 
-def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390", NoSchedModel,
+def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390",
+                                      SiFiveX390Model,
                                       [Feature64Bit,
                                        FeatureStdExtI,
                                        FeatureStdExtM,
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 071b64571fe3c..78a176fcf18d9 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -169,6 +169,12 @@ class SiFive7GetOrderedReductionCycles<string mx, int sew, int VLEN> {
   int c = !mul(6, VLUpperBound);
 }
 
+class SiFive7FPLatencies {
+  int BasicFP16ALU;
+  int BasicFP32ALU;
+  int BasicFP64ALU;
+}
+
 class SiFive7AnyToGPRBypass<SchedRead read, int cycles = 2>
     : ReadAdvance<read, cycles, [WriteIALU, WriteIALU32,
                                  WriteShiftImm, WriteShiftImm32,
@@ -186,12 +192,13 @@ class SiFive7AnyToGPRBypass<SchedRead read, int cycles = 2>
                                  WriteIRem, WriteIRem32,
                                  WriteLDB, WriteLDH, WriteLDW, WriteLDD]>;
 
-// The SiFive7 microarchitecture has three pipelines: A, B, V.
+// The SiFive7 microarchitecture has three kinds of pipelines: A, B, V.
 // Pipe A can handle memory, integer alu and vector operations.
 // Pipe B can handle integer alu, control flow, integer multiply and divide,
 // and floating point computation.
-// The V pipeline is modeled by the VCQ, VA, VL, and VS resources.
-multiclass SiFive7ProcResources {
+// The V pipeline is modeled by the VCQ, VA, VL, and VS resources. There can
+// be one or two VA (Vector Arithmetic).
+multiclass SiFive7ProcResources<bit extraVALU = false> {
   let BufferSize = 0 in {
     def PipeA     : ProcResource<1>;
     def PipeB     : ProcResource<1>;
@@ -199,7 +206,15 @@ multiclass SiFive7ProcResources {
     def IDiv      : ProcResource<1>; // Int Division
     def FDiv      : ProcResource<1>; // FP Division/Sqrt
 
-    def VA      : ProcResource<1>; // Arithmetic sequencer
+    // Arithmetic sequencer(s)
+    if extraVALU then {
+      // VA1 can handle any vector airthmetic instruction.
+      def VA1     : ProcResource<1>;
+      // VA2 generally can only handle simple vector arithmetic.
+      def VA2     : ProcResource<1>;
+    } else {
+      def VA      : ProcResource<1>;
+    }
 
     def VL        : ProcResource<1>; // Load sequencer
     def VS        : ProcResource<1>; // Store sequencer
@@ -217,13 +232,20 @@ multiclass SiFive7ProcResources {
 
   def PipeAB : ProcResGroup<[!cast<ProcResource>(NAME#"PipeA"),
                              !cast<ProcResource>(NAME#"PipeB")]>;
+
+  if extraVALU then
+  def VA1OrVA2 : ProcResGroup<[!cast<ProcResource>(NAME#"VA1"),
+                               !cast<ProcResource>(NAME#"VA2")]>;
 }
 
 multiclass SiFive7WriteResBase<int VLEN,
     ProcResourceKind PipeA, ProcResourceKind PipeB, ProcResourceKind PipeAB,
     ProcResourceKind IDiv, ProcResourceKind FDiv,
-    ProcResourceKind VA, ProcResourceKind VL, ProcResourceKind VS,
-    ProcResourceKind VCQ> {
+    ProcResourceKind VA1, ProcResourceKind VA1OrVA2,
+    ProcResourceKind VL, ProcResourceKind VS,
+    ProcResourceKind VCQ,
+    SiFive7FPLatencies fpLatencies,
+    bit isFP64Throttled = false> {
 
   // Branching
   let Latency = 3 in {
@@ -350,7 +372,7 @@ multiclass SiFive7WriteResBase<int VLEN,
   }
 
   // Half precision.
-  let Latency = 5 in {
+  let Latency = fpLatencies.BasicFP16ALU in {
   def : WriteRes<WriteFAdd16, [PipeB]>;
   def : WriteRes<WriteFMul16, [PipeB]>;
   def : WriteRes<WriteFMA16, [PipeB]>;
@@ -366,7 +388,7 @@ multiclass SiFive7WriteResBase<int VLEN,
   }
 
   // Single precision.
-  let Latency = 5 in {
+  let Latency = fpLatencies.BasicFP32ALU in {
     def : WriteRes<WriteFAdd32, [PipeB]>;
     def : WriteRes<WriteFMul32, [PipeB]>;
     def : WriteRes<WriteFMA32, [PipeB]>;
@@ -386,7 +408,7 @@ multiclass SiFive7WriteResBase<int VLEN,
   }
 
   // Double precision
-  let Latency = 7 in {
+  let Latency = fpLatencies.BasicFP64ALU in {
     def : WriteRes<WriteFAdd64, [PipeB]>;
     def : WriteRes<WriteFMul64, [PipeB]>;
     def : WriteRes<WriteFMA64, [PipeB]>;
@@ -624,43 +646,43 @@ multiclass SiFive7WriteResBase<int VLEN,
     defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
     let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVIALUV",     [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIALUX",     [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIALUI",     [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIALUV",     [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIALUX",     [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIALUI",     [VCQ, VA1OrVA2], mx, IsWorstCase>;
       // vmadc requires mask
-      defm : LMULWriteResMX<"WriteVICALUV",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVICALUX",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVICALUI",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVICALUMV",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVICALUMX",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVICALUMI",   [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVICALUV",    [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVICALUX",    [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVICALUI",    [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVICALUMV",   [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVICALUMX",   [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVICALUMI",   [VCQ, VA1], mx, IsWorstCase>;
       // min max require merge
-      defm : LMULWriteResMX<"WriteVIMinMaxV",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMinMaxX",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMergeV",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMergeX",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMergeI",   [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMinMaxV",  [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMinMaxX",  [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMergeV",   [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMergeX",   [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMergeI",   [VCQ, VA1], mx, IsWorstCase>;
 
-      defm : LMULWriteResMX<"WriteVIMovV",     [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMovX",     [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMovI",     [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMovV",     [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMovX",     [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMovI",     [VCQ, VA1OrVA2], mx, IsWorstCase>;
 
-      defm : LMULWriteResMX<"WriteVExtV",      [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVExtV",      [VCQ, VA1], mx, IsWorstCase>;
     }
     let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVShiftV",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVShiftX",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVShiftI",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMulV",     [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMulX",     [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMulAddV",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIMulAddX",  [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVShiftV",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVShiftX",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVShiftI",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMulV",     [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMulX",     [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMulAddV",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIMulAddX",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
     }
     // Mask results can't chain.
     let Latency = !add(Cycles, 3), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVICmpV",     [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVICmpX",     [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVICmpI",     [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVICmpV",     [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVICmpX",     [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVICmpI",     [VCQ, VA1], mx, IsWorstCase>;
     }
   }
 
@@ -670,8 +692,8 @@ multiclass SiFive7WriteResBase<int VLEN,
                            !div(SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c, 4));
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
       let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-        defm : LMULSEWWriteResMXSEW<"WriteVIDivV", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVIDivX", [VCQ, VA], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVIDivV", [VCQ, VA1], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVIDivX", [VCQ, VA1], mx, sew, IsWorstCase>;
       }
     }
   }
@@ -681,13 +703,13 @@ multiclass SiFive7WriteResBase<int VLEN,
     defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
     let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVIWALUV",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIWALUX",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIWALUI",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIWMulV",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIWMulX",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIWMulAddV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIWMulAddX", [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIWALUV",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIWALUX",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIWALUI",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIWMulV",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIWMulX",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIWMulAddV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIWMulAddX", [VCQ, VA1OrVA2], mx, IsWorstCase>;
     }
   }
   // Narrowing
@@ -695,9 +717,9 @@ multiclass SiFive7WriteResBase<int VLEN,
     defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
     let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVNShiftV",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVNShiftX",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVNShiftI",   [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVNShiftV",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVNShiftX",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVNShiftI",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
     }
   }
 
@@ -706,16 +728,16 @@ multiclass SiFive7WriteResBase<int VLEN,
     defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
     let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVSALUV",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVSALUX",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVSALUI",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVAALUV",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVAALUX",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVSMulV",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVSMulX",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVSShiftV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVSShiftX", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVSShiftI", [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSALUV",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSALUX",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSALUI",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVAALUV",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVAALUX",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSMulV",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSMulX",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSShiftV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSShiftX", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSShiftI", [VCQ, VA1OrVA2], mx, IsWorstCase>;
     }
   }
   // Narrowing
@@ -723,33 +745,38 @@ multiclass SiFive7WriteResBase<int VLEN,
     defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
     let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVNClipV",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVNClipX",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVNClipI",  [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVNClipV",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVNClipX",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVNClipI",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
     }
   }
 
   // 13. Vector Floating-Point Instructions
   foreach mx = SchedMxListF in {
     foreach sew = SchedSEWSet<mx, isF=1>.val in {
-      defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+      defvar Cycles = !if(!and(isFP64Throttled, !eq(sew, 64)),
+                          SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c,
+                          SiFive7GetCyclesDefault<mx>.c);
+      defvar Lat8 = !if(!and(isFP64Throttled, !eq(sew, 64)), Cycles, 8);
+      defvar VA = !if(!and(isFP64Throttled, !eq(sew, 64)), VA1, VA1OrVA2);
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
-      let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
+      let Latency = Lat8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
         defm : LMULSEWWriteResMXSEW<"WriteVFALUV",  [VCQ, VA], mx, sew, IsWorstCase>;
         defm : LMULSEWWriteResMXSEW<"WriteVFALUF",  [VCQ, VA], mx, sew, IsWorstCase>;
         defm : LMULSEWWriteResMXSEW<"WriteVFMulV",  [VCQ, VA], mx, sew, IsWorstCase>;
         defm : LMULSEWWriteResMXSEW<"WriteVFMulF",  [VCQ, VA], mx, sew, IsWorstCase>;
         defm : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [VCQ, VA], mx, sew, IsWorstCase>;
         defm : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFRecpV",   [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [VCQ, VA], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFRecpV",   [VCQ, VA1], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [VCQ, VA1], mx, sew, IsWorstCase>;
       }
-      let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
+      defvar Lat4 = !if(!and(isFP64Throttled, !eq(sew, 64)), Cycles, 4);
+      let Latency = Lat4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
         defm : LMULSEWWriteResMXSEW<"WriteVFSgnjV",   [VCQ, VA], mx, sew, IsWorstCase>;
         defm : LMULSEWWriteResMXSEW<"WriteVFSgnjF",   [VCQ, VA], mx, sew, IsWorstCase>;
         // min max require merge
-        defm : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [VCQ, VA], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [VCQ, VA1], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [VCQ, VA1], mx, sew, IsWorstCase>;
       }
     }
   }
@@ -757,18 +784,18 @@ multiclass SiFive7WriteResBase<int VLEN,
     defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
     let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVFCvtFToIV",  [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVFCvtFToIV",  [VCQ, VA1], mx, IsWorstCase>;
     }
     let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVFClassV",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVFMergeV",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVFMovV",      [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVFClassV",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVFMergeV",    [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVFMovV",      [VCQ, VA1OrVA2], mx, IsWorstCase>;
     }
     // Mask results can't chain.
     let Latency = !add(Cycles, 3), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
       // fcmp requires mask
-      defm : LMULWriteResMX<"WriteVFCmpV",      [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVFCmpF",      [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVFCmpV",      [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVFCmpF",      [VCQ, VA1], mx, IsWorstCase>;
     }
   }
   foreach mx = SchedMxListF in {
@@ -777,9 +804,9 @@ multiclass SiFive7WriteResBase<int VLEN,
                            !div(SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c, 4));
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
       let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-        defm : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFDivV",  [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFDivF",  [VCQ, VA], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [VCQ, VA1], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFDivV",  [VCQ, VA1], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFDivF",  [VCQ, VA1], mx, sew, IsWorstCase>;
       }
     }
   }
@@ -787,10 +814,12 @@ multiclass SiFive7WriteResBase<int VLEN,
   // Widening
   foreach mx = SchedMxListW in {
     foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
-      defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
+      defvar Cycles = !if(!and(isFP64Throttled, !eq(sew, 32)),
+                          SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c,
+                          SiFive7GetCyclesDefault<mx>.c);
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
       let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in
-      defm : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [VCQ, VA], mx, sew, IsWorstCase>;
+      defm : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [VCQ, VA1], mx, sew, IsWorstCase>;
     }
   }
   foreach mx = SchedMxListFW in {
@@ -798,37 +827,41 @@ multiclass SiFive7WriteResBase<int VLEN,
       defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
       let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-        defm : LMULSEWWriteResMXSEW<"WriteVFWALUV", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFWALUF", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFWMulV", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFWMulF", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [VCQ, VA], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFWALUV", [VCQ, VA1OrVA2], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFWALUF", [VCQ, VA1OrVA2], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFWMulV", [VCQ, VA1OrVA2], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFWMulF", [VCQ, VA1OrVA2], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [VCQ, VA1OrVA2], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [VCQ, VA1OrVA2], mx, sew, IsWorstCase>;
       }
-      defvar CvtCycles = SiFive7GetCyclesDefault<mx>.c;
+      defvar CvtCycles = !if(!and(isFP64Throttled, !eq(sew, 32)),
+                          SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c,
+                          SiFive7GetCyclesDefault<mx>.c);
       let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, CvtCycles)] in
-      defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [VCQ, VA], mx, sew, IsWorstCase>;
+      defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [VCQ, VA1], mx, sew, IsWorstCase>;
     }
     defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListFW>.c;
     let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in
-    defm : LMULWriteResMX<"WriteVFWCvtFToIV", [VCQ, VA], mx, IsWorstCase>;
+    defm : LMULWriteResMX<"WriteVFWCvtFToIV", [VCQ, VA1], mx, IsWorstCase>;
   }
   // Narrowing
   foreach mx = SchedMxListW in {
     defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxListW>.c;
     let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVFNCvtFToIV", [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVFNCvtFToIV", [VCQ, VA1], mx, IsWorstCase>;
     }
   }
   foreach mx = SchedMxListFW in {
     foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
-      defvar Cycles = SiFive7GetCyclesNarrowing<mx>.c;
+      defvar Cycles = !if(!and(isFP64Throttled, !eq(sew, 32)),
+                          SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c,
+                          SiFive7GetCyclesNarrowing<mx>.c);
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
       let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-        defm : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [VCQ, VA], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [VCQ, VA1], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [VCQ, VA1], mx, sew, IsWorstCase>;
       }
     }
   }
@@ -839,9 +872,9 @@ multiclass SiFive7WriteResBase<int VLEN,
       defvar Cycles = SiFive7GetReductionCycles<mx, sew, VLEN>.c;
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
       let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-        defm : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [VCQ, VA],
+        defm : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [VCQ, VA1],
                                        mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [VCQ, VA],
+        defm : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [VCQ, VA1],
                                        mx, sew, IsWorstCase>;
       }
     }
@@ -852,7 +885,7 @@ multiclass SiFive7WriteResBase<int VLEN,
       defvar Cycles = SiFive7GetReductionCycles<mx, sew, VLEN>.c;
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
       let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in
-      defm : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [VCQ, VA],
+      defm : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [VCQ, VA1],
                                      mx, sew, IsWorstCase>;
     }
   }
@@ -862,14 +895,14 @@ multiclass SiFive7WriteResBase<int VLEN,
       defvar RedCycles = SiFive7GetReductionCycles<mx, sew, VLEN>.c;
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
       let Latency = RedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, RedCycles)] in {
-        defm : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [VCQ, VA],
+        defm : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [VCQ, VA1],
                                        mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [VCQ, VA],
+        defm : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [VCQ, VA1],
                                        mx, sew, IsWorstCase>;
       }
       defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew, VLEN>.c;
       let Latency = OrdRedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, OrdRedCycles)] in
-      defm : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [VCQ, VA],
+      defm : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [VCQ, VA1],
                                      mx, sew, IsWorstCase>;
     }
   }
@@ -879,11 +912,11 @@ multiclass SiFive7WriteResBase<int VLEN,
       defvar RedCycles = SiFive7GetReductionCycles<mx, sew, VLEN>.c;
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
       let Latency = RedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, RedCycles)] in
-      defm : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [VCQ, VA],
+      defm : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [VCQ, VA1],
                                      mx, sew, IsWorstCase>;
       defvar OrdRedCycles = SiFive7GetOrderedReductionCycles<mx, sew, VLEN>.c;
       let Latency = OrdRedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, OrdRedCycles)] in
-      defm : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [VCQ, VA],
+      defm : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [VCQ, VA1],
                                      mx, sew, IsWorstCase>;
     }
   }
@@ -893,34 +926,34 @@ multiclass SiFive7WriteResBase<int VLEN,
     defvar Cycles = SiFive7GetCyclesVMask<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
     let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVMALUV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVMPopV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVMFFSV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVMSFSV", [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVMALUV", [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVMPopV", [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVMFFSV", [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVMSFSV", [VCQ, VA1], mx, IsWorstCase>;
     }
   }
   foreach mx = SchedMxList in {
     defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
     let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVIotaV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVIdxV", [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIotaV", [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVIdxV", [VCQ, VA1], mx, IsWorstCase>;
     }
   }
 
   // 16. Vector Permutation Instructions
   let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 1)] in {
-    def : WriteRes<WriteVMovSX, [VCQ, VA]>;
-    def : WriteRes<WriteVMovXS, [VCQ, VA]>;
-    def : WriteRes<WriteVMovSF, [VCQ, VA]>;
-    def : WriteRes<WriteVMovFS, [VCQ, VA]>;
+    def : WriteRes<WriteVMovSX, [VCQ, VA1OrVA2]>;
+    def : WriteRes<WriteVMovXS, [VCQ, VA1]>;
+    def : WriteRes<WriteVMovSF, [VCQ, VA1OrVA2]>;
+    def : WriteRes<WriteVMovFS, [VCQ, VA1]>;
   }
   foreach mx = SchedMxList in {
     defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
     let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVRGatherVX",    [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVRGatherVI",    [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVRGatherVX",    [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVRGatherVI",    [VCQ, VA1], mx, IsWorstCase>;
     }
   }
 
@@ -929,9 +962,9 @@ multiclass SiFive7WriteResBase<int VLEN,
       defvar Cycles = SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c;
       defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
       let Latency = !add(Cycles, 3), AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-        defm : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [VCQ, VA], mx, sew, IsWorstCase>;
-        defm : LMULSEWWriteResMXSEW<"WriteVCompressV", [VCQ, VA], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [VCQ, VA1], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [VCQ, VA1], mx, sew, IsWorstCase>;
+        defm : LMULSEWWriteResMXSEW<"WriteVCompressV", [VCQ, VA1], mx, sew, IsWorstCase>;
       }
     }
   }
@@ -940,23 +973,23 @@ multiclass SiFive7WriteResBase<int VLEN,
     defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
     let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVSlideUpX",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVSlideDownX", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVSlideI",     [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVISlide1X",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVFSlide1F",   [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSlideUpX",   [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSlideDownX", [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVSlideI",     [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVISlide1X",   [VCQ, VA1], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVFSlide1F",   [VCQ, VA1], mx, IsWorstCase>;
     }
   }
 
   // VMov*V is LMUL Aware
   let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 2)] in
-    def : WriteRes<WriteVMov1V,     [VCQ, VA]>;
+    def : WriteRes<WriteVMov1V,     [VCQ, VA1OrVA2]>;
   let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 4)] in
-    def : WriteRes<WriteVMov2V,     [VCQ, VA]>;
+    def : WriteRes<WriteVMov2V,     [VCQ, VA1OrVA2]>;
   let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 8)] in
-    def : WriteRes<WriteVMov4V,     [VCQ, VA]>;
+    def : WriteRes<WriteVMov4V,     [VCQ, VA1OrVA2]>;
   let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, 16)] in
-    def : WriteRes<WriteVMov8V,     [VCQ, VA]>;
+    def : WriteRes<WriteVMov8V,     [VCQ, VA1OrVA2]>;
 
   // Others
   def : WriteRes<WriteCSR, [PipeB]>;
@@ -982,37 +1015,37 @@ multiclass SiFive7WriteResBase<int VLEN,
     let Latency = Cycles,
         AcquireAtCycles = [0, 1],
         ReleaseAtCycles = [1, !add(1, Cycles)] in {
-      defm : LMULWriteResMX<"WriteVC_V_I",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_X",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_IV",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_VV",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_XV",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_IVV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_IVW", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_VVV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_VVW", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_XVV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_V_XVW", [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_I",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_X",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_IV",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_VV",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_XV",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_IVV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_IVW", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_VVV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_VVW", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_XVV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_V_XVW", [VCQ, VA1OrVA2], mx, IsWorstCase>;
       foreach f = ["FPR16", "FPR32", "FPR64"] in {
-        defm : LMULWriteResMX<"WriteVC_V_" # f # "V",  [VCQ, VA], mx, IsWorstCase>;
-        defm : LMULWriteResMX<"WriteVC_V_" # f # "VV", [VCQ, VA], mx, IsWorstCase>;
-        defm : LMULWriteResMX<"WriteVC_V_" # f # "VW", [VCQ, VA], mx, IsWorstCase>;
+        defm : LMULWriteResMX<"WriteVC_V_" # f # "V",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+        defm : LMULWriteResMX<"WriteVC_V_" # f # "VV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+        defm : LMULWriteResMX<"WriteVC_V_" # f # "VW", [VCQ, VA1OrVA2], mx, IsWorstCase>;
       }
-      defm : LMULWriteResMX<"WriteVC_I",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_X",   [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_IV",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_VV",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_XV",  [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_IVV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_IVW", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_VVV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_VVW", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_XVV", [VCQ, VA], mx, IsWorstCase>;
-      defm : LMULWriteResMX<"WriteVC_XVW", [VCQ, VA], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_I",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_X",   [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_IV",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_VV",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_XV",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_IVV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_IVW", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_VVV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_VVW", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_XVV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+      defm : LMULWriteResMX<"WriteVC_XVW", [VCQ, VA1OrVA2], mx, IsWorstCase>;
       foreach f = ["FPR16", "FPR32", "FPR64"] in {
-        defm : LMULWriteResMX<"WriteVC_" # f # "V",  [VCQ, VA], mx, IsWorstCase>;
-        defm : LMULWriteResMX<"WriteVC_" # f # "VV", [VCQ, VA], mx, IsWorstCase>;
-        defm : LMULWriteResMX<"WriteVC_" # f # "VW", [VCQ, VA], mx, IsWorstCase>;
+        defm : LMULWriteResMX<"WriteVC_" # f # "V",  [VCQ, VA1OrVA2], mx, IsWorstCase>;
+        defm : LMULWriteResMX<"WriteVC_" # f # "VV", [VCQ, VA1OrVA2], mx, IsWorstCase>;
+        defm : LMULWriteResMX<"WriteVC_" # f # "VW", [VCQ, VA1OrVA2], mx, IsWorstCase>;
       }
     }
   }
@@ -1308,8 +1341,10 @@ multiclass SiFive7ReadAdvance {
 /// This multiclass is a "bundle" of (1) processor resources (i.e. pipes) and
 /// (2) WriteRes entries. It's parameterized by config values that will
 /// eventually be supplied by different SchedMachineModels.
-multiclass SiFive7SchedResources<int vlen> {
-  defm SiFive7 : SiFive7ProcResources;
+multiclass SiFive7SchedResources<int vlen, bit extraVALU,
+                                 SiFive7FPLatencies fpLatencies,
+                                 bit isFP64Throttled> {
+  defm SiFive7 : SiFive7ProcResources<extraVALU>;
 
   // Pull out defs from SiFive7ProcResources so we can refer to them by name.
   defvar SiFive7PipeA = !cast<ProcResource>(NAME # SiFive7PipeA);
@@ -1317,6 +1352,13 @@ multiclass SiFive7SchedResources<int vlen> {
   defvar SiFive7PipeAB = !cast<ProcResGroup>(NAME # SiFive7PipeAB);
   defvar SiFive7IDiv = !cast<ProcResource>(NAME # SiFive7IDiv);
   defvar SiFive7FDiv = !cast<ProcResource>(NAME # SiFive7FDiv);
+  // Pass SiFive7VA for VA1 and VA1OrVA2 if there is only 1 VALU.
+  defvar SiFive7VA1 = !if (extraVALU,
+                            !cast<ProcResource>(NAME # SiFive7VA1),
+                            !cast<ProcResource>(NAME # SiFive7VA));
+  defvar SiFive7VA1OrVA2 = !if (extraVALU,
+                            !cast<ProcResGroup>(NAME # SiFive7VA1OrVA2),
+                            !cast<ProcResource>(NAME # SiFive7VA));
   defvar SiFive7VA = !cast<ProcResource>(NAME # SiFive7VA);
   defvar SiFive7VL = !cast<ProcResource>(NAME # SiFive7VL);
   defvar SiFive7VS = !cast<ProcResource>(NAME # SiFive7VS);
@@ -1326,9 +1368,9 @@ multiclass SiFive7SchedResources<int vlen> {
   // SchedModels.
   defm SiFive7
       : SiFive7WriteResBase<vlen, SiFive7PipeA, SiFive7PipeB, SiFive7PipeAB,
-                            SiFive7IDiv, SiFive7FDiv,
-                            SiFive7VA, SiFive7VL, SiFive7VS,
-                            SiFive7VCQ>;
+                            SiFive7IDiv, SiFive7FDiv, SiFive7VA1,
+                            SiFive7VA1OrVA2, SiFive7VL, SiFive7VS,
+                            SiFive7VCQ, fpLatencies, isFP64Throttled>;
 
   //===----------------------------------------------------------------------===//
   // Bypass and advance
@@ -1357,17 +1399,46 @@ class SiFive7SchedMachineModel<int vlen> : SchedMachineModel {
                              HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
                              HasStdExtZkr];
   int VLEN = vlen;
+  bit HasExtraVALU = false;
+
+  SiFive7FPLatencies FPLatencies;
+  bit IsFP64Throttled = false;
 
   string Name = !subst("Model", "", !subst("SiFive7", "", NAME));
 }
 
+/// Auxiliary config values.
+def SiFive7DefaultFPLatencies : SiFive7FPLatencies {
+  let BasicFP16ALU = 5;
+  let BasicFP32ALU = 5;
+  let BasicFP64ALU = 7;
+}
+
+def SiFive7LowFPLatencies : SiFive7FPLatencies {
+  let BasicFP16ALU = 4;
+  let BasicFP32ALU = 4;
+  let BasicFP64ALU = 4;
+}
+
 /// Models
-def SiFive7VLEN512Model : SiFive7SchedMachineModel<512>;
+def SiFive7VLEN512Model : SiFive7SchedMachineModel<512> {
+  let FPLatencies = SiFive7DefaultFPLatencies;
+}
+
+def SiFive7VLEN1024X300Model : SiFive7SchedMachineModel<1024> {
+  let HasExtraVALU = true;
+  let FPLatencies = SiFive7LowFPLatencies;
+  let IsFP64Throttled = true;
+}
 
 /// Binding models to their scheduling resources.
-let SchedModel = SiFive7VLEN512Model in
-defm !cast<string>(SiFive7VLEN512Model.Name)
-    : SiFive7SchedResources<SiFive7VLEN512Model.VLEN>;
+foreach model = [SiFive7VLEN512Model, SiFive7VLEN1024X300Model] in {
+  let SchedModel = model in
+  defm model.Name : SiFive7SchedResources<model.VLEN, model.HasExtraVALU,
+                                          model.FPLatencies,
+                                          model.IsFP64Throttled>;
+}
 
 // Some model name aliases.
 defvar SiFive7Model = SiFive7VLEN512Model;
+defvar SiFiveX390Model = SiFive7VLEN1024X300Model;
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/div-fdiv.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/div-fdiv.s
new file mode 100644
index 0000000000000..138f4023e448b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/div-fdiv.s
@@ -0,0 +1,54 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s \
+# RUN:   | FileCheck %s
+
+div a0, a1, a2
+fdiv.s f1, f2, f3
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      66    65.00                        66    VLEN1024X300SiFive7IDiv[65],VLEN1024X300SiFive7PipeAB,VLEN1024X300SiFive7PipeB DIV div	a0, a1, a2
+# CHECK-NEXT:  1      27    26.00                        27    VLEN1024X300SiFive7FDiv[26],VLEN1024X300SiFive7PipeAB,VLEN1024X300SiFive7PipeB FDIV_S fdiv.s	ft1, ft2, ft3
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT: 26.00  65.00   -     2.00    -      -      -      -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -     65.00   -     1.00    -      -      -      -      -     div	a0, a1, a2
+# CHECK-NEXT: 26.00   -      -     1.00    -      -      -      -      -     fdiv.s	ft1, ft2, ft3
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/fractional-lmul-data.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/fractional-lmul-data.s
new file mode 100644
index 0000000000000..3795f17fc1cdf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/fractional-lmul-data.s
@@ -0,0 +1,62 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s
+
+# TODO: This test should be replaced by an exhaustive test of legal (LMUL, SEW)
+# pairs for all instructions in the Vector Integer Arithmetic chapter of the RVV
+# SPEC.
+vsetvli zero, zero, e32, mf2, tu, mu
+vdiv.vv v12, v12, v12
+vsetvli zero, zero, e8, mf8, tu, mu
+vdiv.vv v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      112   112.00                       112   VLEN1024X300SiFive7VA1[1,113],VLEN1024X300SiFive7VA1OrVA2[1,113],VLEN1024X300SiFive7VCQ VDIV_VV vdiv.vv	v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      60    60.00                        60    VLEN1024X300SiFive7VA1[1,61],VLEN1024X300SiFive7VA1OrVA2[1,61],VLEN1024X300SiFive7VCQ VDIV_VV vdiv.vv	v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     2.00    -     174.00  -     2.00    -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     113.00  -     1.00    -      -     vdiv.vv	v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     61.00   -     1.00    -      -     vdiv.vv	v12, v12, v12
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/reductions.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/reductions.s
new file mode 100644
index 0000000000000..c1415f3e08e45
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/reductions.s
@@ -0,0 +1,678 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s
+
+# Single-Width Integer Reductions
+vsetvli zero, zero, e8, mf8, tu, mu
+vredsum.vs  v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vredsum.vs  v4, v8, v12
+vsetvli zero, zero, e8, mf2, tu, mu
+vredsum.vs  v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vredsum.vs  v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vredsum.vs  v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vredsum.vs  v4, v8, v12
+vsetvli zero, zero, e8, m8, tu, mu
+vredsum.vs  v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vredand.vs  v4, v8, v12
+vsetvli zero, zero, e16, mf2, tu, mu
+vredand.vs  v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vredand.vs  v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vredand.vs  v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vredand.vs  v4, v8, v12
+vsetvli zero, zero, e16, m8, tu, mu
+vredand.vs  v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vredor.vs   v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vredor.vs   v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vredor.vs   v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vredor.vs   v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vredor.vs   v4, v8, v12
+vsetvli zero, zero, e64, m1, tu, mu
+vredxor.vs  v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vredxor.vs  v4, v8, v12
+vsetvli zero, zero, e64, m4, tu, mu
+vredxor.vs  v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vredxor.vs  v4, v8, v12
+# Single-Width Integer Min/Max Reductions
+vsetvli zero, zero, e8, mf8, tu, mu
+vredmaxu.vs v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vredmaxu.vs v4, v8, v12
+vsetvli zero, zero, e8, mf2, tu, mu
+vredmaxu.vs v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vredmaxu.vs v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vredmaxu.vs v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vredmaxu.vs v4, v8, v12
+vsetvli zero, zero, e8, m8, tu, mu
+vredmaxu.vs v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, mf2, tu, mu
+vredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, m8, tu, mu
+vredmax.vs  v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vredminu.vs v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vredminu.vs v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vredminu.vs v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vredminu.vs v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vredminu.vs v4, v8, v12
+vsetvli zero, zero, e64, m1, tu, mu
+vredmin.vs  v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vredmin.vs  v4, v8, v12
+vsetvli zero, zero, e64, m4, tu, mu
+vredmin.vs  v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vredmin.vs  v4, v8, v12
+# Widening Integer Reductions
+vsetvli zero, zero, e8, mf8, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e8, mf2, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e8, m8, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e16, mf2, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e16, m8, tu, mu
+vwredsumu.vs v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vwredsum.vs  v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vwredsum.vs  v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vwredsum.vs  v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vwredsum.vs  v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vwredsum.vs  v4, v8, v12
+vsetvli zero, zero, e64, m1, tu, mu
+vwredsum.vs  v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vwredsum.vs  v4, v8, v12
+vsetvli zero, zero, e64, m4, tu, mu
+vwredsum.vs  v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vwredsum.vs  v4, v8, v12
+
+# Vector Single-Width FP Reduction Instructions
+# vfwredosum.vs
+# SEW will not be e8, or e64
+# LMUL will not be mf8
+vsetvli zero, zero, e16, mf4, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e16, mf2, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e16, m8, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vfwredosum.vs v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vfwredosum.vs v4, v8, v12
+# vfwredusum.vs
+vsetvli zero, zero, e16, mf4, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e16, mf2, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e16, m8, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vfwredusum.vs v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vfwredusum.vs v4, v8, v12
+
+# Single Width Floating Point Min/Max Reductions
+# SEW wont be e8
+# LMUL wont be mf8
+vsetvli zero, zero, e16, mf4, tu, mu
+vfredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, mf2, tu, mu
+vfredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vfredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vfredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vfredmax.vs  v4, v8, v12
+vsetvli zero, zero, e16, m8, tu, mu
+vfredmax.vs  v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vfredmin.vs  v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vfredmin.vs  v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vfredmin.vs  v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vfredmin.vs  v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vfredmin.vs  v4, v8, v12
+vsetvli zero, zero, e64, m1, tu, mu
+vfredmin.vs  v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vfredmin.vs  v4, v8, v12
+vsetvli zero, zero, e64, m4, tu, mu
+vfredmin.vs  v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vfredmin.vs  v4, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      52    52.00                        52    VLEN1024X300SiFive7VA1[1,53],VLEN1024X300SiFive7VA1OrVA2[1,53],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      54    54.00                        54    VLEN1024X300SiFive7VA1[1,55],VLEN1024X300SiFive7VA1OrVA2[1,55],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      58    58.00                        58    VLEN1024X300SiFive7VA1[1,59],VLEN1024X300SiFive7VA1OrVA2[1,59],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      66    66.00                        66    VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VREDSUM_VS vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      47    47.00                        47    VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      49    49.00                        49    VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      53    53.00                        53    VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      61    61.00                        61    VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VREDAND_VS vredand.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      41    41.00                        41    VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      42    42.00                        42    VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      44    44.00                        44    VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      48    48.00                        48    VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      56    56.00                        56    VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VREDOR_VS vredor.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      37    37.00                        37    VLEN1024X300SiFive7VA1[1,38],VLEN1024X300SiFive7VA1OrVA2[1,38],VLEN1024X300SiFive7VCQ VREDXOR_VS vredxor.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      39    39.00                        39    VLEN1024X300SiFive7VA1[1,40],VLEN1024X300SiFive7VA1OrVA2[1,40],VLEN1024X300SiFive7VCQ VREDXOR_VS vredxor.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      43    43.00                        43    VLEN1024X300SiFive7VA1[1,44],VLEN1024X300SiFive7VA1OrVA2[1,44],VLEN1024X300SiFive7VCQ VREDXOR_VS vredxor.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDXOR_VS vredxor.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      52    52.00                        52    VLEN1024X300SiFive7VA1[1,53],VLEN1024X300SiFive7VA1OrVA2[1,53],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      54    54.00                        54    VLEN1024X300SiFive7VA1[1,55],VLEN1024X300SiFive7VA1OrVA2[1,55],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      58    58.00                        58    VLEN1024X300SiFive7VA1[1,59],VLEN1024X300SiFive7VA1OrVA2[1,59],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      66    66.00                        66    VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VREDMAXU_VS vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      47    47.00                        47    VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      49    49.00                        49    VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      53    53.00                        53    VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      61    61.00                        61    VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VREDMAX_VS vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      41    41.00                        41    VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      42    42.00                        42    VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      44    44.00                        44    VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      48    48.00                        48    VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      56    56.00                        56    VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VREDMINU_VS vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      37    37.00                        37    VLEN1024X300SiFive7VA1[1,38],VLEN1024X300SiFive7VA1OrVA2[1,38],VLEN1024X300SiFive7VCQ VREDMIN_VS vredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      39    39.00                        39    VLEN1024X300SiFive7VA1[1,40],VLEN1024X300SiFive7VA1OrVA2[1,40],VLEN1024X300SiFive7VCQ VREDMIN_VS vredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      43    43.00                        43    VLEN1024X300SiFive7VA1[1,44],VLEN1024X300SiFive7VA1OrVA2[1,44],VLEN1024X300SiFive7VCQ VREDMIN_VS vredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VREDMIN_VS vredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      52    52.00                        52    VLEN1024X300SiFive7VA1[1,53],VLEN1024X300SiFive7VA1OrVA2[1,53],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      54    54.00                        54    VLEN1024X300SiFive7VA1[1,55],VLEN1024X300SiFive7VA1OrVA2[1,55],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      58    58.00                        58    VLEN1024X300SiFive7VA1[1,59],VLEN1024X300SiFive7VA1OrVA2[1,59],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      66    66.00                        66    VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      47    47.00                        47    VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      49    49.00                        49    VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      53    53.00                        53    VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      61    61.00                        61    VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VWREDSUMU_VS vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      41    41.00                        41    VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      42    42.00                        42    VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      44    44.00                        44    VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      48    48.00                        48    VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      56    56.00                        56    VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      66    66.00                        66    VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      66    66.00                        66    VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      66    66.00                        66    VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      66    66.00                        66    VLEN1024X300SiFive7VA1[1,67],VLEN1024X300SiFive7VA1OrVA2[1,67],VLEN1024X300SiFive7VCQ VWREDSUM_VS vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      96    96.00                        96    VLEN1024X300SiFive7VA1[1,97],VLEN1024X300SiFive7VA1OrVA2[1,97],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      192   192.00                       192   VLEN1024X300SiFive7VA1[1,193],VLEN1024X300SiFive7VA1OrVA2[1,193],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      384   384.00                       384   VLEN1024X300SiFive7VA1[1,385],VLEN1024X300SiFive7VA1OrVA2[1,385],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      768   768.00                       768   VLEN1024X300SiFive7VA1[1,769],VLEN1024X300SiFive7VA1OrVA2[1,769],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      1536  1536.00                      1536  VLEN1024X300SiFive7VA1[1,1537],VLEN1024X300SiFive7VA1OrVA2[1,1537],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      3072  3072.00                      3072  VLEN1024X300SiFive7VA1[1,3073],VLEN1024X300SiFive7VA1OrVA2[1,3073],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      96    96.00                        96    VLEN1024X300SiFive7VA1[1,97],VLEN1024X300SiFive7VA1OrVA2[1,97],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      192   192.00                       192   VLEN1024X300SiFive7VA1[1,193],VLEN1024X300SiFive7VA1OrVA2[1,193],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      384   384.00                       384   VLEN1024X300SiFive7VA1[1,385],VLEN1024X300SiFive7VA1OrVA2[1,385],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      768   768.00                       768   VLEN1024X300SiFive7VA1[1,769],VLEN1024X300SiFive7VA1OrVA2[1,769],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      1536  1536.00                      1536  VLEN1024X300SiFive7VA1[1,1537],VLEN1024X300SiFive7VA1OrVA2[1,1537],VLEN1024X300SiFive7VCQ VFWREDOSUM_VS vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      47    47.00                        47    VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      49    49.00                        49    VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      53    53.00                        53    VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      61    61.00                        61    VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      41    41.00                        41    VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      42    42.00                        42    VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      44    44.00                        44    VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      48    48.00                        48    VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      56    56.00                        56    VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VFWREDUSUM_VS vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      46    46.00                        46    VLEN1024X300SiFive7VA1[1,47],VLEN1024X300SiFive7VA1OrVA2[1,47],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      47    47.00                        47    VLEN1024X300SiFive7VA1[1,48],VLEN1024X300SiFive7VA1OrVA2[1,48],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      49    49.00                        49    VLEN1024X300SiFive7VA1[1,50],VLEN1024X300SiFive7VA1OrVA2[1,50],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      53    53.00                        53    VLEN1024X300SiFive7VA1[1,54],VLEN1024X300SiFive7VA1OrVA2[1,54],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      61    61.00                        61    VLEN1024X300SiFive7VA1[1,62],VLEN1024X300SiFive7VA1OrVA2[1,62],VLEN1024X300SiFive7VCQ VFREDMAX_VS vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      41    41.00                        41    VLEN1024X300SiFive7VA1[1,42],VLEN1024X300SiFive7VA1OrVA2[1,42],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      42    42.00                        42    VLEN1024X300SiFive7VA1[1,43],VLEN1024X300SiFive7VA1OrVA2[1,43],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      44    44.00                        44    VLEN1024X300SiFive7VA1[1,45],VLEN1024X300SiFive7VA1OrVA2[1,45],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      48    48.00                        48    VLEN1024X300SiFive7VA1[1,49],VLEN1024X300SiFive7VA1OrVA2[1,49],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      56    56.00                        56    VLEN1024X300SiFive7VA1[1,57],VLEN1024X300SiFive7VA1OrVA2[1,57],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      37    37.00                        37    VLEN1024X300SiFive7VA1[1,38],VLEN1024X300SiFive7VA1OrVA2[1,38],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      39    39.00                        39    VLEN1024X300SiFive7VA1[1,40],VLEN1024X300SiFive7VA1OrVA2[1,40],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      43    43.00                        43    VLEN1024X300SiFive7VA1[1,44],VLEN1024X300SiFive7VA1OrVA2[1,44],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      51    51.00                        51    VLEN1024X300SiFive7VA1[1,52],VLEN1024X300SiFive7VA1OrVA2[1,52],VLEN1024X300SiFive7VCQ VFREDMIN_VS vfredmin.vs	v4, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     103.00  -     13715.00  -   103.00  -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     53.00   -     1.00    -      -     vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     55.00   -     1.00    -      -     vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     59.00   -     1.00    -      -     vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     67.00   -     1.00    -      -     vredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vredand.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vredand.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     48.00   -     1.00    -      -     vredand.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     50.00   -     1.00    -      -     vredand.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     54.00   -     1.00    -      -     vredand.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     62.00   -     1.00    -      -     vredand.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     42.00   -     1.00    -      -     vredor.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     43.00   -     1.00    -      -     vredor.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     45.00   -     1.00    -      -     vredor.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     49.00   -     1.00    -      -     vredor.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     57.00   -     1.00    -      -     vredor.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     38.00   -     1.00    -      -     vredxor.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     40.00   -     1.00    -      -     vredxor.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     44.00   -     1.00    -      -     vredxor.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vredxor.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     53.00   -     1.00    -      -     vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     55.00   -     1.00    -      -     vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     59.00   -     1.00    -      -     vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     67.00   -     1.00    -      -     vredmaxu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     48.00   -     1.00    -      -     vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     50.00   -     1.00    -      -     vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     54.00   -     1.00    -      -     vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     62.00   -     1.00    -      -     vredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     42.00   -     1.00    -      -     vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     43.00   -     1.00    -      -     vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     45.00   -     1.00    -      -     vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     49.00   -     1.00    -      -     vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     57.00   -     1.00    -      -     vredminu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     38.00   -     1.00    -      -     vredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     40.00   -     1.00    -      -     vredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     44.00   -     1.00    -      -     vredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     53.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     55.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     59.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     67.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     48.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     50.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     54.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     62.00   -     1.00    -      -     vwredsumu.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     42.00   -     1.00    -      -     vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     43.00   -     1.00    -      -     vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     45.00   -     1.00    -      -     vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     49.00   -     1.00    -      -     vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     57.00   -     1.00    -      -     vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     67.00   -     1.00    -      -     vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     67.00   -     1.00    -      -     vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     67.00   -     1.00    -      -     vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     67.00   -     1.00    -      -     vwredsum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     97.00   -     1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     193.00  -     1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     385.00  -     1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     769.00  -     1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1537.00  -    1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     3073.00  -    1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     97.00   -     1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     193.00  -     1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     385.00  -     1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     769.00  -     1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1537.00  -    1.00    -      -     vfwredosum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     48.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     50.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     54.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     62.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     42.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     43.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     45.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     49.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     57.00   -     1.00    -      -     vfwredusum.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     47.00   -     1.00    -      -     vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     48.00   -     1.00    -      -     vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     50.00   -     1.00    -      -     vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     54.00   -     1.00    -      -     vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     62.00   -     1.00    -      -     vfredmax.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     42.00   -     1.00    -      -     vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     43.00   -     1.00    -      -     vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     45.00   -     1.00    -      -     vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     49.00   -     1.00    -      -     vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     57.00   -     1.00    -      -     vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     38.00   -     1.00    -      -     vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     40.00   -     1.00    -      -     vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     44.00   -     1.00    -      -     vfredmin.vs	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     52.00   -     1.00    -      -     vfredmin.vs	v4, v8, v12
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/strided-load-store.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/strided-load-store.s
new file mode 100644
index 0000000000000..129a33e13f64f
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/strided-load-store.s
@@ -0,0 +1,368 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e8, mf4, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e8, mf2, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e8, m1, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e8, m2, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+
+vsetvli zero, zero, e8, m4, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+
+vsetvli zero, zero, e8, m8, tu, mu
+vlse8.v  v1, (a1), a2
+
+vsetvli zero, zero, e16, mf4, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e16, mf2, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e16, m1, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e16, m2, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e16, m4, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+
+vsetvli zero, zero, e16, m8, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e32, m1, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e32, m2, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e32, m4, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e32, m8, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+
+vsetvli zero, zero, e64, m1, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e64, m2, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e64, m4, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vsetvli zero, zero, e64, m8, tu, mu
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE8_V           vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE16_V          vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE32_V          vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE64_V          vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      259   256.00  *                    259   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,257] VLSE8_V           vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      259   256.00  *                    259   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,257] VLSE16_V          vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      259   256.00  *                    259   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,257] VLSE32_V          vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      515   512.00  *                    515   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,513] VLSE8_V           vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      515   512.00  *                    515   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,513] VLSE16_V          vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      1027  1024.00 *                    1027  VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,1025] VLSE8_V          vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE8_V           vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE16_V          vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE32_V          vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE64_V          vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      259   256.00  *                    259   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,257] VLSE8_V           vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      259   256.00  *                    259   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,257] VLSE16_V          vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      259   256.00  *                    259   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,257] VLSE32_V          vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      515   512.00  *                    515   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,513] VLSE8_V           vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      515   512.00  *                    515   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,513] VLSE16_V          vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE8_V           vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE16_V          vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE32_V          vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE64_V          vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      259   256.00  *                    259   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,257] VLSE8_V           vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      259   256.00  *                    259   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,257] VLSE16_V          vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      259   256.00  *                    259   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,257] VLSE32_V          vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      67    64.00   *                    67    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,65] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE8_V           vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE16_V          vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE32_V          vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      131   128.00  *                    131   VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,129] VLSE64_V          vlse64.v	v1, (a1), a2
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     22.00   -      -      -     78.00  9294.00  -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   257.00  -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   257.00  -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   257.00  -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   513.00  -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   513.00  -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   1025.00  -    vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   257.00  -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   257.00  -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   257.00  -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   513.00  -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   513.00  -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   257.00  -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   257.00  -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   257.00  -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   65.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   129.00  -     vlse64.v	v1, (a1), a2
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/strided-load-x0.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/strided-load-x0.s
new file mode 100644
index 0000000000000..f1c25f7c76350
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/strided-load-x0.s
@@ -0,0 +1,132 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, m1, tu, mu
+
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vlse8.v  v1, (a1), zero
+vlse16.v v1, (a1), zero
+vlse32.v v1, (a1), zero
+vlse64.v v1, (a1), zero
+
+vle8.v  v1, (a1)
+vle16.v v1, (a1)
+vle32.v v1, (a1)
+vle64.v v1, (a1)
+
+vsetvli zero, zero, e64, m1, tu, mu
+
+vlse8.v  v1, (a1), a2
+vlse16.v v1, (a1), a2
+vlse32.v v1, (a1), a2
+vlse64.v v1, (a1), a2
+
+vlse8.v  v1, (a1), zero
+vlse16.v v1, (a1), zero
+vlse32.v v1, (a1), zero
+vlse64.v v1, (a1), zero
+
+vle8.v  v1, (a1)
+vle16.v v1, (a1)
+vle32.v v1, (a1)
+vle64.v v1, (a1)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE8_V            vlse8.v	v1, (a1), zero
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE16_V           vlse16.v	v1, (a1), zero
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE32_V           vlse32.v	v1, (a1), zero
+# CHECK-NEXT:  1      35    32.00   *                    35    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,33] VLSE64_V           vlse64.v	v1, (a1), zero
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a1)
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a1)
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE32_V             vle32.v	v1, (a1)
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE64_V             vle64.v	v1, (a1)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE8_V            vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE16_V           vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE32_V           vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE64_V           vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE8_V            vlse8.v	v1, (a1), zero
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE16_V           vlse16.v	v1, (a1), zero
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE32_V           vlse32.v	v1, (a1), zero
+# CHECK-NEXT:  1      19    16.00   *                    19    VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLSE64_V           vlse64.v	v1, (a1), zero
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a1)
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a1)
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE32_V             vle32.v	v1, (a1)
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE64_V             vle64.v	v1, (a1)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     2.00    -      -      -     24.00  421.00  -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse8.v	v1, (a1), zero
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse16.v	v1, (a1), zero
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse32.v	v1, (a1), zero
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   33.00   -     vlse64.v	v1, (a1), zero
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a1)
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a1)
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle32.v	v1, (a1)
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle64.v	v1, (a1)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse8.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse16.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse32.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse64.v	v1, (a1), a2
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse8.v	v1, (a1), zero
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse16.v	v1, (a1), zero
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse32.v	v1, (a1), zero
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vlse64.v	v1, (a1), zero
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a1)
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a1)
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle32.v	v1, (a1)
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle64.v	v1, (a1)
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s
new file mode 100644
index 0000000000000..e1e9b577b77f3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-fp.s
@@ -0,0 +1,4851 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s
+
+# The legal (SEW, LMUL) pairs for FP on sifive-x390 are:
+# (e16, mf4) (e16, mf2) (e16, m1) (e16, m2) (e16, m4) (e16, m8)
+# (e32, mf2) (e32, m1) (e32, m2) (e32, m4) (e32, m8)
+# (e64, m1) (e64, m2) (e64, m4) (e64, m8)
+# Widening instructions do not have e64
+
+# Vector Single-Width FP
+vsetvli zero, zero, e16, mf4, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, mf2, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, m1, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, m2, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, m4, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, m8, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, m1, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, m2, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, m4, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, m8, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e64, m1, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e64, m2, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e64, m4, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e64, m8, tu, mu
+vfadd.vv v8, v16, v24
+vfadd.vf v8, v16, f8
+vfsub.vv v8, v16, v24
+vfsub.vf v8, v16, f8
+vfrsub.vf v8, v16, f8
+vfmul.vv v8, v16, v24
+vfmul.vf v8, v16, f8
+vfdiv.vv v8, v16, v24
+vfdiv.vf v8, v16, f8
+vfrdiv.vf v8, v16, f8
+vfmacc.vv v8, v16, v24
+vfmacc.vf v8, f8, v24
+vfnmacc.vv v8, v16, v24
+vfnmacc.vf v8, f8, v24
+vfmsac.vv v8, v16, v24
+vfmsac.vf v8, f8, v24
+vfnmsac.vv v8, v16, v24
+vfnmsac.vf v8, f8, v24
+vfmadd.vv v8, v16, v24
+vfmadd.vf v8, f8, v24
+vfnmadd.vv v8, v16, v24
+vfnmadd.vf v8, f8, v24
+vfmsub.vv v8, v16, v24
+vfmsub.vf v8, f8, v24
+vfnmsub.vv v8, v16, v24
+vfnmsub.vf v8, f8, v24
+vfsqrt.v v8, v24
+vfrsqrt7.v v8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+# Vector Widening FP
+# no e64
+vsetvli zero, zero, e16, mf4, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, mf2, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, m1, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, m2, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
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+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
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+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
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+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, m4, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
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+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vsetvli zero, zero, e16, m8, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
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+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
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+vfwmacc.vf v8, f8, v24
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+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vsetvli zero, zero, e32, mf2, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
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+vfwmacc.vf v8, f8, v24
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+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vsetvli zero, zero, e32, m2, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
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+vfwmacc.vf v8, f8, v24
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+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vsetvli zero, zero, e32, m4, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vsetvli zero, zero, e32, m8, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
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+vfmin.vf v8, v16, f8
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+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e16, m8, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, mf2, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
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+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, m1, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, m2, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, m4, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+vsetvli zero, zero, e32, m8, tu, mu
+vfwadd.vv v8, v16, v24
+vfwadd.vf v8, v16, f8
+vfwsub.vv v8, v16, v24
+vfwsub.vf v8, v16, f8
+vfwadd.wv  v8, v16, v24
+vfwadd.wf  v8, v16, f8
+vfwsub.wv  v8, v16, v24
+vfwsub.wf  v8, v16, f8
+vfwmul.vv    v8, v16, v24
+vfwmul.vf    v8, v16, f8
+vfwmacc.vv v8, v16, v24
+vfwmacc.vf v8, f8, v24
+vfwnmacc.vv v8, v16, v24
+vfwnmacc.vf v8, f8, v24
+vfwmsac.vv v8, v16, v24
+vfwmsac.vf v8, f8, v24
+vfwnmsac.vv v8, v16, v24
+vfwnmsac.vf v8, f8, v24
+vfrec7.v v8, v24
+vfmin.vv v8, v16, v24
+vfmin.vf v8, v16, f8
+vfmax.vv v8, v16, v24
+vfmax.vf v8, v16, f8
+vfsgnj.vv v8, v16, v24
+vfsgnj.vf v8, v16, f8
+vfsgnjn.vv v8, v16, v24
+vfsgnjn.vf v8, v16, f8
+vfsgnjx.vv v8, v16, v24
+vfsgnjx.vf v8, v16, f8
+vfcvt.xu.f.v v8, v16
+vfcvt.x.f.v  v8, v16
+vfcvt.rtz.xu.f.v v8, v16
+vfcvt.rtz.x.f.v  v8, v16
+vfcvt.f.xu.v v8, v16
+vfcvt.f.x.v  v8, v16
+vfwcvt.xu.f.v v8, v16
+vfwcvt.x.f.v  v8, v16
+vfwcvt.rtz.xu.f.v v8, v16
+vfwcvt.rtz.x.f.v  v8, v16
+vfwcvt.f.xu.v v8, v16
+vfwcvt.f.x.v  v8, v16
+vfwcvt.f.f.v v8, v16
+vfncvt.xu.f.w v8, v16
+vfncvt.x.f.w  v8, v16
+vfncvt.rtz.xu.f.w v8, v16
+vfncvt.rtz.x.f.w  v8, v16
+vfncvt.f.xu.w v8, v16
+vfncvt.f.x.w  v8, v16
+vfncvt.f.f.w v8, v16
+vfncvt.rod.f.f.w v8, v16
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFADD_VV      vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFADD_VF      vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSUB_VV      vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSUB_VF      vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFRSUB_VF     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMUL_VV      vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMUL_VF      vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      60    60.00                        60    VLEN1024X300SiFive7VA1[1,61],VLEN1024X300SiFive7VA1OrVA2[1,61],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      60    60.00                        60    VLEN1024X300SiFive7VA1[1,61],VLEN1024X300SiFive7VA1OrVA2[1,61],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      60    60.00                        60    VLEN1024X300SiFive7VA1[1,61],VLEN1024X300SiFive7VA1OrVA2[1,61],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      60    60.00                        60    VLEN1024X300SiFive7VA1[1,61],VLEN1024X300SiFive7VA1OrVA2[1,61],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFADD_VV      vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFADD_VF      vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSUB_VV      vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSUB_VF      vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFRSUB_VF     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMUL_VV      vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMUL_VF      vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      120   120.00                       120   VLEN1024X300SiFive7VA1[1,121],VLEN1024X300SiFive7VA1OrVA2[1,121],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      120   120.00                       120   VLEN1024X300SiFive7VA1[1,121],VLEN1024X300SiFive7VA1OrVA2[1,121],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      120   120.00                       120   VLEN1024X300SiFive7VA1[1,121],VLEN1024X300SiFive7VA1OrVA2[1,121],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      120   120.00                       120   VLEN1024X300SiFive7VA1[1,121],VLEN1024X300SiFive7VA1OrVA2[1,121],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFADD_VV      vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFADD_VF      vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSUB_VV      vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSUB_VF      vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFRSUB_VF     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMUL_VV      vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMUL_VF      vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      240   240.00                       240   VLEN1024X300SiFive7VA1[1,241],VLEN1024X300SiFive7VA1OrVA2[1,241],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      240   240.00                       240   VLEN1024X300SiFive7VA1[1,241],VLEN1024X300SiFive7VA1OrVA2[1,241],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      240   240.00                       240   VLEN1024X300SiFive7VA1[1,241],VLEN1024X300SiFive7VA1OrVA2[1,241],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      240   240.00                       240   VLEN1024X300SiFive7VA1[1,241],VLEN1024X300SiFive7VA1OrVA2[1,241],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFADD_VV      vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFADD_VF      vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSUB_VV      vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSUB_VF      vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFRSUB_VF     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMUL_VV      vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMUL_VF      vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      480   480.00                       480   VLEN1024X300SiFive7VA1[1,481],VLEN1024X300SiFive7VA1OrVA2[1,481],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      480   480.00                       480   VLEN1024X300SiFive7VA1[1,481],VLEN1024X300SiFive7VA1OrVA2[1,481],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      480   480.00                       480   VLEN1024X300SiFive7VA1[1,481],VLEN1024X300SiFive7VA1OrVA2[1,481],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      480   480.00                       480   VLEN1024X300SiFive7VA1[1,481],VLEN1024X300SiFive7VA1OrVA2[1,481],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFADD_VV      vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFADD_VF      vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSUB_VV      vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSUB_VF      vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFRSUB_VF     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMUL_VV      vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMUL_VF      vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      960   960.00                       960   VLEN1024X300SiFive7VA1[1,961],VLEN1024X300SiFive7VA1OrVA2[1,961],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      960   960.00                       960   VLEN1024X300SiFive7VA1[1,961],VLEN1024X300SiFive7VA1OrVA2[1,961],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      960   960.00                       960   VLEN1024X300SiFive7VA1[1,961],VLEN1024X300SiFive7VA1OrVA2[1,961],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      960   960.00                       960   VLEN1024X300SiFive7VA1[1,961],VLEN1024X300SiFive7VA1OrVA2[1,961],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFADD_VV     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFADD_VF     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSUB_VV     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSUB_VF     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFRSUB_VF    vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMUL_VV     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMUL_VF     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      1920  1920.00                      1920  VLEN1024X300SiFive7VA1[1,1921],VLEN1024X300SiFive7VA1OrVA2[1,1921],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      1920  1920.00                      1920  VLEN1024X300SiFive7VA1[1,1921],VLEN1024X300SiFive7VA1OrVA2[1,1921],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      1920  1920.00                      1920  VLEN1024X300SiFive7VA1[1,1921],VLEN1024X300SiFive7VA1OrVA2[1,1921],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VV    vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VF    vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VV   vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VF   vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VV    vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VF    vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VV   vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VF   vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VV    vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VF    vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VV   vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VF   vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VV    vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VF    vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VV   vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VF   vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      1920  1920.00                      1920  VLEN1024X300SiFive7VA1[1,1921],VLEN1024X300SiFive7VA1OrVA2[1,1921],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VV    vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VF    vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VV   vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VF   vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VV   vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VF   vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFADD_VV      vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFADD_VF      vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSUB_VV      vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSUB_VF      vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFRSUB_VF     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMUL_VV      vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMUL_VF      vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      112   112.00                       112   VLEN1024X300SiFive7VA1[1,113],VLEN1024X300SiFive7VA1OrVA2[1,113],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      112   112.00                       112   VLEN1024X300SiFive7VA1[1,113],VLEN1024X300SiFive7VA1OrVA2[1,113],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      112   112.00                       112   VLEN1024X300SiFive7VA1[1,113],VLEN1024X300SiFive7VA1OrVA2[1,113],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      112   112.00                       112   VLEN1024X300SiFive7VA1[1,113],VLEN1024X300SiFive7VA1OrVA2[1,113],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFADD_VV      vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFADD_VF      vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSUB_VV      vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSUB_VF      vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFRSUB_VF     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMUL_VV      vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMUL_VF      vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      224   224.00                       224   VLEN1024X300SiFive7VA1[1,225],VLEN1024X300SiFive7VA1OrVA2[1,225],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      224   224.00                       224   VLEN1024X300SiFive7VA1[1,225],VLEN1024X300SiFive7VA1OrVA2[1,225],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      224   224.00                       224   VLEN1024X300SiFive7VA1[1,225],VLEN1024X300SiFive7VA1OrVA2[1,225],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      224   224.00                       224   VLEN1024X300SiFive7VA1[1,225],VLEN1024X300SiFive7VA1OrVA2[1,225],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFADD_VV      vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFADD_VF      vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSUB_VV      vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSUB_VF      vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFRSUB_VF     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMUL_VV      vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMUL_VF      vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      448   448.00                       448   VLEN1024X300SiFive7VA1[1,449],VLEN1024X300SiFive7VA1OrVA2[1,449],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      448   448.00                       448   VLEN1024X300SiFive7VA1[1,449],VLEN1024X300SiFive7VA1OrVA2[1,449],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      448   448.00                       448   VLEN1024X300SiFive7VA1[1,449],VLEN1024X300SiFive7VA1OrVA2[1,449],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      448   448.00                       448   VLEN1024X300SiFive7VA1[1,449],VLEN1024X300SiFive7VA1OrVA2[1,449],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFADD_VV      vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFADD_VF      vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSUB_VV      vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSUB_VF      vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFRSUB_VF     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMUL_VV      vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMUL_VF      vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      896   896.00                       896   VLEN1024X300SiFive7VA1[1,897],VLEN1024X300SiFive7VA1OrVA2[1,897],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      896   896.00                       896   VLEN1024X300SiFive7VA1[1,897],VLEN1024X300SiFive7VA1OrVA2[1,897],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      896   896.00                       896   VLEN1024X300SiFive7VA1[1,897],VLEN1024X300SiFive7VA1OrVA2[1,897],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      896   896.00                       896   VLEN1024X300SiFive7VA1[1,897],VLEN1024X300SiFive7VA1OrVA2[1,897],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFADD_VV     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFADD_VF     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSUB_VV     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSUB_VF     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFRSUB_VF    vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMUL_VV     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMUL_VF     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      1792  1792.00                      1792  VLEN1024X300SiFive7VA1[1,1793],VLEN1024X300SiFive7VA1OrVA2[1,1793],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      1792  1792.00                      1792  VLEN1024X300SiFive7VA1[1,1793],VLEN1024X300SiFive7VA1OrVA2[1,1793],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      1792  1792.00                      1792  VLEN1024X300SiFive7VA1[1,1793],VLEN1024X300SiFive7VA1OrVA2[1,1793],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VV    vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VF    vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VV   vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VF   vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VV    vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VF    vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VV   vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VF   vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VV    vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VF    vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VV   vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VF   vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VV    vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VF    vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VV   vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VF   vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      1792  1792.00                      1792  VLEN1024X300SiFive7VA1[1,1793],VLEN1024X300SiFive7VA1OrVA2[1,1793],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VV    vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VF    vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VV   vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VF   vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VV   vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VF   vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFADD_VV vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFADD_VF vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSUB_VV vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSUB_VF vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFRSUB_VF vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMUL_VV vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMUL_VF vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      228   228.00                       228   VLEN1024X300SiFive7VA1[1,229],VLEN1024X300SiFive7VA1OrVA2[1,229],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      228   228.00                       228   VLEN1024X300SiFive7VA1[1,229],VLEN1024X300SiFive7VA1OrVA2[1,229],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      228   228.00                       228   VLEN1024X300SiFive7VA1[1,229],VLEN1024X300SiFive7VA1OrVA2[1,229],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      228   228.00                       228   VLEN1024X300SiFive7VA1[1,229],VLEN1024X300SiFive7VA1OrVA2[1,229],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VV vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VF vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VV vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VF vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VV vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VF vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      16    16.00                        16    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFADD_VV vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFADD_VF vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFSUB_VV vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFSUB_VF vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFRSUB_VF vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMUL_VV vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMUL_VF vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      456   456.00                       456   VLEN1024X300SiFive7VA1[1,457],VLEN1024X300SiFive7VA1OrVA2[1,457],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      456   456.00                       456   VLEN1024X300SiFive7VA1[1,457],VLEN1024X300SiFive7VA1OrVA2[1,457],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      456   456.00                       456   VLEN1024X300SiFive7VA1[1,457],VLEN1024X300SiFive7VA1OrVA2[1,457],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      456   456.00                       456   VLEN1024X300SiFive7VA1[1,457],VLEN1024X300SiFive7VA1OrVA2[1,457],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFSGNJ_VV vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFSGNJ_VF vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFSGNJN_VV vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFSGNJN_VF vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFSGNJX_VV vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFSGNJX_VF vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      32    32.00                        32    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFADD_VV vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFADD_VF vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFSUB_VV vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFSUB_VF vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFRSUB_VF vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMUL_VV vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMUL_VF vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      912   912.00                       912   VLEN1024X300SiFive7VA1[1,913],VLEN1024X300SiFive7VA1OrVA2[1,913],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      912   912.00                       912   VLEN1024X300SiFive7VA1[1,913],VLEN1024X300SiFive7VA1OrVA2[1,913],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      912   912.00                       912   VLEN1024X300SiFive7VA1[1,913],VLEN1024X300SiFive7VA1OrVA2[1,913],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMACC_VV     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMACC_VF     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMACC_VV    vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMACC_VF    vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSAC_VV     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSAC_VF     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSAC_VV    vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSAC_VF    vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMADD_VV     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMADD_VF     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMADD_VV    vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMADD_VF    vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSUB_VV     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMSUB_VF     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSUB_VV    vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNMSUB_VF    vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      912   912.00                       912   VLEN1024X300SiFive7VA1[1,913],VLEN1024X300SiFive7VA1OrVA2[1,913],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFSGNJ_VV vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFSGNJ_VF vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFSGNJN_VV vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFSGNJN_VF vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFSGNJX_VV vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFSGNJX_VF vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      64    64.00                        64    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFADD_VV vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFADD_VF vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFSUB_VV vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFSUB_VF vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFRSUB_VF vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMUL_VV vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMUL_VF vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      1824  1824.00                      1824  VLEN1024X300SiFive7VA1[1,1825],VLEN1024X300SiFive7VA1OrVA2[1,1825],VLEN1024X300SiFive7VCQ VFDIV_VV vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  1      1824  1824.00                      1824  VLEN1024X300SiFive7VA1[1,1825],VLEN1024X300SiFive7VA1OrVA2[1,1825],VLEN1024X300SiFive7VCQ VFDIV_VF vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      1824  1824.00                      1824  VLEN1024X300SiFive7VA1[1,1825],VLEN1024X300SiFive7VA1OrVA2[1,1825],VLEN1024X300SiFive7VCQ VFRDIV_VF vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VV    vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMACC_VF    vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VV   vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMACC_VF   vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VV    vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSAC_VF    vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VV   vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSAC_VF   vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VV    vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMADD_VF    vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VV   vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMADD_VF   vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VV    vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMSUB_VF    vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VV   vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNMSUB_VF   vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  1      1824  1824.00                      1824  VLEN1024X300SiFive7VA1[1,1825],VLEN1024X300SiFive7VA1OrVA2[1,1825],VLEN1024X300SiFive7VCQ VFSQRT_V vfsqrt.v	v8, v24
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFRSQRT7_V vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFSGNJ_VV vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFSGNJ_VF vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFSGNJN_VV vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFSGNJN_VF vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFSGNJX_VV vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFSGNJX_VF vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      128   128.00                       128   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VV    vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VF    vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VV   vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VF   vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VV   vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VF   vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VV    vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VF    vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VV   vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VF   vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VV   vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VF   vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     32.00                        8     VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     64.00                        8     VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJ_VV     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJ_VF     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJN_VV    vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJN_VF    vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJX_VV    vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFSGNJX_VF    vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     128.00                       8     VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VV     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_VF     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VV     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_VF     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WV     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWADD_WF     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WV     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWSUB_WF     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VV     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMUL_VF     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VV    vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMACC_VF    vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VV   vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMACC_VF   vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VV    vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWMSAC_VF    vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VV   vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWNMSAC_VF   vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFREC7_V vfrec7.v	v8, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VV vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMIN_VF vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VV vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFMAX_VF vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VV    vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJ_VF    vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VV   vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJN_VF   vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VV   vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFSGNJX_VF   vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_XU_F_V vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_X_F_V vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_XU_F_V vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_RTZ_X_F_V vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_XU_V vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFCVT_F_X_V vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_XU_F_V vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_X_F_V vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_XU_F_V vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_RTZ_X_F_V vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_XU_V vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_X_V vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VFWCVT_F_F_V vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_XU_F_W vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_X_F_W vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_XU_F_W vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_RTZ_X_F_W vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_XU_W vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_X_W vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_F_F_W vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  1      8     16.00                        8     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VFNCVT_ROD_F_F_W vfncvt.rod.f.f.w	v8, v16
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     32.00   -     58006.00 2446.00 1558.00  -   -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     61.00   -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     61.00   -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     61.00   -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     61.00   -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     121.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     121.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     121.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     121.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     241.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     241.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     241.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     241.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     481.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     481.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     481.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     481.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     961.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     961.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     961.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     961.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1921.00  -    1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1921.00  -    1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1921.00  -    1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1921.00  -    1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     113.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     113.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     113.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     113.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     225.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     225.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     225.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     225.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     449.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     449.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     449.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     449.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     897.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     897.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     897.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     897.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1793.00  -    1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1793.00  -    1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1793.00  -    1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1793.00  -    1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     229.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     229.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     229.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     229.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     457.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     457.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     457.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     457.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     913.00  -     1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     913.00  -     1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     913.00  -     1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     913.00  -     1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfrsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1825.00  -    1.00    -      -     vfdiv.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1825.00  -    1.00    -      -     vfdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1825.00  -    1.00    -      -     vfrdiv.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmadd.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfnmsub.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1825.00  -    1.00    -      -     vfsqrt.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrsqrt7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwadd.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwsub.wf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmul.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmacc.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vfwnmsac.vf	v8, fs0, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfrec7.v	v8, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmin.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfmax.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnj.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjn.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vfsgnjx.vf	v8, v16, fs0
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.xu.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.rtz.x.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.xu.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.x.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vfwcvt.f.f.v	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.xu.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rtz.x.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.xu.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.x.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.f.f.w	v8, v16
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vfncvt.rod.f.f.w	v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-integer-arithmetic.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-integer-arithmetic.s
new file mode 100644
index 0000000000000..8e5de00c48e06
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vector-integer-arithmetic.s
@@ -0,0 +1,2272 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s
+
+# The legal (SEW, LMUL) pairs are:
+# (e8, mf8) (e8, mf4) (e8, mf2) (e8, m1) (e8, m2) (e8, m4) (e8, m8)
+# (e16, mf4) (e16, mf2) (e16, m1) (e16, m2) (e16, m4) (e16, m8)
+# (e32, mf2) (e32, m1) (e32, m2) (e32, m4) (e32, m8)
+# (e64, m1) (e64, m2) (e64, m4) (e64, m8)
+# Widening instructions do not have e64
+# Narrowing instructions do not have e8
+
+# Vector Single-Width Integer Add and Subtract
+vsetvli zero, zero, e8, mf8, tu, mu
+vadd.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vadd.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vadd.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vsub.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vsub.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vrsub.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vrsub.vi v4, v8, 0
+vsetvli zero, zero, e16, mf4, tu, mu
+vadd.vv v4, v8, v12
+vsetvli zero, zero, e16, mf2, tu, mu
+vadd.vx v4, v8, x10
+vsetvli zero, zero, e16, m1, tu, mu
+vadd.vi v4, v8, 0
+vsetvli zero, zero, e16, m2, tu, mu
+vsub.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vsub.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vrsub.vx v4, v8, x10
+vsetvli zero, zero, e32, mf2, tu, mu
+vrsub.vi v4, v8, 0
+vsetvli zero, zero, e32, m1, tu, mu
+vadd.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vadd.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vadd.vi v4, v8, 0
+vsetvli zero, zero, e32, m8, tu, mu
+vsub.vv v4, v8, v12
+vsetvli zero, zero, e64, m1, tu, mu
+vsub.vx v4, v8, x10
+vsetvli zero, zero, e64, m2, tu, mu
+vrsub.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vrsub.vi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vadd.vv v4, v8, v12
+
+# Vector Widening Integer Add/Subtract
+# no e64
+vsetvli zero, zero, e8, mf8, tu, mu
+vwaddu.vv  v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vwaddu.vx  v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vwsubu.vv  v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vwsubu.vx  v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vwadd.vv  v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vwadd.vx  v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vwsub.vv  v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vwsub.vx  v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vwaddu.wv  v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vwaddu.wx  v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vwsubu.wv  v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vwsubu.wx  v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vwadd.wv  v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vwadd.wx  v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vwsub.wv  v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vwsub.wx  v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vwaddu.vv  v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vwaddu.vx  v4, v8, x10
+
+# Vector Integer Extension
+# no e8
+vsetvli zero, zero, e16, mf4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, mf2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m1, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e16, m8, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vsetvli zero, zero, e32, mf2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m1, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e32, m8, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vsetvli zero, zero, e64, m1, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+vsetvli zero, zero, e64, m2, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+vsetvli zero, zero, e64, m4, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+vsetvli zero, zero, e64, m8, tu, mu
+vzext.vf2 v4, v8
+vsext.vf2 v4, v8
+vzext.vf4 v4, v8
+vsext.vf4 v4, v8
+vzext.vf8 v4, v8
+vsext.vf8 v4, v8
+
+# Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vadc.vvm   v4, v8, v12, v0
+vsetvli zero, zero, e8, mf4, tu, mu
+vadc.vxm   v4, v8, x10, v0
+vsetvli zero, zero, e8, mf2, tu, mu
+vadc.vim   v4, v8, 0, v0
+vsetvli zero, zero, e8, m1, tu, mu
+vmadc.vvm   v4, v8, v12, v0
+vsetvli zero, zero, e8, m2, tu, mu
+vmadc.vxm   v4, v8, x10, v0
+vsetvli zero, zero, e8, m4, tu, mu
+vmadc.vim   v4, v8, 0, v0
+vsetvli zero, zero, e8, m8, tu, mu
+vmadc.vv    v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmadc.vx    v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmadc.vi    v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vsbc.vvm   v4, v8, v12, v0
+vsetvli zero, zero, e16, m2, tu, mu
+vsbc.vxm   v4, v8, x10, v0
+vsetvli zero, zero, e16, m4, tu, mu
+vmsbc.vvm   v4, v8, v12, v0
+vsetvli zero, zero, e16, m8, tu, mu
+vmsbc.vxm   v4, v8, x10, v0
+vsetvli zero, zero, e32, mf2, tu, mu
+vmsbc.vv    v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vmsbc.vx    v4, v8, x10
+vsetvli zero, zero, e32, m2, tu, mu
+vadc.vvm   v4, v8, v12, v0
+vsetvli zero, zero, e32, m4, tu, mu
+vadc.vxm   v4, v8, x10, v0
+vsetvli zero, zero, e32, m8, tu, mu
+vadc.vim   v4, v8, 0, v0
+vsetvli zero, zero, e64, m1, tu, mu
+vmadc.vvm   v4, v8, v12, v0
+vsetvli zero, zero, e64, m2, tu, mu
+vmadc.vxm   v4, v8, x10, v0
+vsetvli zero, zero, e64, m4, tu, mu
+vmadc.vim   v4, v8, 0, v0
+vsetvli zero, zero, e64, m8, tu, mu
+vmadc.vv    v4, v8, v12
+
+# Vector Bitwise Logical Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vand.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vand.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vand.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vor.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vor.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vor.vi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vxor.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vxor.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vxor.vi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vand.vv v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vand.vx v4, v8, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vand.vi v4, v8, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vor.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vor.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vor.vi v4, v8, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vxor.vv v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vxor.vx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vxor.vi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vand.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vand.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vand.vi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vor.vv v4, v8, v12
+
+# Vector Single-Width Shift Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vsll.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vsll.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vsll.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vsrl.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vsrl.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vsrl.vi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vsra.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vsra.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vsra.vi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vsll.vv v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vsll.vx v4, v8, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vsll.vi v4, v8, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vsrl.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vsrl.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vsrl.vi v4, v8, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vsra.vv v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vsra.vx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vsra.vi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vsll.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vsll.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vsll.vi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vsrl.vv v4, v8, v12
+
+# Vector Narrowing Integer Right Shift Instructions
+# no e8
+vsetvli zero, zero, e8, mf8, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vnsra.wv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vnsra.wx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vnsra.wi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vnsra.wv v4, v8, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vnsra.wx v4, v8, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vnsra.wi v4, v8, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vnsra.wv v4, v8, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vnsra.wx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vnsra.wi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vnsrl.wv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vnsrl.wx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vnsrl.wi v4, v8, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vnsra.wv v4, v8, v12
+
+# Vector Integer Compare Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmseq.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vmseq.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmseq.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vmsne.vv v4, v8, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vmsne.vx v4, v8, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vmsne.vi v4, v8, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vmsltu.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmsltu.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmslt.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vmslt.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vmsleu.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vmsleu.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vmsleu.vi v4, v8, 0
+vsetvli zero, zero, e32, mf2, tu, mu
+vmsle.vv v4, v8, v12
+vsetvli zero, zero, e32, m1, tu, mu
+vmsle.vx v4, v8, x10
+vsetvli zero, zero, e32, m2, tu, mu
+vmsle.vi v4, v8, 0
+vsetvli zero, zero, e32, m4, tu, mu
+vmsgtu.vx v4, v8, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vmsgtu.vi v4, v8, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vmsgt.vx v4, v8, x10
+vsetvli zero, zero, e64, m2, tu, mu
+vmsgt.vi v4, v8, 0
+vsetvli zero, zero, e64, m4, tu, mu
+vmseq.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vmseq.vx v4, v8, x10
+
+# Pseudo instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmslt.vi v4, v8, 1
+vsetvli zero, zero, e8, mf4, tu, mu
+vmsltu.vi v4, v8, 1
+vsetvli zero, zero, e8, mf2, tu, mu
+vmsltu.vi v4, v8, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vmsgeu.vi v4, v8, 1
+vsetvli zero, zero, e8, m2, tu, mu
+vmsge.vi v4, v8, 1
+vsetvli zero, zero, e8, m4, tu, mu
+vmsgeu.vi v4, v8, 0
+vsetvli zero, zero, e16, mf4, tu, mu
+vmsge.vi v4, v8, 0
+vsetvli zero, zero, e16, mf2, tu, mu
+vmsge.vx v4, v8, x10
+vsetvli zero, zero, e16, m1, tu, mu
+vmsgeu.vx v4, v8, x11
+
+# Vector Integer Min/Max Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vminu.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vminu.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmin.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vmin.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vmaxu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vmaxu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vmax.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmax.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vminu.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vminu.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vmin.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vmin.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vmaxu.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vmaxu.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vmax.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vmax.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vminu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vminu.vx v4, v8, x10
+vsetvli zero, zero, e64, m1, tu, mu
+vmin.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vmin.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vmaxu.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vmaxu.vx v4, v8, x10
+
+# Vector Single-Width Integer Multiply Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmul.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vmul.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmulh.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vmulh.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vmulhu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vmulhu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vmulhsu.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmulhsu.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmul.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vmul.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vmulh.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vmulh.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vmulhu.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vmulhu.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vmulhsu.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vmulhsu.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vmul.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vmul.vx v4, v8, x10
+vsetvli zero, zero, e64, m1, tu, mu
+vmulh.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vmulh.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vmulhu.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vmulhu.vx v4, v8, x10
+
+# Vector Integer Divide Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vdivu.vv v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vdivu.vx v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vdiv.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vremu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vremu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vrem.vv v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vrem.vx v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vdivu.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vdivu.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vdiv.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vdiv.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vremu.vv v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vremu.vx v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vrem.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vrem.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vdivu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vdivu.vx v4, v8, x10
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vv v4, v8, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vdiv.vx v4, v8, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vremu.vv v4, v8, v12
+vsetvli zero, zero, e64, m8, tu, mu
+vremu.vx v4, v8, x10
+
+# Vector Widening Integer Multiply Instructions
+# no e64
+vsetvli zero, zero, e8, mf8, tu, mu
+vwmul.vv  v4, v8, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vwmul.vx  v4, v8, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vwmulu.vv v4, v8, v12
+vsetvli zero, zero, e8, m1, tu, mu
+vwmulu.vx v4, v8, x10
+vsetvli zero, zero, e8, m2, tu, mu
+vwmulsu.vv v4, v8, v12
+vsetvli zero, zero, e8, m4, tu, mu
+vwmulsu.vx v4, v8, x10
+vsetvli zero, zero, e8, m8, tu, mu
+vwmul.vv  v4, v8, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vwmul.vx  v4, v8, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vwmulu.vv v4, v8, v12
+vsetvli zero, zero, e16, m1, tu, mu
+vwmulu.vx v4, v8, x10
+vsetvli zero, zero, e16, m2, tu, mu
+vwmulsu.vv v4, v8, v12
+vsetvli zero, zero, e16, m4, tu, mu
+vwmulsu.vx v4, v8, x10
+vsetvli zero, zero, e16, m8, tu, mu
+vwmul.vv  v4, v8, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vwmul.vx  v4, v8, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vwmulu.vv v4, v8, v12
+vsetvli zero, zero, e32, m2, tu, mu
+vwmulu.vx v4, v8, x10
+vsetvli zero, zero, e32, m4, tu, mu
+vwmulsu.vv v4, v8, v12
+vsetvli zero, zero, e32, m8, tu, mu
+vwmulsu.vx v4, v8, x10
+
+# Vector Single-Width Integer Multiply-Add Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmacc.vv v4, v12, v8
+vsetvli zero, zero, e8, mf4, tu, mu
+vmacc.vx v4, x10, v8
+vsetvli zero, zero, e8, mf2, tu, mu
+vnmsac.vv v4, v12, v8
+vsetvli zero, zero, e8, m1, tu, mu
+vnmsac.vx v4, x10, v8
+vsetvli zero, zero, e8, m2, tu, mu
+vmadd.vv v4, v12, v8
+vsetvli zero, zero, e8, m4, tu, mu
+vmadd.vx v4, x10, v8
+vsetvli zero, zero, e8, m8, tu, mu
+vnmsub.vv v4, v12, v8
+vsetvli zero, zero, e16, mf4, tu, mu
+vnmsub.vx v4, x10, v8
+vsetvli zero, zero, e16, mf2, tu, mu
+vmacc.vv v4, v12, v8
+vsetvli zero, zero, e16, m1, tu, mu
+vmacc.vx v4, x10, v8
+vsetvli zero, zero, e16, m2, tu, mu
+vnmsac.vv v4, v12, v8
+vsetvli zero, zero, e16, m4, tu, mu
+vnmsac.vx v4, x10, v8
+vsetvli zero, zero, e16, m8, tu, mu
+vmadd.vv v4, v12, v8
+vsetvli zero, zero, e32, mf2, tu, mu
+vmadd.vx v4, x10, v8
+vsetvli zero, zero, e32, m1, tu, mu
+vnmsub.vv v4, v12, v8
+vsetvli zero, zero, e32, m2, tu, mu
+vnmsub.vx v4, x10, v8
+vsetvli zero, zero, e32, m4, tu, mu
+vmacc.vv v4, v12, v8
+vsetvli zero, zero, e32, m8, tu, mu
+vmacc.vx v4, x10, v8
+vsetvli zero, zero, e64, m1, tu, mu
+vnmsac.vv v4, v12, v8
+vsetvli zero, zero, e64, m2, tu, mu
+vnmsac.vx v4, x10, v8
+vsetvli zero, zero, e64, m4, tu, mu
+vmadd.vv v4, v12, v8
+vsetvli zero, zero, e64, m8, tu, mu
+vmadd.vx v4, x10, v8
+
+# Vector Widening Integer Multiply-Add Instructions
+# no e64
+vsetvli zero, zero, e8, mf8, tu, mu
+vwmaccu.vv v4, v12, v8
+vsetvli zero, zero, e8, mf4, tu, mu
+vwmaccu.vx v4, x10, v8
+vsetvli zero, zero, e8, mf2, tu, mu
+vwmacc.vv v4, v12, v8
+vsetvli zero, zero, e8, m1, tu, mu
+vwmacc.vx v4, x10, v8
+vsetvli zero, zero, e8, m2, tu, mu
+vwmaccsu.vv v4, v12, v8
+vsetvli zero, zero, e8, m4, tu, mu
+vwmaccsu.vx v4, x10, v8
+vsetvli zero, zero, e8, m8, tu, mu
+vwmaccus.vx v4, x10, v8
+vsetvli zero, zero, e16, mf4, tu, mu
+vwmaccu.vv v4, v12, v8
+vsetvli zero, zero, e16, mf2, tu, mu
+vwmaccu.vx v4, x10, v8
+vsetvli zero, zero, e16, m1, tu, mu
+vwmacc.vv v4, v12, v8
+vsetvli zero, zero, e16, m2, tu, mu
+vwmacc.vx v4, x10, v8
+vsetvli zero, zero, e16, m4, tu, mu
+vwmaccsu.vv v4, v12, v8
+vsetvli zero, zero, e16, m8, tu, mu
+vwmaccsu.vx v4, x10, v8
+vsetvli zero, zero, e32, mf2, tu, mu
+vwmaccus.vx v4, x10, v8
+vsetvli zero, zero, e32, m1, tu, mu
+vwmaccu.vv v4, v12, v8
+vsetvli zero, zero, e32, m2, tu, mu
+vwmaccu.vx v4, x10, v8
+vsetvli zero, zero, e32, m4, tu, mu
+vwmacc.vv v4, v12, v8
+vsetvli zero, zero, e32, m8, tu, mu
+vwmacc.vx v4, x10, v8
+
+# Vector Integer Merge Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, mf4, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, mf2, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m1, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e8, m2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e8, m4, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e8, m8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, mf4, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e16, mf2, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e16, m1, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e16, m2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e16, m4, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e16, m8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e32, mf2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, m1, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e32, m2, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e32, m4, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e32, m8, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m1, tu, mu
+vmerge.vvm v4, v8, v12, v0
+vsetvli zero, zero, e64, m2, tu, mu
+vmerge.vxm v4, v8, x10, v0
+vsetvli zero, zero, e64, m4, tu, mu
+vmerge.vim v4, v8, 0, v0
+vsetvli zero, zero, e64, m8, tu, mu
+vmerge.vvm v4, v8, v12, v0
+
+# Vector Integer Move Instructions
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e8, m1, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e8, m2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e8, m4, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e8, m8, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e16, m1, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e16, m2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e16, m4, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e16, m8, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e32, m1, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e32, m2, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e32, m4, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e32, m8, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e64, m1, tu, mu
+vmv.v.v v4, v12
+vsetvli zero, zero, e64, m2, tu, mu
+vmv.v.x v4, x10
+vsetvli zero, zero, e64, m4, tu, mu
+vmv.v.i v4, 0
+vsetvli zero, zero, e64, m8, tu, mu
+vmv.v.v v4, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VADD_VV       vadd.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VADD_VX       vadd.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VADD_VI       vadd.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSUB_VV       vsub.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSUB_VX       vsub.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VRSUB_VX      vrsub.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRSUB_VI     vrsub.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VADD_VV       vadd.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VADD_VX       vadd.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VADD_VI       vadd.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSUB_VV       vsub.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSUB_VX       vsub.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRSUB_VX     vrsub.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VRSUB_VI      vrsub.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VADD_VV       vadd.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VADD_VX       vadd.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VADD_VI       vadd.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSUB_VV      vsub.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSUB_VX       vsub.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VRSUB_VX      vrsub.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VRSUB_VI      vrsub.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VADD_VV      vadd.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWADDU_VV     vwaddu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWADDU_VX     vwaddu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWSUBU_VV     vwsubu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VWSUBU_VX     vwsubu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VWADD_VV      vwadd.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWADD_VX      vwadd.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWSUB_VV      vwsub.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWSUB_VX      vwsub.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWADDU_WV     vwaddu.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VWADDU_WX     vwaddu.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VWSUBU_WV     vwsubu.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWSUBU_WX     vwsubu.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWADD_WV      vwadd.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWADD_WX      vwadd.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VWSUB_WV      vwsub.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VWSUB_WX      vwsub.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWADDU_VV     vwaddu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWADDU_VX     vwaddu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VZEXT_VF4 vzext.vf4	v4, v8
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSEXT_VF4 vsext.vf4	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VZEXT_VF4 vzext.vf4	v4, v8
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSEXT_VF4 vsext.vf4	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VZEXT_VF4 vzext.vf4	v4, v8
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSEXT_VF4 vsext.vf4	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VZEXT_VF4 vzext.vf4	v4, v8
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSEXT_VF4 vsext.vf4	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VZEXT_VF4 vzext.vf4	v4, v8
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSEXT_VF4 vsext.vf4	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VZEXT_VF4 vzext.vf4	v4, v8
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSEXT_VF4 vsext.vf4	v4, v8
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VZEXT_VF8 vzext.vf8	v4, v8
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSEXT_VF8 vsext.vf8	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VZEXT_VF4 vzext.vf4	v4, v8
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSEXT_VF4 vsext.vf4	v4, v8
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VZEXT_VF8 vzext.vf8	v4, v8
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSEXT_VF8 vsext.vf8	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VZEXT_VF4 vzext.vf4	v4, v8
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSEXT_VF4 vsext.vf4	v4, v8
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VZEXT_VF8 vzext.vf8	v4, v8
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSEXT_VF8 vsext.vf8	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VZEXT_VF2 vzext.vf2	v4, v8
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSEXT_VF2 vsext.vf2	v4, v8
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VZEXT_VF4 vzext.vf4	v4, v8
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSEXT_VF4 vsext.vf4	v4, v8
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VZEXT_VF8 vzext.vf8	v4, v8
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSEXT_VF8 vsext.vf8	v4, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VADC_VVM vadc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VADC_VXM vadc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VADC_VIM vadc.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMADC_VVM vmadc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMADC_VXM vmadc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMADC_VIM vmadc.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMADC_VV vmadc.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMADC_VX vmadc.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMADC_VI vmadc.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSBC_VVM vsbc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSBC_VXM vsbc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMSBC_VVM vmsbc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMSBC_VXM vmsbc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSBC_VV vmsbc.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMSBC_VX vmsbc.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VADC_VVM vadc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VADC_VXM vadc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VADC_VIM vadc.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMADC_VVM vmadc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMADC_VXM vmadc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMADC_VIM vmadc.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMADC_VV vmadc.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VAND_VV       vand.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VAND_VX       vand.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VAND_VI       vand.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VOR_VV        vor.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VOR_VX        vor.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VOR_VI        vor.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VXOR_VV      vxor.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VXOR_VX       vxor.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VXOR_VI       vxor.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VAND_VV       vand.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VAND_VX       vand.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VAND_VI       vand.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VOR_VV       vor.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VOR_VX        vor.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VOR_VI        vor.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VXOR_VV       vxor.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VXOR_VX       vxor.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VXOR_VI      vxor.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VAND_VV       vand.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VAND_VX       vand.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VAND_VI       vand.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VOR_VV       vor.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSLL_VV       vsll.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSLL_VX       vsll.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSLL_VI       vsll.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSRL_VV       vsrl.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSRL_VX       vsrl.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSRL_VI       vsrl.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSRA_VV      vsra.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSRA_VX       vsra.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSRA_VI       vsra.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSLL_VV       vsll.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSLL_VX       vsll.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSLL_VI       vsll.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSRL_VV      vsrl.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VSRL_VX       vsrl.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSRL_VI       vsrl.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSRA_VV       vsra.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSRA_VX       vsra.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSRA_VI      vsra.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VSLL_VV       vsll.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VSLL_VX       vsll.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VSLL_VI       vsll.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VSRL_VV      vsrl.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VNSRL_WV      vnsrl.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VNSRL_WX      vnsrl.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VNSRL_WI      vnsrl.wi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VNSRA_WV      vnsra.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VNSRA_WX      vnsra.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VNSRA_WI     vnsra.wi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VNSRL_WV     vnsrl.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VNSRL_WX      vnsrl.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VNSRL_WI      vnsrl.wi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VNSRA_WV      vnsra.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VNSRA_WX      vnsra.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VNSRA_WI     vnsra.wi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VNSRL_WV     vnsrl.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VNSRL_WX      vnsrl.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VNSRL_WI      vnsrl.wi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VNSRA_WV      vnsra.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VNSRA_WX     vnsra.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VNSRA_WI     vnsra.wi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VNSRL_WV      vnsrl.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VNSRL_WX      vnsrl.wx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VNSRL_WI     vnsrl.wi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VNSRA_WV     vnsra.wv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSEQ_VV vmseq.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSEQ_VX vmseq.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSEQ_VI vmseq.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      5     2.00                         5     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMSNE_VV vmsne.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      7     4.00                         7     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMSNE_VX vmsne.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      11    8.00                         11    VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMSNE_VI vmsne.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMSLTU_VV vmsltu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSLTU_VX vmsltu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSLT_VV vmslt.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      5     2.00                         5     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMSLT_VX vmslt.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      7     4.00                         7     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMSLEU_VV vmsleu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      11    8.00                         11    VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMSLEU_VX vmsleu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMSLEU_VI vmsleu.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSLE_VV vmsle.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      5     2.00                         5     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMSLE_VX vmsle.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      7     4.00                         7     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMSLE_VI vmsle.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      11    8.00                         11    VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMSGTU_VX vmsgtu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMSGTU_VI vmsgtu.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      5     2.00                         5     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMSGT_VX vmsgt.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      7     4.00                         7     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMSGT_VI vmsgt.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      11    8.00                         11    VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMSEQ_VV vmseq.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMSEQ_VX vmseq.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSLE_VI vmsle.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSLEU_VI vmsleu.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSNE_VV vmsne.vv	v4, v8, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      5     2.00                         5     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMSGTU_VI vmsgtu.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      7     4.00                         7     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMSGT_VI vmsgt.vi	v4, v8, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      11    8.00                         11    VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMSEQ_VV vmseq.vv	v4, v8, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSGT_VI vmsgt.vi	v4, v8, -1
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMSLT_VX vmslt.vx	v4, v8, a0
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMNAND_MM vmnot.m	v4, v4
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      5     2.00                         5     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMSLTU_VX vmsltu.vx	v4, v8, a1
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMNAND_MM vmnot.m	v4, v4
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMINU_VV vminu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMINU_VX vminu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMIN_VV vmin.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMIN_VX vmin.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMAXU_VV vmaxu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMAXU_VX vmaxu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMAX_VV vmax.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMAX_VX vmax.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMINU_VV vminu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMINU_VX vminu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMIN_VV vmin.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMIN_VX vmin.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMAXU_VV vmaxu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMAXU_VX vmaxu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMAX_VV vmax.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMAX_VX vmax.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMINU_VV vminu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMINU_VX vminu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMIN_VV vmin.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMIN_VX vmin.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMAXU_VV vmaxu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMAXU_VX vmaxu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMUL_VV       vmul.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMUL_VX       vmul.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMULH_VV      vmulh.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMULH_VX      vmulh.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMULHU_VV     vmulhu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMULHU_VX     vmulhu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMULHSU_VV   vmulhsu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMULHSU_VX    vmulhsu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMUL_VV       vmul.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMUL_VX       vmul.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMULH_VV      vmulh.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMULH_VX      vmulh.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMULHU_VV    vmulhu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMULHU_VX     vmulhu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMULHSU_VV    vmulhsu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMULHSU_VX    vmulhsu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMUL_VV       vmul.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMUL_VX      vmul.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMULH_VV      vmulh.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMULH_VX      vmulh.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMULHU_VV     vmulhu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMULHU_VX    vmulhu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      60    60.00                        60    VLEN1024X300SiFive7VA1[1,61],VLEN1024X300SiFive7VA1OrVA2[1,61],VLEN1024X300SiFive7VCQ VDIVU_VV vdivu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      120   120.00                       120   VLEN1024X300SiFive7VA1[1,121],VLEN1024X300SiFive7VA1OrVA2[1,121],VLEN1024X300SiFive7VCQ VDIVU_VX vdivu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      240   240.00                       240   VLEN1024X300SiFive7VA1[1,241],VLEN1024X300SiFive7VA1OrVA2[1,241],VLEN1024X300SiFive7VCQ VDIV_VV vdiv.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      480   480.00                       480   VLEN1024X300SiFive7VA1[1,481],VLEN1024X300SiFive7VA1OrVA2[1,481],VLEN1024X300SiFive7VCQ VDIV_VX vdiv.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      960   960.00                       960   VLEN1024X300SiFive7VA1[1,961],VLEN1024X300SiFive7VA1OrVA2[1,961],VLEN1024X300SiFive7VCQ VREMU_VV vremu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      1920  1920.00                      1920  VLEN1024X300SiFive7VA1[1,1921],VLEN1024X300SiFive7VA1OrVA2[1,1921],VLEN1024X300SiFive7VCQ VREMU_VX vremu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      3840  3840.00                      3840  VLEN1024X300SiFive7VA1[1,3841],VLEN1024X300SiFive7VA1OrVA2[1,3841],VLEN1024X300SiFive7VCQ VREM_VV vrem.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      60    60.00                        60    VLEN1024X300SiFive7VA1[1,61],VLEN1024X300SiFive7VA1OrVA2[1,61],VLEN1024X300SiFive7VCQ VREM_VX vrem.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      120   120.00                       120   VLEN1024X300SiFive7VA1[1,121],VLEN1024X300SiFive7VA1OrVA2[1,121],VLEN1024X300SiFive7VCQ VDIVU_VV vdivu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      240   240.00                       240   VLEN1024X300SiFive7VA1[1,241],VLEN1024X300SiFive7VA1OrVA2[1,241],VLEN1024X300SiFive7VCQ VDIVU_VX vdivu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      480   480.00                       480   VLEN1024X300SiFive7VA1[1,481],VLEN1024X300SiFive7VA1OrVA2[1,481],VLEN1024X300SiFive7VCQ VDIV_VV vdiv.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      960   960.00                       960   VLEN1024X300SiFive7VA1[1,961],VLEN1024X300SiFive7VA1OrVA2[1,961],VLEN1024X300SiFive7VCQ VDIV_VX vdiv.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      1920  1920.00                      1920  VLEN1024X300SiFive7VA1[1,1921],VLEN1024X300SiFive7VA1OrVA2[1,1921],VLEN1024X300SiFive7VCQ VREMU_VV vremu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      112   112.00                       112   VLEN1024X300SiFive7VA1[1,113],VLEN1024X300SiFive7VA1OrVA2[1,113],VLEN1024X300SiFive7VCQ VREMU_VX vremu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      224   224.00                       224   VLEN1024X300SiFive7VA1[1,225],VLEN1024X300SiFive7VA1OrVA2[1,225],VLEN1024X300SiFive7VCQ VREM_VV vrem.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      448   448.00                       448   VLEN1024X300SiFive7VA1[1,449],VLEN1024X300SiFive7VA1OrVA2[1,449],VLEN1024X300SiFive7VCQ VREM_VX vrem.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      896   896.00                       896   VLEN1024X300SiFive7VA1[1,897],VLEN1024X300SiFive7VA1OrVA2[1,897],VLEN1024X300SiFive7VCQ VDIVU_VV vdivu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      1792  1792.00                      1792  VLEN1024X300SiFive7VA1[1,1793],VLEN1024X300SiFive7VA1OrVA2[1,1793],VLEN1024X300SiFive7VCQ VDIVU_VX vdivu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      228   228.00                       228   VLEN1024X300SiFive7VA1[1,229],VLEN1024X300SiFive7VA1OrVA2[1,229],VLEN1024X300SiFive7VCQ VDIV_VV vdiv.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      456   456.00                       456   VLEN1024X300SiFive7VA1[1,457],VLEN1024X300SiFive7VA1OrVA2[1,457],VLEN1024X300SiFive7VCQ VDIV_VX vdiv.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      912   912.00                       912   VLEN1024X300SiFive7VA1[1,913],VLEN1024X300SiFive7VA1OrVA2[1,913],VLEN1024X300SiFive7VCQ VREMU_VV vremu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      1824  1824.00                      1824  VLEN1024X300SiFive7VA1[1,1825],VLEN1024X300SiFive7VA1OrVA2[1,1825],VLEN1024X300SiFive7VCQ VREMU_VX vremu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMUL_VV      vwmul.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMUL_VX      vwmul.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMULU_VV     vwmulu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VWMULU_VX     vwmulu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VWMULSU_VV    vwmulsu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMULSU_VX    vwmulsu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMUL_VV      vwmul.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMUL_VX      vwmul.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMULU_VV     vwmulu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VWMULU_VX     vwmulu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VWMULSU_VV    vwmulsu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMULSU_VX    vwmulsu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMUL_VV      vwmul.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMUL_VX      vwmul.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VWMULU_VV     vwmulu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VWMULU_VX     vwmulu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMULSU_VV    vwmulsu.vv	v4, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMULSU_VX    vwmulsu.vx	v4, v8, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMACC_VV      vmacc.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMACC_VX      vmacc.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VNMSAC_VV     vnmsac.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VNMSAC_VX     vnmsac.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMADD_VV      vmadd.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMADD_VX      vmadd.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VNMSUB_VV    vnmsub.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VNMSUB_VX     vnmsub.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMACC_VV      vmacc.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMACC_VX      vmacc.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VNMSAC_VV     vnmsac.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VNMSAC_VX     vnmsac.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMADD_VV     vmadd.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMADD_VX      vmadd.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VNMSUB_VV     vnmsub.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VNMSUB_VX     vnmsub.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMACC_VV      vmacc.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMACC_VX     vmacc.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VNMSAC_VV     vnmsac.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VNMSAC_VX     vnmsac.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMADD_VV      vmadd.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      8     8.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMADD_VX     vmadd.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMACCU_VV    vwmaccu.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMACCU_VX    vwmaccu.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMACC_VV     vwmacc.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VWMACC_VX     vwmacc.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VWMACCSU_VV   vwmaccsu.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMACCSU_VX   vwmaccsu.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMACCUS_VX   vwmaccus.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMACCU_VV    vwmaccu.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMACCU_VX    vwmaccu.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VWMACC_VV     vwmacc.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VWMACC_VX     vwmacc.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMACCSU_VV   vwmaccsu.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMACCSU_VX   vwmaccsu.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VWMACCUS_VX   vwmaccus.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      8     1.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VWMACCU_VV    vwmaccu.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      8     2.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VWMACCU_VX    vwmaccu.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMACC_VV     vwmacc.vv	v4, v12, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      8     4.00                         8     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VWMACC_VX     vwmacc.vx	v4, a0, v8
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMERGE_VVM vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMERGE_VXM vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMERGE_VIM vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMERGE_VVM vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMERGE_VXM vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMERGE_VIM vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMERGE_VVM vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMERGE_VXM vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMERGE_VIM vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMERGE_VVM vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMERGE_VXM vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMERGE_VIM vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMERGE_VVM vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1[1,2],VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMERGE_VXM vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMERGE_VIM vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMERGE_VVM vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMERGE_VXM vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMERGE_VIM vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1[1,3],VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMERGE_VVM vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1[1,5],VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMERGE_VXM vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1[1,9],VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMERGE_VIM vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                        4     VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMERGE_VVM vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMV_V_V       vmv.v.v	v4, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMV_V_X       vmv.v.x	v4, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMV_V_I       vmv.v.i	v4, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMV_V_V       vmv.v.v	v4, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMV_V_X       vmv.v.x	v4, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMV_V_I       vmv.v.i	v4, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMV_V_V      vmv.v.v	v4, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMV_V_X       vmv.v.x	v4, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMV_V_I       vmv.v.i	v4, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMV_V_V       vmv.v.v	v4, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMV_V_X       vmv.v.x	v4, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMV_V_I       vmv.v.i	v4, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMV_V_V      vmv.v.v	v4, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,2],VLEN1024X300SiFive7VCQ VMV_V_X       vmv.v.x	v4, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMV_V_I       vmv.v.i	v4, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMV_V_V       vmv.v.v	v4, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMV_V_X       vmv.v.x	v4, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMV_V_I      vmv.v.i	v4, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,3],VLEN1024X300SiFive7VCQ VMV_V_V       vmv.v.v	v4, v12
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,5],VLEN1024X300SiFive7VCQ VMV_V_X       vmv.v.x	v4, a0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,9],VLEN1024X300SiFive7VCQ VMV_V_I       vmv.v.i	v4, 0
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00                         4     VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VMV_V_V      vmv.v.v	v4, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     342.00  -     20046.50 682.50 385.00  -    -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vadd.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vadd.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vadd.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vsub.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vsub.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vrsub.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vrsub.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vadd.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vadd.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vadd.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vsub.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vsub.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vrsub.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vrsub.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vadd.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vadd.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vadd.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vsub.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vsub.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vrsub.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vrsub.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vadd.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwaddu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwaddu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwsubu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vwsubu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vwadd.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwadd.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwsub.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwsub.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwaddu.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vwaddu.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vwsubu.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwsubu.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwadd.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwadd.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vwsub.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vwsub.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwaddu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwaddu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vzext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vsext.vf4	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vzext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vsext.vf4	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vzext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vsext.vf4	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vzext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vsext.vf4	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vzext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vsext.vf4	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vzext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vsext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vzext.vf8	v4, v8
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vsext.vf8	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vzext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vsext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vzext.vf8	v4, v8
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vsext.vf8	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vzext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vsext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vzext.vf8	v4, v8
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vsext.vf8	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vzext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vsext.vf2	v4, v8
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vzext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vsext.vf4	v4, v8
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vzext.vf8	v4, v8
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vsext.vf8	v4, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vadc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vadc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vadc.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmadc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmadc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmadc.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmadc.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmadc.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmadc.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vsbc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vsbc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmsbc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmsbc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmsbc.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmsbc.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vadc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vadc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vadc.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmadc.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmadc.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmadc.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmadc.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vand.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vand.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vand.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vor.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vor.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vor.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vxor.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vxor.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vxor.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vand.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vand.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vand.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vor.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vor.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vor.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vxor.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vxor.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vxor.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vand.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vand.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vand.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vor.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vsll.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vsll.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vsll.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vsrl.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vsrl.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vsrl.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vsra.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vsra.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vsra.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vsll.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vsll.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vsll.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vsrl.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vsrl.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vsrl.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vsra.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vsra.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vsra.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vsll.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vsll.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vsll.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vsrl.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vnsrl.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vnsrl.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vnsrl.wi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vnsra.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vnsra.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vnsra.wi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vnsrl.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vnsrl.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vnsrl.wi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vnsra.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vnsra.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vnsra.wi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vnsrl.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vnsrl.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vnsrl.wi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vnsra.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vnsra.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vnsra.wi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vnsrl.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vnsrl.wx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vnsrl.wi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vnsra.wv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmseq.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmseq.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmseq.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmsne.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmsne.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmsne.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmsltu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmsltu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmslt.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmslt.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmsleu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmsleu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmsleu.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmsle.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmsle.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmsle.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmsgtu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmsgtu.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmsgt.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmsgt.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmseq.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmseq.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmsle.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmsleu.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmsne.vv	v4, v8, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmsgtu.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmsgt.vi	v4, v8, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmseq.vv	v4, v8, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmsgt.vi	v4, v8, -1
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmslt.vx	v4, v8, a0
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmnot.m	v4, v4
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmsltu.vx	v4, v8, a1
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmnot.m	v4, v4
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vminu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vminu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmin.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmin.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmaxu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmaxu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmax.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmax.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vminu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vminu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmin.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmin.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmaxu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmaxu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmax.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmax.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vminu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vminu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmin.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmin.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmaxu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmaxu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmul.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmul.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmulh.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vmulh.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vmulhu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmulhu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmulhsu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmulhsu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmul.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vmul.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vmulh.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmulh.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmulhu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmulhu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vmulhsu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vmulhsu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmul.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmul.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vmulh.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vmulh.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmulhu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmulhu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     61.00   -     1.00    -      -     vdivu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     121.00  -     1.00    -      -     vdivu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     241.00  -     1.00    -      -     vdiv.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     481.00  -     1.00    -      -     vdiv.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     961.00  -     1.00    -      -     vremu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1921.00  -    1.00    -      -     vremu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     3841.00  -    1.00    -      -     vrem.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     61.00   -     1.00    -      -     vrem.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     121.00  -     1.00    -      -     vdivu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     241.00  -     1.00    -      -     vdivu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     481.00  -     1.00    -      -     vdiv.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     961.00  -     1.00    -      -     vdiv.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1921.00  -    1.00    -      -     vremu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     113.00  -     1.00    -      -     vremu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     225.00  -     1.00    -      -     vrem.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     449.00  -     1.00    -      -     vrem.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     897.00  -     1.00    -      -     vdivu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1793.00  -    1.00    -      -     vdivu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     229.00  -     1.00    -      -     vdiv.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     457.00  -     1.00    -      -     vdiv.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     913.00  -     1.00    -      -     vremu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1825.00  -    1.00    -      -     vremu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmul.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmul.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmulu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vwmulu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vwmulsu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmulsu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmul.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmul.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmulu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vwmulu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vwmulsu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmulsu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmul.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmul.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vwmulu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vwmulu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmulsu.vv	v4, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmulsu.vx	v4, v8, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmacc.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmacc.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vnmsac.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vnmsac.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vmadd.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmadd.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vnmsub.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vnmsub.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmacc.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vmacc.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vnmsac.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vnmsac.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmadd.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmadd.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vnmsub.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vnmsub.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmacc.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmacc.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vnmsac.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vnmsac.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmadd.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmadd.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmaccu.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmaccu.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmacc.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vwmacc.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vwmaccsu.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmaccsu.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmaccus.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmaccu.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmaccu.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vwmacc.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vwmacc.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmaccsu.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmaccsu.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vwmaccus.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vwmaccu.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vwmaccu.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmacc.vv	v4, v12, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vwmacc.vx	v4, a0, v8
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00    -     1.00    -      -     vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     3.00    -     1.00    -      -     vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     5.00    -     1.00    -      -     vmerge.vxm	v4, v8, a0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     9.00    -     1.00    -      -     vmerge.vim	v4, v8, 0, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vmerge.vvm	v4, v8, v12, v0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmv.v.v	v4, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmv.v.x	v4, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmv.v.i	v4, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vmv.v.v	v4, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vmv.v.x	v4, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmv.v.i	v4, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmv.v.v	v4, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmv.v.x	v4, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmv.v.i	v4, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vmv.v.v	v4, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vmv.v.x	v4, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmv.v.i	v4, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmv.v.v	v4, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00   1.00    -      -     vmv.v.x	v4, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vmv.v.i	v4, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vmv.v.v	v4, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmv.v.x	v4, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmv.v.i	v4, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.50   1.50   1.00    -      -     vmv.v.v	v4, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.50   2.50   1.00    -      -     vmv.v.x	v4, a0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     4.50   4.50   1.00    -      -     vmv.v.i	v4, 0
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.50   8.50   1.00    -      -     vmv.v.v	v4, v12
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vgather-vcompress.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vgather-vcompress.s
new file mode 100644
index 0000000000000..d3f129a19b01e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vgather-vcompress.s
@@ -0,0 +1,317 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s
+
+# The legal (SEW, LMUL) pairs on sifive-x280 are:
+# (e8, mf8) (e8, mf4) (e8, mf2) (e8, m1) (e8, m2) (e8, m4) (e8, m8)
+# (e16, mf4) (e16, mf2) (e16, m1) (e16, m2) (e16, m4) (e16, m8)
+# (e32, mf2) (e32, m1) (e32, m2) (e32, m4) (e32, m8)
+# (e64, m1) (e64, m2) (e64, m4) (e64, m8)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e8, mf4, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e8, mf2, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e8, m1, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e8, m2, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e8, m4, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e8, m8, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e16, mf4, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e16, mf2, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e16, m1, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e16, m2, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e16, m4, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e16, m8, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e32, mf2, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e32, m2, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e32, m4, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e32, m8, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e64, m1, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e64, m2, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e64, m4, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+vsetvli zero, zero, e64, m8, tu, mu
+vrgather.vv v8, v16, v24
+vrgatherei16.vv v8, v16, v24
+vcompress.vm v8, v16, v24
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      259   256.00                       259   VLEN1024X300SiFive7VA1[1,257],VLEN1024X300SiFive7VA1OrVA2[1,257],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      259   256.00                       259   VLEN1024X300SiFive7VA1[1,257],VLEN1024X300SiFive7VA1OrVA2[1,257],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      259   256.00                       259   VLEN1024X300SiFive7VA1[1,257],VLEN1024X300SiFive7VA1OrVA2[1,257],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      515   512.00                       515   VLEN1024X300SiFive7VA1[1,513],VLEN1024X300SiFive7VA1OrVA2[1,513],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      515   512.00                       515   VLEN1024X300SiFive7VA1[1,513],VLEN1024X300SiFive7VA1OrVA2[1,513],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      515   512.00                       515   VLEN1024X300SiFive7VA1[1,513],VLEN1024X300SiFive7VA1OrVA2[1,513],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      1027  1024.00                      1027  VLEN1024X300SiFive7VA1[1,1025],VLEN1024X300SiFive7VA1OrVA2[1,1025],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      1027  1024.00                      1027  VLEN1024X300SiFive7VA1[1,1025],VLEN1024X300SiFive7VA1OrVA2[1,1025],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      1027  1024.00                      1027  VLEN1024X300SiFive7VA1[1,1025],VLEN1024X300SiFive7VA1OrVA2[1,1025],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      259   256.00                       259   VLEN1024X300SiFive7VA1[1,257],VLEN1024X300SiFive7VA1OrVA2[1,257],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      259   256.00                       259   VLEN1024X300SiFive7VA1[1,257],VLEN1024X300SiFive7VA1OrVA2[1,257],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      259   256.00                       259   VLEN1024X300SiFive7VA1[1,257],VLEN1024X300SiFive7VA1OrVA2[1,257],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      515   512.00                       515   VLEN1024X300SiFive7VA1[1,513],VLEN1024X300SiFive7VA1OrVA2[1,513],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      515   512.00                       515   VLEN1024X300SiFive7VA1[1,513],VLEN1024X300SiFive7VA1OrVA2[1,513],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      515   512.00                       515   VLEN1024X300SiFive7VA1[1,513],VLEN1024X300SiFive7VA1OrVA2[1,513],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      259   256.00                       259   VLEN1024X300SiFive7VA1[1,257],VLEN1024X300SiFive7VA1OrVA2[1,257],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      259   256.00                       259   VLEN1024X300SiFive7VA1[1,257],VLEN1024X300SiFive7VA1OrVA2[1,257],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      259   256.00                       259   VLEN1024X300SiFive7VA1[1,257],VLEN1024X300SiFive7VA1OrVA2[1,257],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      19    16.00                        19    VLEN1024X300SiFive7VA1[1,17],VLEN1024X300SiFive7VA1OrVA2[1,17],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      35    32.00                        35    VLEN1024X300SiFive7VA1[1,33],VLEN1024X300SiFive7VA1OrVA2[1,33],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      67    64.00                        67    VLEN1024X300SiFive7VA1[1,65],VLEN1024X300SiFive7VA1OrVA2[1,65],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VRGATHER_VV vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VRGATHEREI16_VV vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  1      131   128.00                       131   VLEN1024X300SiFive7VA1[1,129],VLEN1024X300SiFive7VA1OrVA2[1,129],VLEN1024X300SiFive7VCQ VCOMPRESS_VM vcompress.vm	v8, v16, v24
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     22.00   -     11394.00  -   66.00   -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     257.00  -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     257.00  -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     257.00  -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     513.00  -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     513.00  -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     513.00  -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1025.00  -    1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1025.00  -    1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     1025.00  -    1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     257.00  -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     257.00  -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     257.00  -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     513.00  -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     513.00  -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     513.00  -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     257.00  -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     257.00  -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     257.00  -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     17.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     33.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     65.00   -     1.00    -      -     vcompress.vm	v8, v16, v24
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vrgather.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vrgatherei16.vv	v8, v16, v24
+# CHECK-NEXT:  -      -      -      -     129.00  -     1.00    -      -     vcompress.vm	v8, v16, v24
diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vle-vse.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vle-vse.s
new file mode 100644
index 0000000000000..f6114225f33ba
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX390/vle-vse.s
@@ -0,0 +1,1256 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x390 -instruction-tables=full -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vle8.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vle8.v    v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vle16.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vle16.v    v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vle32.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vle32.v    v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vle64.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vle64.v    v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vse8.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vse8.v    v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vse16.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vse16.v    v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vse32.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vse32.v    v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vse64.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vse64.v    v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlm.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vlm.v    v1, (a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e8, m8, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e16, m8, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e32, m8, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vsm.v    v1, (a0)
+vsetvli zero, zero, e64, m8, tu, mu
+vsm.v    v1, (a0)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv:1
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv:1
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA:1
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeAB:2 VLEN1024X300SiFive7PipeA, VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7PipeB:1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA1:1
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VA1OrVA2:2 VLEN1024X300SiFive7VA1, VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VA2:1
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VCQ:1
+# CHECK-NEXT: [9]   - VLEN1024X300SiFive7VL:1
+# CHECK-NEXT: [10]  - VLEN1024X300SiFive7VS:1
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE8_V             vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE8_V              vle8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE16_V            vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE16_V            vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE16_V             vle16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE32_V            vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE32_V            vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE32_V            vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     1.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,2] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE32_V             vle32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE64_V            vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE64_V            vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE64_V            vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     4.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,5] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     8.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,9] VLE64_V             vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00   *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,17] VLE64_V            vle64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE8_V             vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE8_V              vse8.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE16_V            vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE16_V            vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE16_V             vse16.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE32_V            vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE32_V            vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE32_V            vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      1     1.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,2] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE32_V             vse32.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE64_V            vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE64_V            vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE64_V            vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      1     4.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,5] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      1     8.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,9] VSE64_V             vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      1     16.00          *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,17] VSE64_V            vse64.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      4     2.00    *                    4     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VL[1,3] VLM_V               vlm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+# CHECK-NEXT:  1      3     1.00                  U      1     VLEN1024X300SiFive7PipeA,VLEN1024X300SiFive7PipeAB VSETVLI            vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  1      1     2.00           *             1     VLEN1024X300SiFive7VCQ,VLEN1024X300SiFive7VS[1,3] VSM_V               vsm.v	v1, (a0)
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - VLEN1024X300SiFive7FDiv
+# CHECK-NEXT: [1]   - VLEN1024X300SiFive7IDiv
+# CHECK-NEXT: [2]   - VLEN1024X300SiFive7PipeA
+# CHECK-NEXT: [3]   - VLEN1024X300SiFive7PipeB
+# CHECK-NEXT: [4]   - VLEN1024X300SiFive7VA1
+# CHECK-NEXT: [5]   - VLEN1024X300SiFive7VA2
+# CHECK-NEXT: [6]   - VLEN1024X300SiFive7VCQ
+# CHECK-NEXT: [7]   - VLEN1024X300SiFive7VL
+# CHECK-NEXT: [8]   - VLEN1024X300SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
+# CHECK-NEXT:  -      -     200.00  -      -      -     200.00 524.00 524.00
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   2.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   5.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   9.00    -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   17.00   -     vle64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse8.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse16.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     2.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse32.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     5.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     9.00   vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     17.00  vse64.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00   3.00    -     vlm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e16, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m4, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -      -     vsetvli	zero, zero, e64, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -      -      -     1.00    -     3.00   vsm.v	v1, (a0)