From 9d7007d336304d761952e2971fdf3507de9468ba Mon Sep 17 00:00:00 2001 From: guochen2 Date: Fri, 13 Jun 2025 02:08:01 -0400 Subject: [PATCH 1/2] fix bfe for true16 mode --- llvm/lib/Target/AMDGPU/SIInstructions.td | 19 +++++++++++++++++ llvm/lib/Target/AMDGPU/VOP3Instructions.td | 24 ++++++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 897c30948cf06..56b15c11a6694 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -2623,6 +2623,8 @@ def : GCNPat< (i32 (DivergentSextInreg i32:$src)), (V_BFE_I32_e64 i32:$src, (i32 0), (i32 1))>; +foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in +let True16Predicate = p in { def : GCNPat < (i16 (DivergentSextInreg i16:$src)), (V_BFE_I32_e64 $src, (i32 0), (i32 1)) @@ -2632,6 +2634,23 @@ def : GCNPat < (i16 (DivergentSextInreg i16:$src)), (V_BFE_I32_e64 $src, (i32 0), (i32 8)) >; +} + +let True16Predicate = UseRealTrue16Insts in { +def : GCNPat < + (i16 (DivergentSextInreg i16:$src)), + (V_BFE_I32_e64 + (REG_SEQUENCE VGPR_32, VGPR_16:$src, lo16, (i16 (IMPLICIT_DEF)), hi16), + (i32 0), (i32 1)) +>; + +def : GCNPat < + (i16 (DivergentSextInreg i16:$src)), + (V_BFE_I32_e64 + (REG_SEQUENCE VGPR_32, VGPR_16:$src, lo16, (i16 (IMPLICIT_DEF)), hi16), + (i32 0), (i32 8)) +>; +} def : GCNPat< (i32 (DivergentSextInreg i32:$src)), diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td index 2dbc119f65cda..89a9ecc27c6ed 100644 --- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td +++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td @@ -319,11 +319,21 @@ let SchedRW = [Write64Bit] in { } // End SchedRW = [Write64Bit] } // End isReMaterializable = 1 +foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in +let True16Predicate = p in def : GCNPat< (i32 (DivergentUnaryFrag i16:$src)), (i32 (V_BFE_I32_e64 i16:$src, (i32 0), (i32 0x10))) >; +let True16Predicate = UseRealTrue16Insts in +def : GCNPat< + (i32 (DivergentUnaryFrag i16:$src)), + (i32 (V_BFE_I32_e64 + (REG_SEQUENCE VGPR_32, VGPR_16:$src, lo16, (i16 (IMPLICIT_DEF)), hi16), + (i32 0), (i32 0x10))) +>; + let isReMaterializable = 1 in { let SubtargetPredicate = isGFX6GFX7GFX10Plus in { defm V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile>; @@ -423,6 +433,8 @@ def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32 } // End SubtargetPredicate = Has16BitInsts, isCommutable = 1 +foreach p = [NotHasTrue16BitInsts, UseFakeTrue16Insts] in +let True16Predicate = p in def : GCNPat< (i64 (DivergentUnaryFrag i16:$src)), (REG_SEQUENCE VReg_64, @@ -432,6 +444,18 @@ def : GCNPat< ), VGPR_32)), sub1) >; +let True16Predicate = UseRealTrue16Insts in +def : GCNPat< + (i64 (DivergentUnaryFrag i16:$src)), + (REG_SEQUENCE VReg_64, + (i32 (V_BFE_I32_e64 + (REG_SEQUENCE VGPR_32, VGPR_16:$src, lo16, (i16 (IMPLICIT_DEF)), hi16), + (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0, + (i32 (COPY_TO_REGCLASS + (V_ASHRREV_I32_e32 (S_MOV_B32 (i32 0x1f)), (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))) + ), VGPR_32)), sub1) +>; + let SubtargetPredicate = isGFX8Plus, Uses = [MODE, M0, EXEC], OtherPredicates = [isNotGFX90APlus] in { def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>; def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>; From ccb669a2fe9b9ee71ec331656854f39192e8e393 Mon Sep 17 00:00:00 2001 From: guochen2 Date: Fri, 13 Jun 2025 02:43:15 -0400 Subject: [PATCH 2/2] update test --- llvm/test/CodeGen/AMDGPU/idot4s.ll | 69 +++-- llvm/test/CodeGen/AMDGPU/idot4u.ll | 79 +++--- llvm/test/CodeGen/AMDGPU/llvm.frexp.ll | 64 ++--- .../AMDGPU/sext-in-reg-vector-shuffle.ll | 86 ++++++ .../test/CodeGen/AMDGPU/vector-reduce-smax.ll | 260 ++++++++++-------- .../test/CodeGen/AMDGPU/vector-reduce-smin.ll | 260 ++++++++++-------- 6 files changed, 478 insertions(+), 340 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll diff --git a/llvm/test/CodeGen/AMDGPU/idot4s.ll b/llvm/test/CodeGen/AMDGPU/idot4s.ll index 9e7968f1acb84..ab38bd21994ec 100644 --- a/llvm/test/CodeGen/AMDGPU/idot4s.ll +++ b/llvm/test/CodeGen/AMDGPU/idot4s.ll @@ -1165,35 +1165,32 @@ define amdgpu_kernel void @idot4_acc16_vecMul(ptr addrspace(1) %src1, ; GFX11-DL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX11-DL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-DL-TRUE16-NEXT: s_clause 0x1 -; GFX11-DL-TRUE16-NEXT: global_load_b32 v1, v0, s[2:3] -; GFX11-DL-TRUE16-NEXT: global_load_b32 v2, v0, s[0:1] +; GFX11-DL-TRUE16-NEXT: global_load_b32 v1, v0, s[0:1] +; GFX11-DL-TRUE16-NEXT: global_load_b32 v2, v0, s[2:3] ; GFX11-DL-TRUE16-NEXT: global_load_d16_b16 v0, v3, s[4:5] ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(2) -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v1, 0, 8 ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l -; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v6.h, 8, v2.l -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.h -; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v8.h, 8, v1.l -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8 -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.h -; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v2.h, 8, v2.h +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 8 +; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v4.h, 8, v1.l +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v1.h +; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v7.h, 8, v2.l +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v1, 0, 8 ; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v1.h, 8, v1.h -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v4, v9, 0, 8 -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v7, 0, 8 -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v6, v6, v8 -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3) +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 8 +; GFX11-DL-TRUE16-NEXT: v_ashrrev_i16 v2.h, 8, v2.h +; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v4, v4, v7 +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v6.l +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) ; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v6.l, v0.l +; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v4.l, v0.l ; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v2, v1 -; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v6.h +; GFX11-DL-TRUE16-NEXT: v_pk_mul_lo_u16 v1, v1, v2 +; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v4.h ; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.l ; GFX11-DL-TRUE16-NEXT: v_add_nc_u16 v0.l, v0.l, v1.h @@ -3435,35 +3432,31 @@ define amdgpu_kernel void @idot4_nonstandard_signed(ptr addrspace(1) %src1, ; GFX11-DL-TRUE16-NEXT: global_load_b32 v2, v0, s[0:1] ; GFX11-DL-TRUE16-NEXT: global_load_b32 v3, v0, s[2:3] ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l -; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 +; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v2 +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v1, v2, 0, 8 ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v3 -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.h -; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 24, v2 -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v4, v0, 0, 8 -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l ; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l -; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v6.l +; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v3 +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.h +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 ; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.h +; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.l +; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v5.l +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v6, 0, 8 ; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v4, v5, 0, 8 -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v7, 0, 8 +; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 24, v2 ; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3 ; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-DL-TRUE16-NEXT: v_mul_lo_u16 v0.l, v1.l, v0.l -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l ; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v1.l, v0.l +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.h, v2.l, v0.l +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.l -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v3.l, v0.l ; GFX11-DL-TRUE16-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16 ; GFX11-DL-TRUE16-NEXT: global_store_b32 v1, v0, s[4:5] ; GFX11-DL-TRUE16-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll index f995f426c6372..5e502882a2645 100644 --- a/llvm/test/CodeGen/AMDGPU/idot4u.ll +++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll @@ -1669,40 +1669,38 @@ define amdgpu_kernel void @notdot4_mixedtypes(ptr addrspace(1) %src1, ; GFX11-DL-TRUE16-LABEL: notdot4_mixedtypes: ; GFX11-DL-TRUE16: ; %bb.0: ; %entry ; GFX11-DL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-DL-TRUE16-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0x3ff, v0 +; GFX11-DL-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0 ; GFX11-DL-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-DL-TRUE16-NEXT: v_mov_b32_e32 v6, 0 +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-DL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX11-DL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-DL-TRUE16-NEXT: s_clause 0x1 -; GFX11-DL-TRUE16-NEXT: global_load_b32 v3, v0, s[0:1] -; GFX11-DL-TRUE16-NEXT: global_load_b32 v4, v0, s[2:3] -; GFX11-DL-TRUE16-NEXT: global_load_d16_b16 v0, v5, s[4:5] +; GFX11-DL-TRUE16-NEXT: global_load_b32 v4, v0, s[0:1] +; GFX11-DL-TRUE16-NEXT: global_load_b32 v5, v0, s[2:3] +; GFX11-DL-TRUE16-NEXT: global_load_d16_b16 v0, v6, s[4:5] ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(2) -; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3 +; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v4 ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v4 -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l +; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v5 +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v7, v5, 0, 8 ; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l ; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v2.l -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8 +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l ; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3) -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v7, 0, 8 +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v1.l, v0.l -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.l -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v2.l, v0.l -; GFX11-DL-TRUE16-NEXT: v_perm_b32 v1, v4, v4, 0xc0c0302 -; GFX11-DL-TRUE16-NEXT: v_perm_b32 v2, v3, v3, 0xc0c0302 +; GFX11-DL-TRUE16-NEXT: v_perm_b32 v1, v5, v5, 0xc0c0302 +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v2.l, v3.l, v0.l +; GFX11-DL-TRUE16-NEXT: v_perm_b32 v2, v4, v4, 0xc0c0302 ; GFX11-DL-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-DL-TRUE16-NEXT: v_dot4_u32_u8 v0, v2, v1, v0 -; GFX11-DL-TRUE16-NEXT: global_store_b16 v5, v0, s[4:5] +; GFX11-DL-TRUE16-NEXT: global_store_b16 v6, v0, s[4:5] ; GFX11-DL-TRUE16-NEXT: s_endpgm ; ; GFX11-DL-FAKE16-LABEL: notdot4_mixedtypes: @@ -1964,44 +1962,41 @@ define amdgpu_kernel void @notdot4_mixedtypes2(ptr addrspace(1) %src1, ; GFX11-DL-TRUE16-LABEL: notdot4_mixedtypes2: ; GFX11-DL-TRUE16: ; %bb.0: ; %entry ; GFX11-DL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 -; GFX11-DL-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-DL-TRUE16-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0x3ff, v0 ; GFX11-DL-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 -; GFX11-DL-TRUE16-NEXT: v_mov_b32_e32 v4, 0 -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-DL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX11-DL-TRUE16-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-DL-TRUE16-NEXT: s_clause 0x1 -; GFX11-DL-TRUE16-NEXT: global_load_b32 v2, v0, s[2:3] -; GFX11-DL-TRUE16-NEXT: global_load_b32 v3, v0, s[0:1] -; GFX11-DL-TRUE16-NEXT: global_load_d16_b16 v0, v4, s[4:5] +; GFX11-DL-TRUE16-NEXT: global_load_b32 v3, v0, s[2:3] +; GFX11-DL-TRUE16-NEXT: global_load_b32 v4, v0, s[0:1] +; GFX11-DL-TRUE16-NEXT: global_load_d16_b16 v0, v5, s[4:5] ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(2) -; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2 +; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v3 ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(1) -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l -; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v3 -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.h -; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3 +; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v4 +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v6, v4, 0, 8 +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.h ; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8 -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8 -; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v6.l -; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v2 -; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v2.l +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4) +; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l +; GFX11-DL-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v3.l ; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8 -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v5.l +; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v6.l +; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 24, v3 ; GFX11-DL-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v0.h, v1.l, v0.l -; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l -; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.h +; GFX11-DL-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v3.h ; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-DL-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v4 +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v2.l, v1.h, v0.l -; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v5, 0, 8 -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-DL-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8 ; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v1.l, v0.h, v0.l +; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-DL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l -; GFX11-DL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-DL-TRUE16-NEXT: v_mad_u16 v0.l, v3.l, v1.l, v0.l -; GFX11-DL-TRUE16-NEXT: global_store_b16 v4, v0, s[4:5] +; GFX11-DL-TRUE16-NEXT: global_store_b16 v5, v0, s[4:5] ; GFX11-DL-TRUE16-NEXT: s_endpgm ; ; GFX11-DL-FAKE16-LABEL: notdot4_mixedtypes2: diff --git a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll index f44faf4f7edba..3a4bf1c81ed58 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll @@ -424,15 +424,15 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) { ; GFX11-SDAG-TRUE16-LABEL: test_frexp_v2f16_v2i32: ; GFX11-SDAG-TRUE16: ; %bb.0: ; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l -; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h -; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h -; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.l, v0.h +; GFX11-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.h, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v0.h +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v1.h, v1.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v2, 0, 16 ; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 16 ; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32: @@ -457,15 +457,15 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) { ; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l -; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h -; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h -; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.l, v0.h +; GFX12-SDAG-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.h, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v0.h +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v1.h, v1.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v2, 0, 16 ; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-SDAG-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 16 ; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-SDAG-FAKE16-LABEL: test_frexp_v2f16_v2i32: @@ -534,15 +534,15 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) { ; GFX11-GISEL-TRUE16-LABEL: test_frexp_v2f16_v2i32: ; GFX11-GISEL-TRUE16: ; %bb.0: ; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l -; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h -; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l -; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h -; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16 -; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.l, v0.l +; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.h, v0.h +; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.l +; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v0.h +; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v1.l, v1.h +; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v2, 0, 16 ; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX11-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h +; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 16 ; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-GISEL-FAKE16-LABEL: test_frexp_v2f16_v2i32: @@ -567,15 +567,15 @@ define { <2 x half>, <2 x i32> } @test_frexp_v2f16_v2i32(<2 x half> %a) { ; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l -; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.h -; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l -; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.h, v0.h -; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16 -; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16 +; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.l, v0.l +; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.h, v0.h +; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v0.l +; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v0.h +; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v1.l, v1.h +; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v2, 0, 16 ; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) -; GFX12-GISEL-TRUE16-NEXT: v_pack_b32_f16 v0, v0.l, v0.h +; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 16 ; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-GISEL-FAKE16-LABEL: test_frexp_v2f16_v2i32: diff --git a/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll b/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll new file mode 100644 index 0000000000000..49dec15f9f7d7 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/sext-in-reg-vector-shuffle.ll @@ -0,0 +1,86 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11-TRUE16 %s +; RUN: llc -mtriple=amdgcn-- -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -enable-var-scope --check-prefixes=GFX11-FAKE16 %s + +define amdgpu_kernel void @v_sext_in_reg_i8_i16_shuffle_vector(ptr addrspace(1) %out, ptr addrspace(1) %ptr) #0 { +; +; GFX11-TRUE16-LABEL: v_sext_in_reg_i8_i16_shuffle_vector: +; GFX11-TRUE16: ; %bb.0: +; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0 +; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-TRUE16-NEXT: global_load_b64 v[1:2], v0, s[2:3] +; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.h +; GFX11-TRUE16-NEXT: v_bfe_i32 v7, v2, 0, 8 +; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v5, 24, v2 +; GFX11-TRUE16-NEXT: v_ashrrev_i32_e32 v6, 24, v1 +; GFX11-TRUE16-NEXT: v_bfe_i32 v8, v3, 0, 8 +; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.l, 8, v1.l +; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8 +; GFX11-TRUE16-NEXT: v_ashrrev_i16 v0.h, 8, v2.l +; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v7.l +; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l +; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v0.l, v0.l +; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v0.h, v0.h +; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v2.h, v6.l +; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v4.h, v5.l +; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v1.l, v1.l +; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v1.h, v2.l +; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v2.l, v3.l +; GFX11-TRUE16-NEXT: v_cvt_f16_i16_e32 v4.l, v4.l +; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, 0 +; GFX11-TRUE16-NEXT: v_pack_b32_f16 v3, v0.l, v1.l +; GFX11-TRUE16-NEXT: v_pack_b32_f16 v1, v0.h, v1.h +; GFX11-TRUE16-NEXT: v_pack_b32_f16 v2, v2.h, v2.l +; GFX11-TRUE16-NEXT: v_pack_b32_f16 v0, v4.h, v4.l +; GFX11-TRUE16-NEXT: global_store_b128 v5, v[0:3], s[0:1] +; GFX11-TRUE16-NEXT: s_endpgm +; +; GFX11-FAKE16-LABEL: v_sext_in_reg_i8_i16_shuffle_vector: +; GFX11-FAKE16: ; %bb.0: +; GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_and_b32 v0, 0x3ff, v0 +; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-FAKE16-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1 +; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0 +; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v2, 24, v1 +; GFX11-FAKE16-NEXT: v_ashrrev_i32_e32 v5, 24, v0 +; GFX11-FAKE16-NEXT: v_ashrrev_i16 v6, 8, v1 +; GFX11-FAKE16-NEXT: v_bfe_i32 v7, v0, 0, 8 +; GFX11-FAKE16-NEXT: v_ashrrev_i16 v0, 8, v0 +; GFX11-FAKE16-NEXT: v_bfe_i32 v1, v1, 0, 8 +; GFX11-FAKE16-NEXT: v_bfe_i32 v3, v3, 0, 8 +; GFX11-FAKE16-NEXT: v_bfe_i32 v4, v4, 0, 8 +; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v7, v7 +; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v0, v0 +; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v1, v1 +; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v6, v6 +; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v5, v5 +; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v8, v2 +; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v2, v4 +; GFX11-FAKE16-NEXT: v_cvt_f16_i16_e32 v4, v3 +; GFX11-FAKE16-NEXT: v_pack_b32_f16 v3, v0, v7 +; GFX11-FAKE16-NEXT: v_pack_b32_f16 v1, v6, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-FAKE16-NEXT: v_pack_b32_f16 v2, v5, v2 +; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v8, v4 +; GFX11-FAKE16-NEXT: global_store_b128 v9, v[0:3], s[0:1] +; GFX11-FAKE16-NEXT: s_endpgm + %tid = call i32 @llvm.amdgcn.workitem.id.x() + %in.gep = getelementptr <{ [0 x i8] }>, ptr addrspace(1) %ptr, i64 0, i32 0, i32 %tid + %load = load <8 x i8>, ptr addrspace(1) %in.gep + %shuff = shufflevector <8 x i8> %load, <8 x i8> poison, <8 x i32> + %cast = sitofp <8 x i8> %shuff to <8 x half> + store <8 x half> %cast, ptr addrspace(1) %out + ret void +} + +declare i32 @llvm.amdgcn.workitem.id.x() #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll index 2d4c881b855e8..16fbd1eabb305 100644 --- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll +++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smax.ll @@ -208,11 +208,16 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) { ; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v3i8: ; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry ; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v0.l, 0xff80 ; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -245,11 +250,16 @@ define i8 @test_vector_reduce_smax_v3i8(<3 x i8> %v) { ; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v0.l, 0xff80 ; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -790,7 +800,7 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) { ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v1, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v5, 0, 8 @@ -798,24 +808,27 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) { ; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v3.l ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v1.l, v5.l, v3.l, v1.l ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v6, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v1.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v5, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v6 +; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v0, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v1.l, v2.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v5, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v2.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l ; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -897,7 +910,7 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) { ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v1, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v5, 0, 8 @@ -905,24 +918,27 @@ define i8 @test_vector_reduce_smax_v8i8(<8 x i8> %v) { ; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v3.l ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v1.l, v5.l, v3.l, v1.l ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v6, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v1.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v5, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v6 +; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v0, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v1.l, v2.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v5, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v2.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l ; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -1291,51 +1307,59 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) { ; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smax_v16i8: ; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry ; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v11, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v17, v3, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v15, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v9, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v13, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v1, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v9.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v9.l, v13.l -; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v17.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v13.l, v16.l -; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v1.h, v5.l, v7.l -; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v3.h, v9.l, v11.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v2, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v15.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v17.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v9.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v11, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v15, v2, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v7, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v14, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v14, v6, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v0, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v5, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v6, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v8, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v1.l, v3.l, v13.l, v1.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v0, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v1, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v10, v10, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v2, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v14, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v1.l, v3.h, v1.h, v1.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v12, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v1.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l -; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v9 -; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.h, v1.l, v2.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v13.l +; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v15.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.l +; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.h, v2.l, v3.l ; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v1.h, v4.l, v5.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v8.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.h, v1.l, v2.l, v0.h +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v11.l, v12.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v9, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v6.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v8, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v14.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v17, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.h, v0.h, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v11, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v9.l +; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.h, v2.l, v3.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l +; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v10.l +; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v4.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v7 +; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v5.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.h, v2.l, v3.l, v0.h ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.h, v0.l, v0.h +; GFX11-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v1.l, v0.h ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l ; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l @@ -1444,51 +1468,59 @@ define i8 @test_vector_reduce_smax_v16i8(<16 x i8> %v) { ; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v11, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v17, v3, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v15, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v9, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v13, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v1, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v9.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v9.l, v13.l -; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v17.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v13.l, v16.l -; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v1.h, v5.l, v7.l -; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v3.h, v9.l, v11.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v2, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v15.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v17.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v9.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v11, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v15, v2, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v7, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v14, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v14, v6, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v0, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v5, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v6, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v8, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v1.l, v3.l, v13.l, v1.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v0, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v1, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v10, v10, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v2, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v14, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v1.l, v3.h, v1.h, v1.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v12, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v1.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l -; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v9 -; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.h, v1.l, v2.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v13.l +; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v15.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.l +; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.h, v2.l, v3.l ; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v1.h, v4.l, v5.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v8.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.h, v1.l, v2.l, v0.h +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v11.l, v12.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v9, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.l, v6.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v8, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v14.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v17, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.h, v0.h, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v11, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v9.l +; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.h, v2.l, v3.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l +; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v10.l +; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v1.l, v1.l, v4.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v7 +; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v5.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.h, v2.l, v3.l, v0.h ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v1.h, v0.l, v0.h +; GFX12-SDAG-TRUE16-NEXT: v_max3_i16 v0.l, v0.l, v1.l, v0.h ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l ; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-SDAG-TRUE16-NEXT: v_max_i16 v0.l, v0.l, v1.l diff --git a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll index d9d9a6b9a4b19..bb868621c23d7 100644 --- a/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll +++ b/llvm/test/CodeGen/AMDGPU/vector-reduce-smin.ll @@ -208,11 +208,16 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) { ; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v3i8: ; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry ; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v0.l, 0x7f ; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -245,11 +250,16 @@ define i8 @test_vector_reduce_smin_v3i8(<3 x i8> %v) { ; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v0.l, 0x7f ; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -790,7 +800,7 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) { ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v1, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v5, 0, 8 @@ -798,24 +808,27 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) { ; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v3.l ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v1.l, v5.l, v3.l, v1.l ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v6, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v1.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v5, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v6 +; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v0, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v1.l, v2.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v5, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v2.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l ; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -897,7 +910,7 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) { ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v1, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v5, 0, 8 @@ -905,24 +918,27 @@ define i8 @test_vector_reduce_smin_v8i8(<8 x i8> %v) { ; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v3.l ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v1.l, v5.l, v3.l, v1.l ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v6, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) -; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v1 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v6.l, 8, v1.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v5, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v6 +; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v0, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v1.l, v2.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v5, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v4, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v2.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l ; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31] ; @@ -1291,51 +1307,59 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) { ; GFX11-SDAG-TRUE16-LABEL: test_vector_reduce_smin_v16i8: ; GFX11-SDAG-TRUE16: ; %bb.0: ; %entry ; GFX11-SDAG-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v11, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v17, v3, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v15, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v9, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v13, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v1, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v9.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v9.l, v13.l -; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v17.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v13.l, v16.l -; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v1.h, v5.l, v7.l -; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v3.h, v9.l, v11.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v2, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v15.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v17.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v9.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v11, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v15, v2, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v7, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v14, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v14, v6, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v0, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v5, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v6, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v8, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v1.l, v3.l, v13.l, v1.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v0, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v1, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v10, v10, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v2, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v14, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v1.l, v3.h, v1.h, v1.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l -; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v12, 0, 8 -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v1.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l -; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v3.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v9 -; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.h, v1.l, v2.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v13.l +; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v15.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.l +; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.h, v2.l, v3.l ; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v1.h, v4.l, v5.l -; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v8.l -; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.h, v1.l, v2.l, v0.h +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v11.l, v12.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v9, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v6.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v8, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v14.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v17, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.h, v0.h, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v11, 0, 8 +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v9.l +; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.h, v2.l, v3.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l +; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v0.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l +; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v10.l +; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v4.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX11-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v7 +; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v5.l, v0.l +; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.h, v2.l, v3.l, v0.h ; GFX11-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8 ; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.h, v0.l, v0.h +; GFX11-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v1.l, v0.h ; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l ; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l @@ -1444,51 +1468,59 @@ define i8 @test_vector_reduce_smin_v16i8(<16 x i8> %v) { ; GFX12-SDAG-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_bvhcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v7, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v11, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v17, v3, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v15, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v9, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v13, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v1, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v9.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v9.l, v13.l -; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v17.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v13.l, v16.l -; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v1.h, v5.l, v7.l -; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v3.h, v9.l, v11.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v16, v2, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v15.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v17.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v9.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v11, v11, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v15, v2, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v3, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v7, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v14, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v14, v6, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v13.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v9.l, v4.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v13, v0, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v5, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v6, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v8, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v1.l, v3.l, v13.l, v1.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v8, v0, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v1, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v10, v10, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v7, v2, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v14, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v1.l, v3.h, v1.h, v1.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l -; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v3, v12, 0, 8 -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4) -; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v9.l, 8, v1.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v5.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v6.l -; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v3.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 8, v9 -; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.h, v1.l, v2.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v7.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v10.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v5.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v13.l +; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v15.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v11.l +; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.h, v2.l, v3.l ; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v1.h, v4.l, v5.l -; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v8.l -; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.h, v1.l, v2.l, v0.h +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v11.l, v12.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v9, v9, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.l, v6.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v6, v8, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v14.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v7.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v5, v17, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.h, v0.h, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v4, v11, 0, 8 +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v9.l +; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.h, v2.l, v3.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v16.l +; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b16 v7.l, 8, v0.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v6.l +; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v10.l +; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v1.l, v1.l, v4.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) +; GFX12-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 8, v7 +; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v5.l, v0.l +; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3) +; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.h, v2.l, v3.l, v0.h ; GFX12-SDAG-TRUE16-NEXT: v_bfe_i32 v2, v6, 0, 8 ; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v1.h, v0.l, v0.h +; GFX12-SDAG-TRUE16-NEXT: v_min3_i16 v0.l, v0.l, v1.l, v0.h ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.l ; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-SDAG-TRUE16-NEXT: v_min_i16 v0.l, v0.l, v1.l