From 87280cd9fcf13430780f71b3d7c0961508134734 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 13 Jun 2025 15:27:36 -0700 Subject: [PATCH 1/2] [RISCV] Simplify macros used for commuting vector multiply-accumulate instructions. NFC Inline some macros that were only instantiated once. Remove unused macros --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 65 ++++++++---------------- 1 file changed, 22 insertions(+), 43 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index e5d29e1a8b476..8a09067ecfc64 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3573,24 +3573,15 @@ std::string RISCVInstrInfo::createMIROperandComment( #define CASE_VMA_OPCODE_COMMON(OP, TYPE, LMUL) \ RISCV::PseudoV##OP##_##TYPE##_##LMUL -#define CASE_VMA_OPCODE_LMULS_M1(OP, TYPE) \ - CASE_VMA_OPCODE_COMMON(OP, TYPE, M1): \ +#define CASE_VMA_OPCODE_LMULS(OP, TYPE) \ + CASE_VMA_OPCODE_COMMON(OP, TYPE, MF8): \ + case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF4): \ + case CASE_VMA_OPCODE_COMMON(OP, TYPE, MF2): \ + case CASE_VMA_OPCODE_COMMON(OP, TYPE, M1): \ case CASE_VMA_OPCODE_COMMON(OP, TYPE, M2): \ case CASE_VMA_OPCODE_COMMON(OP, TYPE, M4): \ case CASE_VMA_OPCODE_COMMON(OP, TYPE, M8) -#define CASE_VMA_OPCODE_LMULS_MF2(OP, TYPE) \ - CASE_VMA_OPCODE_COMMON(OP, TYPE, MF2): \ - case CASE_VMA_OPCODE_LMULS_M1(OP, TYPE) - -#define CASE_VMA_OPCODE_LMULS_MF4(OP, TYPE) \ - CASE_VMA_OPCODE_COMMON(OP, TYPE, MF4): \ - case CASE_VMA_OPCODE_LMULS_MF2(OP, TYPE) - -#define CASE_VMA_OPCODE_LMULS(OP, TYPE) \ - CASE_VMA_OPCODE_COMMON(OP, TYPE, MF8): \ - case CASE_VMA_OPCODE_LMULS_MF4(OP, TYPE) - // VFMA instructions are SEW specific. #define CASE_VFMA_OPCODE_COMMON(OP, TYPE, LMUL, SEW) \ RISCV::PseudoV##OP##_##TYPE##_##LMUL##_##SEW @@ -3788,29 +3779,15 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI, Opc = RISCV::PseudoV##NEWOP##_##TYPE##_##LMUL; \ break; -#define CASE_VMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE) \ +#define CASE_VMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE) \ + CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \ + CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \ + CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \ CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M1) \ CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M2) \ CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M4) \ CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, M8) -#define CASE_VMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE) \ - CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2) \ - CASE_VMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE) - -#define CASE_VMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE) \ - CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4) \ - CASE_VMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE) - -#define CASE_VMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE) \ - CASE_VMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8) \ - CASE_VMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE) - -#define CASE_VMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP) \ - CASE_VMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16) \ - CASE_VMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VFPR32) \ - CASE_VMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VFPR64) - // VFMA depends on SEW. #define CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, LMUL, SEW) \ case RISCV::PseudoV##OLDOP##_##TYPE##_##LMUL##_##SEW: \ @@ -3827,18 +3804,14 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI, CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF2, SEW) \ CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, TYPE, SEW) -#define CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP) \ - CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16) \ - CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32) \ - CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64) - #define CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW) \ CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF4, SEW) \ CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, TYPE, SEW) -#define CASE_VFMA_CHANGE_OPCODE_LMULS(OLDOP, NEWOP, TYPE, SEW) \ - CASE_VFMA_CHANGE_OPCODE_COMMON(OLDOP, NEWOP, TYPE, MF8, SEW) \ - CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, TYPE, SEW) +#define CASE_VFMA_CHANGE_OPCODE_VV(OLDOP, NEWOP) \ + CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VV, E16) \ + CASE_VFMA_CHANGE_OPCODE_LMULS_MF2(OLDOP, NEWOP, VV, E32) \ + CASE_VFMA_CHANGE_OPCODE_LMULS_M1(OLDOP, NEWOP, VV, E64) #define CASE_VFMA_CHANGE_OPCODE_SPLATS(OLDOP, NEWOP) \ CASE_VFMA_CHANGE_OPCODE_LMULS_MF4(OLDOP, NEWOP, VFPR16, E16) \ @@ -3961,6 +3934,15 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI, return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); } +#undef CASE_VMA_CHANGE_OPCODE_COMMON +#undef CASE_VMA_CHANGE_OPCODE_LMULS +#undef CASE_VFMA_CHANGE_OPCODE_COMMON +#undef CASE_VFMA_CHANGE_OPCODE_LMULS_M1 +#undef CASE_VFMA_CHANGE_OPCODE_LMULS_MF2 +#undef CASE_VFMA_CHANGE_OPCODE_VV +#undef CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 +#undef CASE_VFMA_CHANGE_OPCODE_SPLATS + #undef CASE_RVV_OPCODE_UNMASK_LMUL #undef CASE_RVV_OPCODE_MASK_LMUL #undef CASE_RVV_OPCODE_LMUL @@ -3972,9 +3954,6 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI, #undef CASE_RVV_OPCODE #undef CASE_VMA_OPCODE_COMMON -#undef CASE_VMA_OPCODE_LMULS_M1 -#undef CASE_VMA_OPCODE_LMULS_MF2 -#undef CASE_VMA_OPCODE_LMULS_MF4 #undef CASE_VMA_OPCODE_LMULS #undef CASE_VFMA_OPCODE_COMMON #undef CASE_VFMA_OPCODE_LMULS_M1 From 38655c02f0cdf86958836fc5990de39e29ac0281 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 13 Jun 2025 15:46:24 -0700 Subject: [PATCH 2/2] fixup! reorder undefs slightly --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 8a09067ecfc64..f48ef5edb4223 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3939,8 +3939,8 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI, #undef CASE_VFMA_CHANGE_OPCODE_COMMON #undef CASE_VFMA_CHANGE_OPCODE_LMULS_M1 #undef CASE_VFMA_CHANGE_OPCODE_LMULS_MF2 -#undef CASE_VFMA_CHANGE_OPCODE_VV #undef CASE_VFMA_CHANGE_OPCODE_LMULS_MF4 +#undef CASE_VFMA_CHANGE_OPCODE_VV #undef CASE_VFMA_CHANGE_OPCODE_SPLATS #undef CASE_RVV_OPCODE_UNMASK_LMUL