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[X86][GlobalIsel] G_BITCAST support #144473

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[X86][GlobalIsel] G_BITCAST support #144473

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7e9a3d8
add bitcast
Jun 17, 2025
7c9a415
fix test
Jun 19, 2025
04abe43
fix review comment
Jun 19, 2025
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19 changes: 19 additions & 0 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -669,6 +669,8 @@ bool X86LegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
return legalizeSITOFP(MI, MRI, Helper);
case TargetOpcode::G_FPTOSI:
return legalizeFPTOSI(MI, MRI, Helper);
case TargetOpcode::G_BITCAST:
return legalizeBitcast(MI, MRI, Helper);
}
llvm_unreachable("expected switch to return");
}
Expand Down Expand Up @@ -835,6 +837,23 @@ bool X86LegalizerInfo::legalizeNarrowingStore(MachineInstr &MI,
return true;
}

bool X86LegalizerInfo::legalizeBitcast(MachineInstr &MI,
MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const {
MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
assert(!SrcTy.isVector() && "G_BITCAST does not support vectors yet");
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@Nic30 Nic30 Jun 17, 2025

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Is it correct to put assert there? It may be better to return false.

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@mahesh-attarde mahesh-attarde Jun 18, 2025

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Ok. It seems like multiple recurring pattern though

llvm-project/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp

Line 685 in 7e9a3d8

assert((SrcTy.getSizeInBits() == 16 || SrcTy.getSizeInBits() == 32 ||

llvm-project/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp

Line 634 in 7e9a3d8

assert((Opc == TargetOpcode::G_STORE || Opc == TargetOpcode::G_LOAD) &&

bool isCopy =
(SrcTy == DstTy) || (SrcTy.getSizeInBits() == DstTy.getSizeInBits());
if (isCopy) {
MIRBuilder.buildCopy(DstReg, SrcReg);
MI.eraseFromParent();
return true;
}
// For Vectors specific bitcasts
return Helper.lowerBitcast(MI) == LegalizerHelper::LegalizeResult::Legalized;
}

bool X86LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
return true;
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2 changes: 2 additions & 0 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
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Expand Up @@ -54,6 +54,8 @@ class X86LegalizerInfo : public LegalizerInfo {

bool legalizeFPTOSI(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
bool legalizeBitcast(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
};
} // namespace llvm
#endif
19 changes: 19 additions & 0 deletions llvm/test/CodeGen/X86/bitcast.ll
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@@ -1,23 +1,42 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=i686--
; RUN: llc < %s -mtriple=x86_64--
; RUN: llc < %s -mtriple=x86_64-- -global-isel -global-isel-abort=1 | FileCheck %s -check-prefixes=GISEL
; XRUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=1 | FileCheck %s -check-prefixes=GISEL
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@mahesh-attarde mahesh-attarde Jun 17, 2025

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i686 run is WIP

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@mahesh-attarde mahesh-attarde Jun 19, 2025

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done

; PR1033

define i64 @test1(double %t) {
; GISEL-LABEL: test1:
; GISEL: # %bb.0:
; GISEL-NEXT: movq %xmm0, %rax
; GISEL-NEXT: retq
%u = bitcast double %t to i64 ; <i64> [#uses=1]
ret i64 %u
}

define double @test2(i64 %t) {
; GISEL-LABEL: test2:
; GISEL: # %bb.0:
; GISEL-NEXT: movq %rdi, %xmm0
; GISEL-NEXT: retq
%u = bitcast i64 %t to double ; <double> [#uses=1]
ret double %u
}

define i32 @test3(float %t) {
; GISEL-LABEL: test3:
; GISEL: # %bb.0:
; GISEL-NEXT: movd %xmm0, %eax
; GISEL-NEXT: retq
%u = bitcast float %t to i32 ; <i32> [#uses=1]
ret i32 %u
}

define float @test4(i32 %t) {
; GISEL-LABEL: test4:
; GISEL: # %bb.0:
; GISEL-NEXT: movd %edi, %xmm0
; GISEL-NEXT: retq
%u = bitcast i32 %t to float ; <float> [#uses=1]
ret float %u
}
Expand Down
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