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[RISCV] Set the exact flag on the SRL created for converting vscale to a read of vlenb. #144571

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Merged
merged 4 commits into from
Jun 17, 2025
Merged

[RISCV] Set the exact flag on the SRL created for converting vscale to a read of vlenb. #144571

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2b7b12f
[RISCV] Set the exact flag on the SRL created for converting vscale t…
topperc Jun 17, 2025
82a2700
fixup! clang-format
topperc Jun 17, 2025
f9f69e7
fixup! Add to the earlier SRL for the power 2 case too.
topperc Jun 17, 2025
bbc3ce7
fixup! Really pass the flags to getNode.
topperc Jun 17, 2025
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11 changes: 8 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7360,20 +7360,25 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
uint64_t Val = Op.getConstantOperandVal(0);
if (isPowerOf2_64(Val)) {
uint64_t Log2 = Log2_64(Val);
if (Log2 < 3)
if (Log2 < 3) {
SDNodeFlags Flags;
Flags.setExact(true);
Res = DAG.getNode(ISD::SRL, DL, XLenVT, Res,
DAG.getConstant(3 - Log2, DL, VT));
else if (Log2 > 3)
} else if (Log2 > 3) {
Res = DAG.getNode(ISD::SHL, DL, XLenVT, Res,
DAG.getConstant(Log2 - 3, DL, XLenVT));
}
} else if ((Val % 8) == 0) {
// If the multiplier is a multiple of 8, scale it down to avoid needing
// to shift the VLENB value.
Res = DAG.getNode(ISD::MUL, DL, XLenVT, Res,
DAG.getConstant(Val / 8, DL, XLenVT));
} else {
SDNodeFlags Flags;
Flags.setExact(true);
SDValue VScale = DAG.getNode(ISD::SRL, DL, XLenVT, Res,
DAG.getConstant(3, DL, XLenVT));
DAG.getConstant(3, DL, XLenVT), Flags);
Res = DAG.getNode(ISD::MUL, DL, XLenVT, VScale,
DAG.getConstant(Val, DL, XLenVT));
}
Expand Down
12 changes: 5 additions & 7 deletions llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
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Expand Up @@ -290,8 +290,7 @@ define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_6(<vscale x 32 x i8> %vec) {
; CHECK-LABEL: extract_nxv32i8_nxv2i8_6:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: sub a0, a0, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a0
Expand All @@ -314,8 +313,7 @@ define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_22(<vscale x 32 x i8> %vec) {
; CHECK-LABEL: extract_nxv32i8_nxv2i8_22:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: slli a1, a1, 1
; CHECK-NEXT: srli a1, a0, 2
; CHECK-NEXT: sub a0, a0, a1
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v10, a0
Expand All @@ -341,9 +339,9 @@ define <vscale x 1 x i8> @extract_nxv4i8_nxv1i8_3(<vscale x 4 x i8> %vec) {
; CHECK-LABEL: extract_nxv4i8_nxv1i8_3:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: srli a0, a0, 3
; CHECK-NEXT: slli a1, a0, 1
; CHECK-NEXT: add a0, a1, a0
; CHECK-NEXT: srli a1, a0, 3
; CHECK-NEXT: srli a0, a0, 2
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vx v8, v8, a0
; CHECK-NEXT: ret
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll
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Expand Up @@ -257,9 +257,9 @@ define i32 @vector_length_vf3_i32(i32 zeroext %tc) {
; RV32-LABEL: vector_length_vf3_i32:
; RV32: # %bb.0:
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: srli a1, a1, 3
; RV32-NEXT: slli a2, a1, 1
; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: srli a2, a1, 3
; RV32-NEXT: srli a1, a1, 2
; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: bltu a0, a1, .LBB22_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a1
Expand All @@ -270,9 +270,9 @@ define i32 @vector_length_vf3_i32(i32 zeroext %tc) {
; RV64: # %bb.0:
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a1, a1, 3
; RV64-NEXT: slli a2, a1, 1
; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: srli a2, a1, 3
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: add a1, a1, a2
; RV64-NEXT: bltu a0, a1, .LBB22_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a1
Expand All @@ -286,9 +286,9 @@ define i32 @vector_length_vf3_XLen(iXLen zeroext %tc) {
; RV32-LABEL: vector_length_vf3_XLen:
; RV32: # %bb.0:
; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: srli a1, a1, 3
; RV32-NEXT: slli a2, a1, 1
; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: srli a2, a1, 3
; RV32-NEXT: srli a1, a1, 2
; RV32-NEXT: add a1, a1, a2
; RV32-NEXT: bltu a0, a1, .LBB23_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: mv a0, a1
Expand All @@ -299,9 +299,9 @@ define i32 @vector_length_vf3_XLen(iXLen zeroext %tc) {
; RV64: # %bb.0:
; RV64-NEXT: sext.w a0, a0
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: srli a1, a1, 3
; RV64-NEXT: slli a2, a1, 1
; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: srli a2, a1, 3
; RV64-NEXT: srli a1, a1, 2
; RV64-NEXT: add a1, a1, a2
; RV64-NEXT: bltu a0, a1, .LBB23_2
; RV64-NEXT: # %bb.1:
; RV64-NEXT: mv a0, a1
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,9 @@ define <vscale x 3 x i8> @load_nxv3i8(ptr %ptr) {
; CHECK-LABEL: load_nxv3i8:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: ret
Expand All @@ -22,9 +22,9 @@ define <vscale x 5 x half> @load_nxv5f16(ptr %ptr) {
; CHECK-LABEL: load_nxv5f16:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: slli a2, a1, 2
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: srli a1, a1, 1
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: ret
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
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Expand Up @@ -8,9 +8,9 @@ define void @store_nxv3i8(<vscale x 3 x i8> %val, ptr %ptr) {
; CHECK-LABEL: store_nxv3i8:
; CHECK: # %bb.0:
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: srli a1, a1, 3
; CHECK-NEXT: slli a2, a1, 1
; CHECK-NEXT: add a1, a2, a1
; CHECK-NEXT: srli a2, a1, 3
; CHECK-NEXT: srli a1, a1, 2
; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
; CHECK-NEXT: vse8.v v8, (a0)
; CHECK-NEXT: ret
Expand Down
15 changes: 6 additions & 9 deletions llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll
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Expand Up @@ -2300,10 +2300,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-RV64-NEXT: li a2, 0
; CHECK-RV64-NEXT: j .LBB98_5
; CHECK-RV64-NEXT: .LBB98_2: # %vector.ph
; CHECK-RV64-NEXT: slli a2, a2, 2
; CHECK-RV64-NEXT: negw a2, a2
; CHECK-RV64-NEXT: andi a2, a2, 256
; CHECK-RV64-NEXT: srli a3, a4, 1
; CHECK-RV64-NEXT: negw a2, a3
; CHECK-RV64-NEXT: andi a2, a2, 256
; CHECK-RV64-NEXT: slli a4, a4, 1
; CHECK-RV64-NEXT: mv a5, a0
; CHECK-RV64-NEXT: mv a6, a2
Expand Down Expand Up @@ -2395,10 +2394,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-NOZBB64-NEXT: li a2, 0
; CHECK-ZVKB-NOZBB64-NEXT: j .LBB98_5
; CHECK-ZVKB-NOZBB64-NEXT: .LBB98_2: # %vector.ph
; CHECK-ZVKB-NOZBB64-NEXT: slli a2, a2, 2
; CHECK-ZVKB-NOZBB64-NEXT: negw a2, a2
; CHECK-ZVKB-NOZBB64-NEXT: andi a2, a2, 256
; CHECK-ZVKB-NOZBB64-NEXT: srli a3, a4, 1
; CHECK-ZVKB-NOZBB64-NEXT: negw a2, a3
; CHECK-ZVKB-NOZBB64-NEXT: andi a2, a2, 256
; CHECK-ZVKB-NOZBB64-NEXT: slli a4, a4, 1
; CHECK-ZVKB-NOZBB64-NEXT: mv a5, a0
; CHECK-ZVKB-NOZBB64-NEXT: mv a6, a2
Expand Down Expand Up @@ -2489,10 +2487,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
; CHECK-ZVKB-ZBB64-NEXT: li a2, 0
; CHECK-ZVKB-ZBB64-NEXT: j .LBB98_5
; CHECK-ZVKB-ZBB64-NEXT: .LBB98_2: # %vector.ph
; CHECK-ZVKB-ZBB64-NEXT: slli a2, a2, 2
; CHECK-ZVKB-ZBB64-NEXT: negw a2, a2
; CHECK-ZVKB-ZBB64-NEXT: andi a2, a2, 256
; CHECK-ZVKB-ZBB64-NEXT: srli a3, a4, 1
; CHECK-ZVKB-ZBB64-NEXT: negw a2, a3
; CHECK-ZVKB-ZBB64-NEXT: andi a2, a2, 256
; CHECK-ZVKB-ZBB64-NEXT: slli a4, a4, 1
; CHECK-ZVKB-ZBB64-NEXT: mv a5, a0
; CHECK-ZVKB-ZBB64-NEXT: mv a6, a2
Expand Down
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