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4 changes: 2 additions & 2 deletions llvm/include/llvm/CodeGen/MachineScheduler.h
Original file line number Diff line number Diff line change
Expand Up @@ -1403,7 +1403,7 @@ createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
/// default scheduler if the target does not set a default.
/// Adds default DAG mutations.
template <typename Strategy = GenericScheduler>
LLVM_ABI ScheduleDAGMILive *createSchedLive(MachineSchedContext *C) {
ScheduleDAGMILive *createSchedLive(MachineSchedContext *C) {
ScheduleDAGMILive *DAG =
new ScheduleDAGMILive(C, std::make_unique<Strategy>(C));
// Register DAG post-processors.
Expand All @@ -1423,7 +1423,7 @@ LLVM_ABI ScheduleDAGMILive *createSchedLive(MachineSchedContext *C) {

/// Create a generic scheduler with no vreg liveness or DAG mutation passes.
template <typename Strategy = PostGenericScheduler>
LLVM_ABI ScheduleDAGMI *createSchedPostRA(MachineSchedContext *C) {
ScheduleDAGMI *createSchedPostRA(MachineSchedContext *C) {
ScheduleDAGMI *DAG = new ScheduleDAGMI(C, std::make_unique<Strategy>(C),
/*RemoveKillFlags=*/true);
const TargetSubtargetInfo &STI = C->MF->getSubtarget();
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8 changes: 4 additions & 4 deletions llvm/include/llvm/MC/MCExpr.h
Original file line number Diff line number Diff line change
Expand Up @@ -514,10 +514,10 @@ class LLVM_ABI MCSpecifierExpr : public MCExpr {
: MCExpr(Specifier, Loc), Expr(Expr), specifier(S) {}

public:
LLVM_ABI static const MCSpecifierExpr *
create(const MCExpr *Expr, Spec S, MCContext &Ctx, SMLoc Loc = SMLoc());
LLVM_ABI static const MCSpecifierExpr *
create(const MCSymbol *Sym, Spec S, MCContext &Ctx, SMLoc Loc = SMLoc());
static const MCSpecifierExpr *create(const MCExpr *Expr, Spec S,
MCContext &Ctx, SMLoc Loc = SMLoc());
static const MCSpecifierExpr *create(const MCSymbol *Sym, Spec S,
MCContext &Ctx, SMLoc Loc = SMLoc());

Spec getSpecifier() const { return specifier; }
const MCExpr *getSubExpr() const { return Expr; }
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