From f53b5ca9936506bb0c4ed182db055ce549d11454 Mon Sep 17 00:00:00 2001 From: guochen2 Date: Mon, 23 Jun 2025 23:14:46 -0400 Subject: [PATCH 1/3] fix mutli use list modification --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 7 ++++- .../AMDGPU/fix-sgpr-copies-f16-true16.mir | 26 +++++++++++++++++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 333e91bf37df5..cd0e0f65af0dc 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -8716,6 +8716,8 @@ void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist, void SIInstrInfo::addUsersToMoveToVALUWorklist( Register DstReg, MachineRegisterInfo &MRI, SIInstrWorklist &Worklist) const { + SmallVector> EarlyRangeInc; + for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg), E = MRI.use_end(); I != E;) { MachineInstr &UseMI = *I->getParent(); @@ -8744,11 +8746,14 @@ void SIInstrInfo::addUsersToMoveToVALUWorklist( ++I; } while (I != E && I->getParent() == &UseMI); } else { - legalizeOperandsVALUt16(UseMI, OpNo, MRI); + EarlyRangeInc.emplace_back(&UseMI, OpNo); ++I; } } + + for (auto &[UseMI, OpNo] : EarlyRangeInc) + legalizeOperandsVALUt16(*UseMI, OpNo, MRI); } void SIInstrInfo::movePackToVALU(SIInstrWorklist &Worklist, diff --git a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir index 9b6a2f3a1aa1e..59184499de2f0 100644 --- a/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir +++ b/llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir @@ -108,6 +108,32 @@ body: | %4:sreg_32 = S_FMAC_F16 %3:sreg_32, %3:sreg_32, %2:sreg_32, implicit $mode ... +--- +name: legalize_with_multi_user +body: | + bb.0: + ; GCN-LABEL: name: legalize_with_multi_user + ; GCN: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF + ; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF + ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF]], %subreg.lo16, [[DEF1]], %subreg.hi16 + ; GCN-NEXT: [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_ADD_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 1, 0, 0, 0, implicit $mode, implicit $exec + ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 + ; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF + ; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF + ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_ADD_F16_t16_e64_]], %subreg.lo16, [[DEF3]], %subreg.hi16 + ; GCN-NEXT: [[V_PK_FMA_F16_:%[0-9]+]]:vgpr_32 = V_PK_FMA_F16 11, [[S_MOV_B32_]], 0, [[REG_SEQUENCE1]], 8, [[DEF2]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec + ; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF + ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_ADD_F16_t16_e64_]], %subreg.lo16, [[DEF4]], %subreg.hi16 + ; GCN-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[REG_SEQUENCE2]], [[S_MOV_B32_]], implicit $exec + %0:vgpr_16 = IMPLICIT_DEF + %1:sreg_32 = COPY %0:vgpr_16 + %2:sreg_32 = S_ADD_F16 %1:sreg_32, 1, implicit $mode + %3:sreg_32 = S_MOV_B32 32768 + %4:vgpr_32 = IMPLICIT_DEF + %5:vgpr_32 = V_PK_FMA_F16 11, %3:sreg_32, 0, %2:sreg_32, 8, %4:vgpr_32, 0, 0, 0, 0, 0, implicit $mode, implicit $exec + %6:sreg_32 = S_XOR_B32 %2:sreg_32, %3:sreg_32, implicit-def dead $scc +... + --- name: vgpr16_to_spgr32 body: | From 40bc7a399d30eed1a059eff6348a5dffafca8d81 Mon Sep 17 00:00:00 2001 From: guochen2 Date: Tue, 24 Jun 2025 13:31:52 -0400 Subject: [PATCH 2/3] use early_inc_range --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 27 +++++++++++--------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index cd0e0f65af0dc..0407206e5a2a7 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -8716,11 +8716,9 @@ void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist, void SIInstrInfo::addUsersToMoveToVALUWorklist( Register DstReg, MachineRegisterInfo &MRI, SIInstrWorklist &Worklist) const { - SmallVector> EarlyRangeInc; - - for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg), - E = MRI.use_end(); I != E;) { - MachineInstr &UseMI = *I->getParent(); + MachineInstr *prevMI = nullptr; + for (MachineOperand &MO : make_early_inc_range(MRI.use_operands(DstReg))) { + MachineInstr &UseMI = *MO.getParent(); unsigned OpNo = 0; @@ -8735,25 +8733,22 @@ void SIInstrInfo::addUsersToMoveToVALUWorklist( case AMDGPU::INSERT_SUBREG: break; default: - OpNo = I.getOperandNo(); + OpNo = MO.getOperandNo(); break; } if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) { - Worklist.insert(&UseMI); + if (&UseMI == prevMI) + continue; - do { - ++I; - } while (I != E && I->getParent() == &UseMI); - } else { - EarlyRangeInc.emplace_back(&UseMI, OpNo); + prevMI = &UseMI; - ++I; + Worklist.insert(&UseMI); + } else { + // legalize could changes user list + legalizeOperandsVALUt16(UseMI, OpNo, MRI); } } - - for (auto &[UseMI, OpNo] : EarlyRangeInc) - legalizeOperandsVALUt16(*UseMI, OpNo, MRI); } void SIInstrInfo::movePackToVALU(SIInstrWorklist &Worklist, From 75ce40da0943189382b24a3c139cb115e2f0fa9d Mon Sep 17 00:00:00 2001 From: guochen2 Date: Tue, 24 Jun 2025 16:10:51 -0400 Subject: [PATCH 3/3] remove dup check --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 0407206e5a2a7..a2be3870bffca 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -8716,7 +8716,6 @@ void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist, void SIInstrInfo::addUsersToMoveToVALUWorklist( Register DstReg, MachineRegisterInfo &MRI, SIInstrWorklist &Worklist) const { - MachineInstr *prevMI = nullptr; for (MachineOperand &MO : make_early_inc_range(MRI.use_operands(DstReg))) { MachineInstr &UseMI = *MO.getParent(); @@ -8737,17 +8736,11 @@ void SIInstrInfo::addUsersToMoveToVALUWorklist( break; } - if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) { - if (&UseMI == prevMI) - continue; - - prevMI = &UseMI; - + if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) Worklist.insert(&UseMI); - } else { - // legalize could changes user list + else + // Legalization could change user list. legalizeOperandsVALUt16(UseMI, OpNo, MRI); - } } }