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[AMDGPU][True16][CodeGen] do not legalize t16 operand during user scan #145450

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Merged
merged 3 commits into from
Jun 25, 2025
Merged

[AMDGPU][True16][CodeGen] do not legalize t16 operand during user scan #145450

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f53b5ca
fix mutli use list modification
broxigarchen Jun 24, 2025
40bc7a3
use early_inc_range
broxigarchen Jun 24, 2025
75ce40d
remove dup check
broxigarchen Jun 24, 2025
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20 changes: 10 additions & 10 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8716,9 +8716,9 @@ void SIInstrInfo::splitScalar64BitCountOp(SIInstrWorklist &Worklist,
void SIInstrInfo::addUsersToMoveToVALUWorklist(
Register DstReg, MachineRegisterInfo &MRI,
SIInstrWorklist &Worklist) const {
for (MachineRegisterInfo::use_iterator I = MRI.use_begin(DstReg),
E = MRI.use_end(); I != E;) {
MachineInstr &UseMI = *I->getParent();
MachineInstr *prevMI = nullptr;
for (MachineOperand &MO : make_early_inc_range(MRI.use_operands(DstReg))) {
MachineInstr &UseMI = *MO.getParent();

unsigned OpNo = 0;

Expand All @@ -8733,20 +8733,20 @@ void SIInstrInfo::addUsersToMoveToVALUWorklist(
case AMDGPU::INSERT_SUBREG:
break;
default:
OpNo = I.getOperandNo();
OpNo = MO.getOperandNo();
break;
}

if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo))) {
Worklist.insert(&UseMI);
if (&UseMI == prevMI)
continue;

prevMI = &UseMI;

do {
++I;
} while (I != E && I->getParent() == &UseMI);
Worklist.insert(&UseMI);
} else {
// legalize could changes user list
legalizeOperandsVALUt16(UseMI, OpNo, MRI);

++I;
}
}
}
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26 changes: 26 additions & 0 deletions llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16-true16.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -108,6 +108,32 @@ body: |
%4:sreg_32 = S_FMAC_F16 %3:sreg_32, %3:sreg_32, %2:sreg_32, implicit $mode
...

---
name: legalize_with_multi_user
body: |
bb.0:
; GCN-LABEL: name: legalize_with_multi_user
; GCN: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
; GCN-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[DEF]], %subreg.lo16, [[DEF1]], %subreg.hi16
; GCN-NEXT: [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = V_ADD_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 1, 0, 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN-NEXT: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN-NEXT: [[DEF3:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_ADD_F16_t16_e64_]], %subreg.lo16, [[DEF3]], %subreg.hi16
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@Sisyph Sisyph Jun 24, 2025

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Is it reasonable to have one REG_SEQUENCE per use? I guess most or all of them will eventually fold out?

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@broxigarchen broxigarchen Jun 24, 2025

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reg_sequence should be fold out in the two-address, rewrite virtual reg and coalescer

; GCN-NEXT: [[V_PK_FMA_F16_:%[0-9]+]]:vgpr_32 = V_PK_FMA_F16 11, [[S_MOV_B32_]], 0, [[REG_SEQUENCE1]], 8, [[DEF2]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GCN-NEXT: [[DEF4:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_ADD_F16_t16_e64_]], %subreg.lo16, [[DEF4]], %subreg.hi16
; GCN-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[REG_SEQUENCE2]], [[S_MOV_B32_]], implicit $exec
%0:vgpr_16 = IMPLICIT_DEF
%1:sreg_32 = COPY %0:vgpr_16
%2:sreg_32 = S_ADD_F16 %1:sreg_32, 1, implicit $mode
%3:sreg_32 = S_MOV_B32 32768
%4:vgpr_32 = IMPLICIT_DEF
%5:vgpr_32 = V_PK_FMA_F16 11, %3:sreg_32, 0, %2:sreg_32, 8, %4:vgpr_32, 0, 0, 0, 0, 0, implicit $mode, implicit $exec
%6:sreg_32 = S_XOR_B32 %2:sreg_32, %3:sreg_32, implicit-def dead $scc
...

---
name: vgpr16_to_spgr32
body: |
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