From 09d76788555bf07ac652c4e6a0236c707882305e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 26 Jun 2025 10:08:49 -0700 Subject: [PATCH] [RISCV] Simplify the check for when to call EmitLoweredCascadedSelect. NFC Based on the comments and tests, we only want to call EmitLoweredCascadedSelect on selects of FP registers. Everytime we add a new branch with immediate opcode, we've been excluding it here. This patch switches to checking that the comparison operands are both registers so branch on immediate is automatically excluded. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 01722ee023060..683ce1fed9253 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -21444,12 +21444,8 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI, // EmitLoweredCascadedSelect. auto Next = next_nodbg(MI.getIterator(), BB->instr_end()); - if ((MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR && - MI.getOpcode() != RISCV::Select_GPR_Using_CC_SImm5_CV && - MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_SImm5NonZero_QC && - MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_UImm5NonZero_QC && - MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_SImm16NonZero_QC && - MI.getOpcode() != RISCV::Select_GPRNoX0_Using_CC_UImm16NonZero_QC) && + if (MI.getOpcode() != RISCV::Select_GPR_Using_CC_GPR && + MI.getOperand(1).isReg() && MI.getOperand(2).isReg() && Next != BB->end() && Next->getOpcode() == MI.getOpcode() && Next->getOperand(5).getReg() == MI.getOperand(0).getReg() && Next->getOperand(5).isKill())