diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll index 38c1f10f2c011..4a2c1fe2cf91c 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.gfx90a.ll @@ -1,18 +1,38 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s ; RUN: llc -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs -early-live-intervals < %s | FileCheck -check-prefixes=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx90a -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s -; GCN-LABEL: {{^}}load_1d: -; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm{{$}} define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, i32 %s) { +; GCN-LABEL: load_1d: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_1d_lwe: -; GCN: image_load v[0:4], v{{[0-9]+}}, s[0:7] dmask:0xf unorm lwe{{$}} define amdgpu_ps <4 x float> @load_1d_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s) { +; GCN-LABEL: load_1d_lwe: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v6, v0 +; GCN-NEXT: v_mov_b32_e32 v9, v8 +; GCN-NEXT: v_mov_b32_e32 v10, v8 +; GCN-NEXT: v_mov_b32_e32 v11, v8 +; GCN-NEXT: v_mov_b32_e32 v12, v8 +; GCN-NEXT: v_mov_b32_e32 v0, v8 +; GCN-NEXT: v_mov_b32_e32 v1, v9 +; GCN-NEXT: v_mov_b32_e32 v2, v10 +; GCN-NEXT: v_mov_b32_e32 v3, v11 +; GCN-NEXT: v_mov_b32_e32 v4, v12 +; GCN-NEXT: image_load v[0:4], v6, s[0:7] dmask:0xf unorm lwe +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: global_store_dword v8, v4, s[8:9] +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call {<4 x float>, i32} @llvm.amdgcn.image.load.1d.v4f32i32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 2, i32 0) %v.vec = extractvalue {<4 x float>, i32} %v, 0 @@ -21,32 +41,39 @@ main_body: ret <4 x float> %v.vec } -; GCN-LABEL: {{^}}load_2d: -; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm{{$}} define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, i32 %s, i32 %t) { +; GCN-LABEL: load_2d: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_3d: -; GCN: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm{{$}} define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) { +; GCN-LABEL: load_3d: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_cube: -; GCN: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm da{{$}} define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice) { +; GCN-LABEL: load_cube: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm da +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_cube_lwe: -; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe da{{$}} define amdgpu_ps <4 x float> @load_cube_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %slice) { main_body: %v = call {<4 x float>,i32} @llvm.amdgcn.image.load.cube.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 2, i32 0) @@ -56,24 +83,28 @@ main_body: ret <4 x float> %v.vec } -; GCN-LABEL: {{^}}load_1darray: -; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm da{{$}} define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, i32 %s, i32 %slice) { +; GCN-LABEL: load_1darray: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm da +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i32(i32 15, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_2darray: -; GCN: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm da{{$}} define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice) { +; GCN-LABEL: load_2darray: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm da +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_2darray_lwe: -; GCN: image_load v[0:4], v[{{[0-9]+:[0-9]+}}], s[0:7] dmask:0xf unorm lwe da{{$}} define amdgpu_ps <4 x float> @load_2darray_lwe(<8 x i32> inreg %rsrc, ptr addrspace(1) inreg %out, i32 %s, i32 %t, i32 %slice) { main_body: %v = call {<4 x float>,i32} @llvm.amdgcn.image.load.2darray.v4f32i32.i32(i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 2, i32 0) @@ -83,184 +114,235 @@ main_body: ret <4 x float> %v.vec } -; GCN-LABEL: {{^}}load_2dmsaa: -; GCN: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm{{$}} define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %fragid) { +; GCN-LABEL: load_2dmsaa: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v[0:2], s[0:7] dmask:0xf unorm +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_2darraymsaa: -; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}} define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) { +; GCN-LABEL: load_2darraymsaa: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_1d_addr_align: -; GCN: v_mov_b32_e32 [[VADDR:v[0-9]?[02468]]], v1 -; GCN: image_load v[0:3], [[VADDR]], s[0:7] dmask:0xf unorm{{$}} define amdgpu_ps <4 x float> @load_1d_addr_align(<8 x i32> inreg %rsrc, <2 x i32> %s) { +; GCN-LABEL: load_1d_addr_align: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: v_mov_b32_e32 v0, v1 +; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %s1 = extractelement <2 x i32> %s, i32 1 %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s1, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } -; GCN-LABEL: {{^}}store_1d: -; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm{{$}} define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) { +; GCN-LABEL: store_1d: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}store_2d: -; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm{{$}} define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t) { +; GCN-LABEL: store_2d: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}store_3d: -; GCN: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm{{$}} define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %r) { +; GCN-LABEL: store_3d: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.3d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}store_cube: -; GCN: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm da{{$}} define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice) { +; GCN-LABEL: store_cube: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm da +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.cube.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}store_1darray: -; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm da{{$}} define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %slice) { +; GCN-LABEL: store_1darray: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm da +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.1darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}store_2darray: -; GCN: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm da{{$}} define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice) { +; GCN-LABEL: store_2darray: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm da +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.2darray.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}store_2dmsaa: -; GCN: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm{{$}} define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %fragid) { +; GCN-LABEL: store_2dmsaa: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v[4:6], s[0:7] dmask:0xf unorm +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}store_2darraymsaa: -; GCN: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm da{{$}} define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s, i32 %t, i32 %slice, i32 %fragid) { +; GCN-LABEL: store_2darraymsaa: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v[4:7], s[0:7] dmask:0xf unorm da +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}load_1d_V1: -; GCN: image_load v0, v0, s[0:7] dmask:0x8 unorm{{$}} define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, i32 %s) { +; GCN-LABEL: load_1d_V1: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v0, v0, s[0:7] dmask:0x8 unorm +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call float @llvm.amdgcn.image.load.1d.f32.i32(i32 8, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) ret float %v } -; GCN-LABEL: {{^}}load_1d_V2: -; GCN: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm{{$}} define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, i32 %s) { +; GCN-LABEL: load_1d_V2: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i32(i32 9, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) ret <2 x float> %v } -; GCN-LABEL: {{^}}store_1d_V1: -; GCN: v_mov_b32_e32 [[VADDR:v[0-9]?[02468]]], v1 -; GCN: image_store v0, [[VADDR]], s[0:7] dmask:0x2 unorm{{$}} define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, i32 %s) { +; GCN-LABEL: store_1d_V1: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: v_mov_b32_e32 v2, v1 +; GCN-NEXT: image_store v0, v2, s[0:7] dmask:0x2 unorm +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.1d.f32.i32(float %vdata, i32 2, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}store_1d_V2: -; GCN: image_store v[0:1], v2, s[0:7] dmask:0xc unorm{{$}} define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, i32 %s) { +; GCN-LABEL: store_1d_V2: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:1], v2, s[0:7] dmask:0xc unorm +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.1d.v2f32.i32(<2 x float> %vdata, i32 12, i32 %s, <8 x i32> %rsrc, i32 0, i32 0) ret void } -; GCN-LABEL: {{^}}load_1d_glc: -; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc{{$}} define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, i32 %s) { +; GCN-LABEL: load_1d_glc: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_1d_slc: -; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc{{$}} define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, i32 %s) { +; GCN-LABEL: load_1d_slc: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2) ret <4 x float> %v } -; GCN-LABEL: {{^}}load_1d_glc_slc: -; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc{{$}} define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, i32 %s) { +; GCN-LABEL: load_1d_glc_slc: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3) ret <4 x float> %v } -; GCN-LABEL: {{^}}store_1d_glc: -; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc{{$}} define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) { +; GCN-LABEL: store_1d_glc: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 1) ret void } -; GCN-LABEL: {{^}}store_1d_slc: -; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc{{$}} define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) { +; GCN-LABEL: store_1d_slc: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 2) ret void } -; GCN-LABEL: {{^}}store_1d_glc_slc: -; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc{{$}} define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, i32 %s) { +; GCN-LABEL: store_1d_glc_slc: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %vdata, i32 15, i32 %s, <8 x i32> %rsrc, i32 0, i32 3) ret void } -; GCN-LABEL: {{^}}image_store_wait: -; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf -; SI: s_waitcnt expcnt(0) -; GCN: image_load v[0:3], v4, s[8:15] dmask:0xf -; GCN: s_waitcnt vmcnt(0) -; GCN: image_store v[0:3], v4, s[16:23] dmask:0xf define amdgpu_ps void @image_store_wait(<8 x i32> inreg %arg, <8 x i32> inreg %arg1, <8 x i32> inreg %arg2, <4 x float> %arg3, i32 %arg4) #0 { +; GCN-LABEL: image_store_wait: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: image_store v[0:3], v4, s[0:7] dmask:0xf unorm +; GCN-NEXT: image_load v[0:3], v4, s[8:15] dmask:0xf unorm +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: image_store v[0:3], v4, s[16:23] dmask:0xf unorm +; GCN-NEXT: s_endpgm main_body: call void @llvm.amdgcn.image.store.1d.v4f32.i32(<4 x float> %arg3, i32 15, i32 %arg4, <8 x i32> %arg, i32 0, i32 0) %data = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i32(i32 15, i32 %arg4, <8 x i32> %arg1, i32 0, i32 0) @@ -268,8 +350,6 @@ main_body: ret void } -; GCN-LABEL: image_load_mmo -; GCN: image_load v1, v[{{[0-9:]+}}], s[0:7] dmask:0x1 unorm define amdgpu_ps float @image_load_mmo(<8 x i32> inreg %rsrc, ptr addrspace(3) %lds, <2 x i32> %c) #0 { store float 0.000000e+00, ptr addrspace(3) %lds %c0 = extractelement <2 x i32> %c, i32 0 @@ -280,9 +360,13 @@ define amdgpu_ps float @image_load_mmo(<8 x i32> inreg %rsrc, ptr addrspace(3) % ret float %tex } -; GCN: v_mov_b32_e32 [[VADDR:v[0-9]?[02468]]], v1 -; GCN: image_get_resinfo v[0:3], [[VADDR]], s[0:7] dmask:0xf unorm define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i32> %s) { +; GCN-LABEL: getresinfo_1d: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: v_mov_b32_e32 v0, v1 +; GCN-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: ; return to shader part epilog main_body: %s1 = extractelement <2 x i32> %s, i32 1 %v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i32(i32 15, i32 %s1, <8 x i32> %rsrc, i32 0, i32 0)