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[AMDGPU][MC] Fix disassembly for v_permlane16_swap_b32 for GFX950 #146600

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Merged
merged 1 commit into from
Jul 2, 2025
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[AMDGPU][MC] Fix disassembly for v_permlane16_swap_b32 for GFX950 #146600

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4 changes: 2 additions & 2 deletions llvm/lib/Target/AMDGPU/VOP1Instructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -389,8 +389,8 @@ def VOP_PERMLANE_SWAP : VOPProfile<[i32, i32, untyped, untyped]> {
let HasExtDPP = 0;
let HasExtSDWA = 0;

let Ins32 = (ins Src0RC64:$vdst_in, Src0RC32:$src0);
let Ins64 = (ins Src0RC64:$vdst_in, Src0RC64:$src0, Dpp16FI:$fi, DppBoundCtrl:$bound_ctrl);
let Ins32 = (ins DstRC:$vdst_in, Src0RC32:$src0);
let Ins64 = (ins DstRC64:$vdst_in, Src0RC64:$src0, Dpp16FI:$fi, DppBoundCtrl:$bound_ctrl);
let InsVOP3OpSel = (ins Src0RC64:$vdst_in, Src0RC64:$src0, Dpp16FI:$fi, DppBoundCtrl:$bound_ctrl);
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@Sisyph Sisyph Jul 2, 2025

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As a side question, is it necessary to have InsVOP3OpSel here? It is not typical to have to override both InsVOP3OpSel and Ins64 in a profile.

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@jwanggit86 jwanggit86 Jul 2, 2025

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Good question. I'll look into it.

let Asm64 = "$vdst, $src0$bound_ctrl$fi";
}
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24 changes: 24 additions & 0 deletions llvm/test/MC/AMDGPU/gfx950_asm_features.s
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Expand Up @@ -40,14 +40,26 @@ global_load_lds_dwordx4 v2, s[4:5] offset:4
// GFX950: v_permlane16_swap_b32_e32 v1, v2 ; encoding: [0x02,0xb3,0x02,0x7e]
v_permlane16_swap_b32 v1, v2

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane16_swap_b32_e32 v218, v219 ; encoding: [0xdb,0xb3,0xb4,0x7f]
v_permlane16_swap_b32 v218, v219

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane16_swap_b32_e32 v1, v2 ; encoding: [0x02,0xb3,0x02,0x7e]
v_permlane16_swap_b32_e32 v1, v2

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane16_swap_b32_e32 v218, v219 ; encoding: [0xdb,0xb3,0xb4,0x7f]
v_permlane16_swap_b32_e32 v218, v219

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane16_swap_b32_e64 v1, v2 ; encoding: [0x01,0x00,0x99,0xd1,0x02,0x01,0x00,0x00]
v_permlane16_swap_b32_e64 v1, v2

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane16_swap_b32_e64 v218, v219 ; encoding: [0xda,0x00,0x99,0xd1,0xdb,0x01,0x00,0x00]
v_permlane16_swap_b32_e64 v218, v219

// FIXME: Parsed as bound_ctrl:1?
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane16_swap_b32_e64 v1, v2 bound_ctrl:1 ; encoding: [0x01,0x10,0x99,0xd1,0x02,0x01,0x00,0x00]
Expand Down Expand Up @@ -81,14 +93,26 @@ v_permlane16_swap_b32_e64 v1, v2 bound_ctrl:1 fi:1
// GFX950: v_permlane32_swap_b32_e32 v1, v2 ; encoding: [0x02,0xb5,0x02,0x7e]
v_permlane32_swap_b32 v1, v2

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane32_swap_b32_e32 v218, v219 ; encoding: [0xdb,0xb5,0xb4,0x7f]
v_permlane32_swap_b32 v218, v219

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane32_swap_b32_e32 v1, v2 ; encoding: [0x02,0xb5,0x02,0x7e]
v_permlane32_swap_b32_e32 v1, v2

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane32_swap_b32_e32 v218, v219 ; encoding: [0xdb,0xb5,0xb4,0x7f]
v_permlane32_swap_b32_e32 v218, v219

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane32_swap_b32_e64 v1, v2 ; encoding: [0x01,0x00,0x9a,0xd1,0x02,0x01,0x00,0x00]
v_permlane32_swap_b32_e64 v1, v2

// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane32_swap_b32_e64 v218, v219 ; encoding: [0xda,0x00,0x9a,0xd1,0xdb,0x01,0x00,0x00]
v_permlane32_swap_b32_e64 v218, v219

// FIXME: Parsed as bound_ctrl:1?
// NOT-GFX950: :[[@LINE+2]]:{{[0-9]+}}: error:
// GFX950: v_permlane32_swap_b32_e64 v1, v2 bound_ctrl:1 ; encoding: [0x01,0x10,0x9a,0xd1,0x02,0x01,0x00,0x00]
Expand Down
36 changes: 36 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx950.txt
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Expand Up @@ -47,9 +47,27 @@
# GFX950: v_permlane16_swap_b32_e32 v1, v2 ; encoding: [0x02,0xb3,0x02,0x7e]
0x02,0xb3,0x02,0x7e

# GFX950: v_permlane16_swap_b32_e32 v218, v219 ; encoding: [0xdb,0xb3,0xb4,0x7f]
0xdb,0xb3,0xb4,0x7f

# GFX950: v_permlane16_swap_b32_e32 v218, v2 ; encoding: [0x02,0xb3,0xb4,0x7f]
0x02,0xb3,0xb4,0x7f

# GFX950: v_permlane16_swap_b32_e32 v2, v219 ; encoding: [0xdb,0xb3,0x04,0x7e]
0xdb,0xb3,0x04,0x7e

# GFX950: v_permlane16_swap_b32_e64 v1, v2 ; encoding: [0x01,0x00,0x99,0xd1,0x02,0x01,0x00,0x00]
0x01,0x00,0x99,0xd1,0x02,0x01,0x00,0x00

# GFX950: v_permlane16_swap_b32_e64 v218, v219 ; encoding: [0xda,0x00,0x99,0xd1,0xdb,0x01,0x00,0x00]
0xda,0x00,0x99,0xd1,0xdb,0x01,0x00,0x00

# GFX950: v_permlane16_swap_b32_e64 v218, v2 ; encoding: [0xda,0x00,0x99,0xd1,0x02,0x01,0x00,0x00]
0xda,0x00,0x99,0xd1,0x02,0x01,0x00,0x00

# GFX950: v_permlane16_swap_b32_e64 v2, v219 ; encoding: [0x02,0x00,0x99,0xd1,0xdb,0x01,0x00,0x00]
0x02,0x00,0x99,0xd1,0xdb,0x01,0x00,0x00

# GFX950: v_permlane16_swap_b32_e64 v1, v2 bound_ctrl:1 ; encoding: [0x01,0x10,0x99,0xd1,0x02,0x01,0x00,0x00]
0x01,0x10,0x99,0xd1,0x02,0x01,0x00,0x00

Expand All @@ -63,9 +81,27 @@
# GFX950: v_permlane32_swap_b32_e32 v1, v2 ; encoding: [0x02,0xb5,0x02,0x7e]
0x02,0xb5,0x02,0x7e

# GFX950: v_permlane32_swap_b32_e32 v218, v219 ; encoding: [0xdb,0xb5,0xb4,0x7f]
0xdb,0xb5,0xb4,0x7f

# GFX950: v_permlane32_swap_b32_e32 v218, v2 ; encoding: [0x02,0xb5,0xb4,0x7f]
0x02,0xb5,0xb4,0x7f

# GFX950: v_permlane32_swap_b32_e32 v2, v219 ; encoding: [0xdb,0xb5,0x04,0x7e]
0xdb,0xb5,0x04,0x7e

# GFX950: v_permlane32_swap_b32_e64 v1, v2 ; encoding: [0x01,0x00,0x9a,0xd1,0x02,0x01,0x00,0x00]
0x01,0x00,0x9a,0xd1,0x02,0x01,0x00,0x00

# GFX950: v_permlane32_swap_b32_e64 v218, v219 ; encoding: [0xda,0x00,0x9a,0xd1,0xdb,0x01,0x00,0x00]
0xda,0x00,0x9a,0xd1,0xdb,0x01,0x00,0x00

# GFX950: v_permlane32_swap_b32_e64 v218, v2 ; encoding: [0xda,0x00,0x9a,0xd1,0x02,0x01,0x00,0x00]
0xda,0x00,0x9a,0xd1,0x02,0x01,0x00,0x00

# GFX950: v_permlane32_swap_b32_e64 v2, v219 ; encoding: [0x02,0x00,0x9a,0xd1,0xdb,0x01,0x00,0x00]
0x02,0x00,0x9a,0xd1,0xdb,0x01,0x00,0x00

# GFX950: v_permlane32_swap_b32_e64 v1, v2 bound_ctrl:1 ; encoding: [0x01,0x10,0x9a,0xd1,0x02,0x01,0x00,0x00]
0x01,0x10,0x9a,0xd1,0x02,0x01,0x00,0x00

Expand Down
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