From 1757d5e4fbdefbc9f8a499391090639475a08c10 Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Wed, 9 Jul 2025 17:46:23 +0800 Subject: [PATCH 01/10] [AMDGPU] Support function attribute to override postRA scheduling direction --- llvm/include/llvm/CodeGen/MachineScheduler.h | 1 + llvm/lib/CodeGen/MachineScheduler.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 17 +++++++++++++++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h index efda7eb8ffc8d..dbb7810791e52 100644 --- a/llvm/include/llvm/CodeGen/MachineScheduler.h +++ b/llvm/include/llvm/CodeGen/MachineScheduler.h @@ -116,6 +116,7 @@ enum Direction { } // namespace MISched LLVM_ABI extern cl::opt PreRADirection; +LLVM_ABI extern cl::opt PostRADirection; LLVM_ABI extern cl::opt VerifyScheduling; #ifndef NDEBUG extern cl::opt ViewMISchedDAGs; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 9d5c39ce7ae76..183b8d5f0714e 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -190,7 +190,7 @@ cl::opt PreRADirection( clEnumValN(MISched::Bidirectional, "bidirectional", "Force bidirectional pre reg-alloc list scheduling"))); -static cl::opt PostRADirection( +cl::opt PostRADirection( "misched-postra-direction", cl::Hidden, cl::desc("Post reg-alloc list scheduling direction"), cl::init(MISched::Unspecified), diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index c1f17033d04a8..6c923ac26b1e2 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -1153,6 +1153,23 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const { ScheduleDAGInstrs * GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const { + Attribute PostRADirectionAttr = + C->MF->getFunction().getFnAttribute("misched-postra-direction"); + + if (PostRADirectionAttr.isValid()) { + StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString(); + if (PostRADirectionStr == "topdown") + PostRADirection = MISched::TopDown; + else if (PostRADirectionStr == "bottomup") + PostRADirection = MISched::BottomUp; + else if (PostRADirectionStr == "bidirectional") + PostRADirection = MISched::Bidirectional; + else + report_fatal_error( + Twine("invalid value for 'misched-postra-direction' attribute: ") + + PostRADirectionStr); + } + ScheduleDAGMI *DAG = new GCNPostScheduleDAGMILive(C, std::make_unique(C), /*RemoveKillFlags=*/true); From 81edefe5886334f53a78926a980cdfeb50ed3d58 Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Sun, 13 Jul 2025 20:54:37 +0800 Subject: [PATCH 02/10] [AMDGPU] Add a new attr and lit test. --- llvm/lib/CodeGen/MachineScheduler.cpp | 19 ++++++++++ .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 19 +++++++--- .../CodeGen/AMDGPU/postra-sched-attribute.ll | 38 +++++++++++++++++++ 3 files changed, 71 insertions(+), 5 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 183b8d5f0714e..4be575fe069c3 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -4336,6 +4336,25 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin, RegionPolicy.OnlyTopDown = false; } + LLVM_DEBUG({ + const char *DirStr = "default"; + switch (PostRADirection) { + case MISched::TopDown: + DirStr = "topdown"; + break; + case MISched::BottomUp: + DirStr = "bottomup"; + break; + case MISched::Bidirectional: + DirStr = "bidirectional"; + break; + default:; + } + + dbgs() << "Post-MI-sched direction (" << MF.getName() << "): " << DirStr + << '\n'; + }); + BotIdx = NumRegionInstrs - 1; this->NumRegionInstrs = NumRegionInstrs; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 6c923ac26b1e2..3f4c931ef5830 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -460,6 +460,11 @@ static cl::opt cl::desc("Select custom AMDGPU scheduling strategy."), cl::Hidden, cl::init("")); +static cl::opt + AMDGPUPostRADirection("amdgpu-post-ra-direction", + cl::desc("Select custom AMDGPU postRA direction."), + cl::Hidden, cl::init("")); + static cl::opt EnableRewritePartialRegUses( "amdgpu-enable-rewrite-partial-reg-uses", cl::desc("Enable rewrite partial reg uses pass"), cl::init(true), @@ -1154,7 +1159,7 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const { ScheduleDAGInstrs * GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const { Attribute PostRADirectionAttr = - C->MF->getFunction().getFnAttribute("misched-postra-direction"); + C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction"); if (PostRADirectionAttr.isValid()) { StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString(); @@ -1164,10 +1169,14 @@ GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const { PostRADirection = MISched::BottomUp; else if (PostRADirectionStr == "bidirectional") PostRADirection = MISched::Bidirectional; - else - report_fatal_error( - Twine("invalid value for 'misched-postra-direction' attribute: ") + - PostRADirectionStr); + else { + PostRADirection = MISched::Unspecified; + DiagnosticInfoOptimizationFailure Diag( + C->MF->getFunction(), C->MF->getFunction().getSubprogram(), + Twine("invalid value for postRa direction attribute: '") + + PostRADirectionStr); + C->MF->getFunction().getContext().diagnose(Diag); + } } ScheduleDAGMI *DAG = diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll new file mode 100644 index 0000000000000..7d9422d81c129 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll @@ -0,0 +1,38 @@ +; REQUIRES: asserts + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefixes=WARNING %s + +; CHECK-LABEL: {{^}}postra-sched-topdown: +; CHECK: Post-MI-sched direction (postra-sched-topdown): topdown +define float @postra-sched-topdown(float %input) nounwind #0 { + %x = fadd float %input, 1.000000e+00 + ret float %x +} + +; CHECK-LABEL: {{^}}postra-sched-bottomup: +; CHECK: Post-MI-sched direction (postra-sched-bottomup): bottomup +define float @postra-sched-bottomup(float %input) nounwind #1 { + %x = fsub float %input, 1.000000e+00 + ret float %x +} + +; CHECK-LABEL: {{^}}postra-sched-bidirectional: +; CHECK: Post-MI-sched direction (postra-sched-bidirectional): bidirectional +define float @postra-sched-bidirectional(float %input) nounwind #2 { + %x = fadd float %input, 1.000000e+00 + ret float %x +} + +; CHECK-LABEL: {{^}}postra-sched-warning: +; CHECK: Post-MI-sched direction (postra-sched-warning): default +; WARNING: invalid value for postRa direction attribute +define float @postra-sched-warning(float %input) nounwind #3 { + %x = fsub float %input, 1.000000e+00 + ret float %x +} + +attributes #0 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="topdown"} +attributes #1 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bottomup"} +attributes #2 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bidirectional"} +attributes #3 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="warning"} From 7058279b4de84de83406ec4959c4c15e20c20eba Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Mon, 14 Jul 2025 09:51:36 +0800 Subject: [PATCH 03/10] [AMDGPU] Remove other att. --- llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll index 7d9422d81c129..c6f63f3b4a1b3 100644 --- a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll +++ b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll @@ -32,7 +32,7 @@ define float @postra-sched-warning(float %input) nounwind #3 { ret float %x } -attributes #0 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="topdown"} -attributes #1 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bottomup"} -attributes #2 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="bidirectional"} -attributes #3 = { alwaysinline nounwind memory(readwrite) "amdgpu-post-ra-direction"="warning"} +attributes #0 = {"amdgpu-post-ra-direction"="topdown"} +attributes #1 = {"amdgpu-post-ra-direction"="bottomup"} +attributes #2 = {"amdgpu-post-ra-direction"="bidirectional"} +attributes #3 = {"amdgpu-post-ra-direction"="warning"} From d3b78446a5b2e376a665b680e69736238c64b0a8 Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Tue, 15 Jul 2025 13:48:18 +0800 Subject: [PATCH 04/10] [AMDGPU] --- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 38 ++++++++++--------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 3f4c931ef5830..01a846c12778a 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -1158,24 +1158,26 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const { ScheduleDAGInstrs * GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const { - Attribute PostRADirectionAttr = - C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction"); - - if (PostRADirectionAttr.isValid()) { - StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString(); - if (PostRADirectionStr == "topdown") - PostRADirection = MISched::TopDown; - else if (PostRADirectionStr == "bottomup") - PostRADirection = MISched::BottomUp; - else if (PostRADirectionStr == "bidirectional") - PostRADirection = MISched::Bidirectional; - else { - PostRADirection = MISched::Unspecified; - DiagnosticInfoOptimizationFailure Diag( - C->MF->getFunction(), C->MF->getFunction().getSubprogram(), - Twine("invalid value for postRa direction attribute: '") + - PostRADirectionStr); - C->MF->getFunction().getContext().diagnose(Diag); + if (PostRADirection.getNumOccurrences() == 0) { + Attribute PostRADirectionAttr = + C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction"); + + if (PostRADirectionAttr.isValid()) { + StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString(); + if (PostRADirectionStr == "topdown") + PostRADirection = MISched::TopDown; + else if (PostRADirectionStr == "bottomup") + PostRADirection = MISched::BottomUp; + else if (PostRADirectionStr == "bidirectional") + PostRADirection = MISched::Bidirectional; + else { + PostRADirection = MISched::Unspecified; + DiagnosticInfoOptimizationFailure Diag( + C->MF->getFunction(), C->MF->getFunction().getSubprogram(), + Twine("invalid value for postRa direction attribute: '") + + PostRADirectionStr); + C->MF->getFunction().getContext().diagnose(Diag); + } } } From ec3de5762593719c28094c27abc3f1572d2c5027 Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Tue, 15 Jul 2025 20:00:37 +0800 Subject: [PATCH 05/10] [AMDGPU] Add post-RA scheduling direction control via target features --- llvm/include/llvm/CodeGen/MachineScheduler.h | 1 - llvm/lib/CodeGen/MachineScheduler.cpp | 21 +--------- llvm/lib/Target/AMDGPU/AMDGPUFeatures.td | 21 ++++++++++ llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 6 +++ .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 28 -------------- llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 34 +++++++++++++++++ llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 ++ .../CodeGen/AMDGPU/postra-sched-attribute.ll | 38 ------------------- .../AMDGPU/postra-sched-target-features.ll | 25 ++++++++++++ 9 files changed, 90 insertions(+), 87 deletions(-) delete mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll create mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h index dbb7810791e52..efda7eb8ffc8d 100644 --- a/llvm/include/llvm/CodeGen/MachineScheduler.h +++ b/llvm/include/llvm/CodeGen/MachineScheduler.h @@ -116,7 +116,6 @@ enum Direction { } // namespace MISched LLVM_ABI extern cl::opt PreRADirection; -LLVM_ABI extern cl::opt PostRADirection; LLVM_ABI extern cl::opt VerifyScheduling; #ifndef NDEBUG extern cl::opt ViewMISchedDAGs; diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index 4be575fe069c3..9d5c39ce7ae76 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -190,7 +190,7 @@ cl::opt PreRADirection( clEnumValN(MISched::Bidirectional, "bidirectional", "Force bidirectional pre reg-alloc list scheduling"))); -cl::opt PostRADirection( +static cl::opt PostRADirection( "misched-postra-direction", cl::Hidden, cl::desc("Post reg-alloc list scheduling direction"), cl::init(MISched::Unspecified), @@ -4336,25 +4336,6 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin, RegionPolicy.OnlyTopDown = false; } - LLVM_DEBUG({ - const char *DirStr = "default"; - switch (PostRADirection) { - case MISched::TopDown: - DirStr = "topdown"; - break; - case MISched::BottomUp: - DirStr = "bottomup"; - break; - case MISched::Bidirectional: - DirStr = "bidirectional"; - break; - default:; - } - - dbgs() << "Post-MI-sched direction (" << MF.getName() << "): " << DirStr - << '\n'; - }); - BotIdx = NumRegionInstrs - 1; this->NumRegionInstrs = NumRegionInstrs; } diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td index 74d1faeb6f545..870144f43b993 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td @@ -6,6 +6,10 @@ // //===----------------------------------------------------------------------===// +defvar TopDown = [{ MISched::TopDown }]; +defvar BottomUp = [{ MISched::BottomUp }]; +defvar Bidirectional = [{ MISched::Bidirectional }]; + def FeatureFP64 : SubtargetFeature<"fp64", "FP64", "true", @@ -54,3 +58,20 @@ def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca", "Enable promote alloca pass" >; +def FeaturePostRATopDown : SubtargetFeature <"postra-top-down", + "PostRASchedDirection", + TopDown, + "Force Post-RA scheduler to run top-down" +>; + +def FeaturePostRABottomUp : SubtargetFeature <"postra-bottom-up", + "PostRASchedDirection", + BottomUp, + "Force Post-RA scheduler to run bottom-up" +>; + +def FeaturePostRABidirectional : SubtargetFeature <"postra-bidirectional", + "PostRASchedDirection", + Bidirectional, + "Force Post-RA scheduler to run bidirectionally" +>; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h index 6878744496cfe..fc1f158e9b475 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -15,6 +15,7 @@ #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H #include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/IR/CallingConv.h" #include "llvm/Support/Alignment.h" #include "llvm/TargetParser/Triple.h" @@ -80,6 +81,7 @@ class AMDGPUSubtarget { unsigned LocalMemorySize = 0; unsigned AddressableLocalMemorySize = 0; char WavefrontSizeLog2 = 0; + MISched::Direction PostRASchedDirection = MISched::TopDown; public: AMDGPUSubtarget(Triple TT); @@ -382,6 +384,10 @@ class AMDGPUSubtarget { AMDGPUDwarfFlavour getAMDGPUDwarfFlavour() const; virtual ~AMDGPUSubtarget() = default; + + MISched::Direction getPostRASchedDirection() const { + return PostRASchedDirection; + } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 01a846c12778a..c1f17033d04a8 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -460,11 +460,6 @@ static cl::opt cl::desc("Select custom AMDGPU scheduling strategy."), cl::Hidden, cl::init("")); -static cl::opt - AMDGPUPostRADirection("amdgpu-post-ra-direction", - cl::desc("Select custom AMDGPU postRA direction."), - cl::Hidden, cl::init("")); - static cl::opt EnableRewritePartialRegUses( "amdgpu-enable-rewrite-partial-reg-uses", cl::desc("Enable rewrite partial reg uses pass"), cl::init(true), @@ -1158,29 +1153,6 @@ GCNTargetMachine::createMachineScheduler(MachineSchedContext *C) const { ScheduleDAGInstrs * GCNTargetMachine::createPostMachineScheduler(MachineSchedContext *C) const { - if (PostRADirection.getNumOccurrences() == 0) { - Attribute PostRADirectionAttr = - C->MF->getFunction().getFnAttribute("amdgpu-post-ra-direction"); - - if (PostRADirectionAttr.isValid()) { - StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString(); - if (PostRADirectionStr == "topdown") - PostRADirection = MISched::TopDown; - else if (PostRADirectionStr == "bottomup") - PostRADirection = MISched::BottomUp; - else if (PostRADirectionStr == "bidirectional") - PostRADirection = MISched::Bidirectional; - else { - PostRADirection = MISched::Unspecified; - DiagnosticInfoOptimizationFailure Diag( - C->MF->getFunction(), C->MF->getFunction().getSubprogram(), - Twine("invalid value for postRa direction attribute: '") + - PostRADirectionStr); - C->MF->getFunction().getContext().diagnose(Diag); - } - } - } - ScheduleDAGMI *DAG = new GCNPostScheduleDAGMILive(C, std::make_unique(C), /*RemoveKillFlags=*/true); diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp index 0a0a107d57e55..0bfd042bfca39 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp @@ -340,6 +340,40 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, Policy.ShouldTrackLaneMasks = true; } +void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy, + unsigned NumRegionInstrs) const { + switch (getPostRASchedDirection()) { + case MISched::TopDown: + Policy.OnlyTopDown = true; + Policy.OnlyBottomUp = false; + break; + case MISched::BottomUp: + Policy.OnlyTopDown = false; + Policy.OnlyBottomUp = true; + break; + case MISched::Bidirectional: + default: + Policy.OnlyTopDown = false; + Policy.OnlyBottomUp = false; + break; + } + + LLVM_DEBUG({ + const char *DirStr = "topdown"; + switch (getPostRASchedDirection()) { + case MISched::BottomUp: + DirStr = "bottomup"; + break; + case MISched::Bidirectional: + DirStr = "bidirectional"; + break; + default: + break; + } + dbgs() << "Post-MI-sched direction: " << DirStr << '\n'; + }); +} + void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const { if (isWave32()) { // Fix implicit $vcc operands after MIParser has verified that they match diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index bdd900d748531..476c1814eb6f5 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -1041,6 +1041,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo, void overrideSchedPolicy(MachineSchedPolicy &Policy, const SchedRegion &Region) const override; + void overridePostRASchedPolicy(MachineSchedPolicy &Policy, + unsigned NumRegionInstrs) const override; + void mirFileLoaded(MachineFunction &MF) const override; unsigned getMaxNumUserSGPRs() const { diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll deleted file mode 100644 index c6f63f3b4a1b3..0000000000000 --- a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll +++ /dev/null @@ -1,38 +0,0 @@ -; REQUIRES: asserts - -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=machine-scheduler < %s 2>&1 | FileCheck %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefixes=WARNING %s - -; CHECK-LABEL: {{^}}postra-sched-topdown: -; CHECK: Post-MI-sched direction (postra-sched-topdown): topdown -define float @postra-sched-topdown(float %input) nounwind #0 { - %x = fadd float %input, 1.000000e+00 - ret float %x -} - -; CHECK-LABEL: {{^}}postra-sched-bottomup: -; CHECK: Post-MI-sched direction (postra-sched-bottomup): bottomup -define float @postra-sched-bottomup(float %input) nounwind #1 { - %x = fsub float %input, 1.000000e+00 - ret float %x -} - -; CHECK-LABEL: {{^}}postra-sched-bidirectional: -; CHECK: Post-MI-sched direction (postra-sched-bidirectional): bidirectional -define float @postra-sched-bidirectional(float %input) nounwind #2 { - %x = fadd float %input, 1.000000e+00 - ret float %x -} - -; CHECK-LABEL: {{^}}postra-sched-warning: -; CHECK: Post-MI-sched direction (postra-sched-warning): default -; WARNING: invalid value for postRa direction attribute -define float @postra-sched-warning(float %input) nounwind #3 { - %x = fsub float %input, 1.000000e+00 - ret float %x -} - -attributes #0 = {"amdgpu-post-ra-direction"="topdown"} -attributes #1 = {"amdgpu-post-ra-direction"="bottomup"} -attributes #2 = {"amdgpu-post-ra-direction"="bidirectional"} -attributes #3 = {"amdgpu-post-ra-direction"="warning"} diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll new file mode 100644 index 0000000000000..339fbe4159db4 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll @@ -0,0 +1,25 @@ +; REQUIRES: asserts + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=gcn-subtarget < %s 2>&1 | FileCheck %s + +; CHECK: Post-MI-sched direction: topdown +define float @postra-sched-topdown(float %input) nounwind #0 { + %x = fadd float %input, 1.000000e+00 + ret float %x +} + +; CHECK: Post-MI-sched direction: bottomup +define float @postra-sched-bottomup(float %input) nounwind #1 { + %x = fsub float %input, 1.000000e+00 + ret float %x +} + +; CHECK: Post-MI-sched direction: bidirectional +define float @postra-sched-bidirectional(float %input) nounwind #2 { + %x = fadd float %input, 1.000000e+00 + ret float %x +} + +attributes #0 = { "target-features"="+postra-top-down" } +attributes #1 = { "target-features"="+postra-bottom-up" } +attributes #2 = { "target-features"="+postra-bidirectional" } From 967bce6791f884556779cb410f462be96afb25c5 Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Thu, 17 Jul 2025 17:44:17 +0800 Subject: [PATCH 06/10] [AMDGPU] --- .../llvm/CodeGen/TargetSubtargetInfo.h | 1 + llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 79 +++++++++++++------ llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 +- 3 files changed, 58 insertions(+), 25 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h index a8c7a8aff83cf..3be7c6a45298c 100644 --- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h +++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h @@ -16,6 +16,7 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" +#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MacroFusion.h" #include "llvm/CodeGen/PBQPRAConstraint.h" #include "llvm/CodeGen/SchedulerRegistry.h" diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp index 0bfd042bfca39..22ec4438e9e0e 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp @@ -52,6 +52,11 @@ static cl::opt cl::desc("Number of addresses from which to enable MIMG NSA."), cl::init(2), cl::Hidden); +static cl::opt + AMDGPUPostRADirection("amdgpu-post-ra-direction", + cl::desc("Select custom AMDGPU postRA direction."), + cl::Hidden, cl::init("")); + GCNSubtarget::~GCNSubtarget() = default; GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT, @@ -341,37 +346,63 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, } void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy, - unsigned NumRegionInstrs) const { - switch (getPostRASchedDirection()) { - case MISched::TopDown: + const MachineBasicBlock &MBB, + unsigned NumRegionInstr) const { + const Function &F = MBB.getParent()->getFunction(); + Attribute PostRADirectionAttr = F.getFnAttribute("amdgpu-post-ra-direction"); + if (!PostRADirectionAttr.isValid()) + return; + + StringRef PostRADirectionStr = PostRADirectionAttr.getValueAsString(); + if (PostRADirectionStr == "topdown") { Policy.OnlyTopDown = true; Policy.OnlyBottomUp = false; - break; - case MISched::BottomUp: + } else if (PostRADirectionStr == "bottomup") { Policy.OnlyTopDown = false; Policy.OnlyBottomUp = true; - break; - case MISched::Bidirectional: - default: + } else if (PostRADirectionStr == "bidirectional") { Policy.OnlyTopDown = false; Policy.OnlyBottomUp = false; - break; + } else { + DiagnosticInfoOptimizationFailure Diag( + F, F.getSubprogram(), + Twine("invalid value for postRa direction attribute: '") + + PostRADirectionStr); + F.getContext().diagnose(Diag); } - - LLVM_DEBUG({ - const char *DirStr = "topdown"; - switch (getPostRASchedDirection()) { - case MISched::BottomUp: - DirStr = "bottomup"; - break; - case MISched::Bidirectional: - DirStr = "bidirectional"; - break; - default: - break; - } - dbgs() << "Post-MI-sched direction: " << DirStr << '\n'; - }); + // } + + // switch (getPostRASchedDirection()) { + // case MISched::TopDown: + // Policy.OnlyTopDown = true; + // Policy.OnlyBottomUp = false; + // break; + // case MISched::BottomUp: + // Policy.OnlyTopDown = false; + // Policy.OnlyBottomUp = true; + // break; + // case MISched::Bidirectional: + // Policy.OnlyTopDown = false; + // Policy.OnlyBottomUp = false; + // break; + // default: + // break; + // } + + // LLVM_DEBUG({ + // const char *DirStr = "topdown"; + // switch (getPostRASchedDirection()) { + // case MISched::BottomUp: + // DirStr = "bottomup"; + // break; + // case MISched::Bidirectional: + // DirStr = "bidirectional"; + // break; + // default: + // break; + // } + // dbgs() << "Post-MI-sched direction: " << DirStr << '\n'; + // }); } void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const { diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index 476c1814eb6f5..b7a81944a549e 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -1042,7 +1042,8 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo, const SchedRegion &Region) const override; void overridePostRASchedPolicy(MachineSchedPolicy &Policy, - unsigned NumRegionInstrs) const override; + const MachineBasicBlock &MBB, + unsigned NumRegionInstr) const override; void mirFileLoaded(MachineFunction &MF) const override; From 4c37d702b00be91e0f907c011e6daeee37839411 Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Tue, 22 Jul 2025 17:12:29 +0800 Subject: [PATCH 07/10] [AMDGPU] Use function attribute for post-ra --- .../llvm/CodeGen/TargetSubtargetInfo.h | 1 - llvm/lib/Target/AMDGPU/AMDGPUFeatures.td | 22 -------- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 6 --- llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 51 ++++++------------- llvm/lib/Target/AMDGPU/GCNSubtarget.h | 3 +- .../CodeGen/AMDGPU/postra-sched-attribute.ll | 34 +++++++++++++ .../AMDGPU/postra-sched-target-features.ll | 25 --------- 7 files changed, 50 insertions(+), 92 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll delete mode 100644 llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll diff --git a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h index 3be7c6a45298c..a8c7a8aff83cf 100644 --- a/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h +++ b/llvm/include/llvm/CodeGen/TargetSubtargetInfo.h @@ -16,7 +16,6 @@ #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringRef.h" -#include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MacroFusion.h" #include "llvm/CodeGen/PBQPRAConstraint.h" #include "llvm/CodeGen/SchedulerRegistry.h" diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td index 870144f43b993..bdc6073889bf3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td @@ -6,10 +6,6 @@ // //===----------------------------------------------------------------------===// -defvar TopDown = [{ MISched::TopDown }]; -defvar BottomUp = [{ MISched::BottomUp }]; -defvar Bidirectional = [{ MISched::Bidirectional }]; - def FeatureFP64 : SubtargetFeature<"fp64", "FP64", "true", @@ -57,21 +53,3 @@ def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca", "true", "Enable promote alloca pass" >; - -def FeaturePostRATopDown : SubtargetFeature <"postra-top-down", - "PostRASchedDirection", - TopDown, - "Force Post-RA scheduler to run top-down" ->; - -def FeaturePostRABottomUp : SubtargetFeature <"postra-bottom-up", - "PostRASchedDirection", - BottomUp, - "Force Post-RA scheduler to run bottom-up" ->; - -def FeaturePostRABidirectional : SubtargetFeature <"postra-bidirectional", - "PostRASchedDirection", - Bidirectional, - "Force Post-RA scheduler to run bidirectionally" ->; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h index fc1f158e9b475..6878744496cfe 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -15,7 +15,6 @@ #define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H #include "llvm/ADT/SmallVector.h" -#include "llvm/CodeGen/MachineScheduler.h" #include "llvm/IR/CallingConv.h" #include "llvm/Support/Alignment.h" #include "llvm/TargetParser/Triple.h" @@ -81,7 +80,6 @@ class AMDGPUSubtarget { unsigned LocalMemorySize = 0; unsigned AddressableLocalMemorySize = 0; char WavefrontSizeLog2 = 0; - MISched::Direction PostRASchedDirection = MISched::TopDown; public: AMDGPUSubtarget(Triple TT); @@ -384,10 +382,6 @@ class AMDGPUSubtarget { AMDGPUDwarfFlavour getAMDGPUDwarfFlavour() const; virtual ~AMDGPUSubtarget() = default; - - MISched::Direction getPostRASchedDirection() const { - return PostRASchedDirection; - } }; } // end namespace llvm diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp index 22ec4438e9e0e..46064f0a56d4f 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp @@ -346,9 +346,8 @@ void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy, } void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy, - const MachineBasicBlock &MBB, - unsigned NumRegionInstr) const { - const Function &F = MBB.getParent()->getFunction(); + const SchedRegion &Region) const { + const Function &F = Region.RegionBegin->getMF()->getFunction(); Attribute PostRADirectionAttr = F.getFnAttribute("amdgpu-post-ra-direction"); if (!PostRADirectionAttr.isValid()) return; @@ -370,39 +369,19 @@ void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy, PostRADirectionStr); F.getContext().diagnose(Diag); } - // } - - // switch (getPostRASchedDirection()) { - // case MISched::TopDown: - // Policy.OnlyTopDown = true; - // Policy.OnlyBottomUp = false; - // break; - // case MISched::BottomUp: - // Policy.OnlyTopDown = false; - // Policy.OnlyBottomUp = true; - // break; - // case MISched::Bidirectional: - // Policy.OnlyTopDown = false; - // Policy.OnlyBottomUp = false; - // break; - // default: - // break; - // } - - // LLVM_DEBUG({ - // const char *DirStr = "topdown"; - // switch (getPostRASchedDirection()) { - // case MISched::BottomUp: - // DirStr = "bottomup"; - // break; - // case MISched::Bidirectional: - // DirStr = "bidirectional"; - // break; - // default: - // break; - // } - // dbgs() << "Post-MI-sched direction: " << DirStr << '\n'; - // }); + + LLVM_DEBUG({ + const char *DirStr = "default"; + if (Policy.OnlyTopDown && !Policy.OnlyBottomUp) + DirStr = "topdown"; + else if (!Policy.OnlyTopDown && Policy.OnlyBottomUp) + DirStr = "bottomup"; + else if (!Policy.OnlyTopDown && !Policy.OnlyBottomUp) + DirStr = "bidirectional"; + + dbgs() << "Post-MI-sched direction (" << F.getName() << "): " << DirStr + << '\n'; + }); } void GCNSubtarget::mirFileLoaded(MachineFunction &MF) const { diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index b7a81944a549e..6fe3abc98b5d5 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -1042,8 +1042,7 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo, const SchedRegion &Region) const override; void overridePostRASchedPolicy(MachineSchedPolicy &Policy, - const MachineBasicBlock &MBB, - unsigned NumRegionInstr) const override; + const SchedRegion &Region) const override; void mirFileLoaded(MachineFunction &MF) const override; diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll new file mode 100644 index 0000000000000..4d517fc640945 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll @@ -0,0 +1,34 @@ +; REQUIRES: asserts + +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=gcn-subtarget < %s 2>&1 | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s 2>&1 | FileCheck -check-prefixes=WARNING %s + +; CHECK: Post-MI-sched direction (postra-sched-topdown): topdown +define float @postra-sched-topdown(float %input) nounwind #0 { + %x = fadd float %input, 1.000000e+00 + ret float %x +} + +; CHECK: Post-MI-sched direction (postra-sched-bottomup): bottomup +define float @postra-sched-bottomup(float %input) nounwind #1 { + %x = fsub float %input, 1.000000e+00 + ret float %x +} + +; CHECK: Post-MI-sched direction (postra-sched-bidirectional): bidirectional +define float @postra-sched-bidirectional(float %input) nounwind #2 { + %x = fadd float %input, 1.000000e+00 + ret float %x +} + +; CHECK: Post-MI-sched direction (postra-sched-warning): topdown +; WARNING: invalid value for postRa direction attribute +define float @postra-sched-warning(float %input) nounwind #3 { + %x = fsub float %input, 1.000000e+00 + ret float %x +} + +attributes #0 = {"amdgpu-post-ra-direction"="topdown"} +attributes #1 = {"amdgpu-post-ra-direction"="bottomup"} +attributes #2 = {"amdgpu-post-ra-direction"="bidirectional"} +attributes #3 = {"amdgpu-post-ra-direction"="warning"} diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll deleted file mode 100644 index 339fbe4159db4..0000000000000 --- a/llvm/test/CodeGen/AMDGPU/postra-sched-target-features.ll +++ /dev/null @@ -1,25 +0,0 @@ -; REQUIRES: asserts - -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -debug-only=gcn-subtarget < %s 2>&1 | FileCheck %s - -; CHECK: Post-MI-sched direction: topdown -define float @postra-sched-topdown(float %input) nounwind #0 { - %x = fadd float %input, 1.000000e+00 - ret float %x -} - -; CHECK: Post-MI-sched direction: bottomup -define float @postra-sched-bottomup(float %input) nounwind #1 { - %x = fsub float %input, 1.000000e+00 - ret float %x -} - -; CHECK: Post-MI-sched direction: bidirectional -define float @postra-sched-bidirectional(float %input) nounwind #2 { - %x = fadd float %input, 1.000000e+00 - ret float %x -} - -attributes #0 = { "target-features"="+postra-top-down" } -attributes #1 = { "target-features"="+postra-bottom-up" } -attributes #2 = { "target-features"="+postra-bidirectional" } From d3a2b63892e706e64da7a636b5157d6374d9f840 Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Tue, 22 Jul 2025 17:14:38 +0800 Subject: [PATCH 08/10] [AMDGPU] Update --- llvm/lib/Target/AMDGPU/AMDGPUFeatures.td | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td index bdc6073889bf3..74d1faeb6f545 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUFeatures.td @@ -53,3 +53,4 @@ def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca", "true", "Enable promote alloca pass" >; + From 90bcf6bb0c25393e9a878a248f4680515f4f8442 Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Thu, 31 Jul 2025 11:28:47 +0800 Subject: [PATCH 09/10] [AMDGPU] Remove option. --- llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 5 ----- 1 file changed, 5 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp index 46064f0a56d4f..4c4eb9a02f0a1 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp @@ -52,11 +52,6 @@ static cl::opt cl::desc("Number of addresses from which to enable MIMG NSA."), cl::init(2), cl::Hidden); -static cl::opt - AMDGPUPostRADirection("amdgpu-post-ra-direction", - cl::desc("Select custom AMDGPU postRA direction."), - cl::Hidden, cl::init("")); - GCNSubtarget::~GCNSubtarget() = default; GCNSubtarget &GCNSubtarget::initializeSubtargetDependencies(const Triple &TT, From 195ce35f84b2801ae1ae6ac4d531a17f6084dea1 Mon Sep 17 00:00:00 2001 From: Harrison Hao Date: Fri, 1 Aug 2025 10:05:48 +0800 Subject: [PATCH 10/10] [AMDGPU] Update for comments. --- llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 4 +--- llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp index 4c4eb9a02f0a1..0237a60673a95 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp @@ -359,9 +359,7 @@ void GCNSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy, Policy.OnlyBottomUp = false; } else { DiagnosticInfoOptimizationFailure Diag( - F, F.getSubprogram(), - Twine("invalid value for postRa direction attribute: '") + - PostRADirectionStr); + F, F.getSubprogram(), "invalid value for postRA direction attribute"); F.getContext().diagnose(Diag); } diff --git a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll index 4d517fc640945..c4a48a469f259 100644 --- a/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll +++ b/llvm/test/CodeGen/AMDGPU/postra-sched-attribute.ll @@ -22,7 +22,7 @@ define float @postra-sched-bidirectional(float %input) nounwind #2 { } ; CHECK: Post-MI-sched direction (postra-sched-warning): topdown -; WARNING: invalid value for postRa direction attribute +; WARNING: invalid value for postRA direction attribute define float @postra-sched-warning(float %input) nounwind #3 { %x = fsub float %input, 1.000000e+00 ret float %x