From 18bc03b7249aea8933e7c6a3ade42490a4cca291 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 11 Jul 2025 14:30:51 -0700 Subject: [PATCH] [RISCV] Remove unneeded AddedComplexity from Xqcibi patterns. NFCI We don't have any tests that show why this AddedComplexity is needed. ImmLeafs are automatically ranked higher than register operands so there is no ambgiuity with the base ISA here. If there's some reason I'm missing, please explain and I'll add a comment. --- llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index 9e3eb1c03fb37..286d44a9c1f72 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -1417,7 +1417,7 @@ def : PatGprNoX0GprNoX0; /// Branches -let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2 in { +let Predicates = [HasVendorXqcibi, IsRV32] in { def : BcciPat; def : BcciPat; def : BcciPat; @@ -1445,7 +1445,7 @@ def : SelectQCbi def : SelectQCbi; def : SelectQCbi; def : SelectQCbi; -} // let Predicates = [HasVendorXqcibi, IsRV32], AddedComplexity = 2 +} // let Predicates = [HasVendorXqcibi, IsRV32] let Predicates = [HasVendorXqcibm, IsRV32] in { def : Pat<(sext_inreg (i32 GPR:$rs1), i1), (QC_EXT GPR:$rs1, 1, 0)>;