From f6b643e18797ca818420a1c5b253eecfcb74af7e Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 14 Jul 2025 16:22:35 -0700 Subject: [PATCH 1/2] [RISCV] Render P-ext simm10_unsigned as a simm10 after parsing. Instead of allowing a parsed MCInst to have a either uimm10 or simm10, always render as simm10. This avoids a mismatch between parsed MCInst and disassembled MCInst when a uimm10 value is used. --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 8 ++++++++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 1 - llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 10 +++++++--- llvm/test/MC/RISCV/rv32p-valid.s | 5 ++--- llvm/test/MC/RISCV/rv64p-valid.s | 8 +++----- 5 files changed, 20 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 66f4aade380fa..b6bb5549985b2 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1199,6 +1199,14 @@ struct RISCVOperand final : public MCParsedAsmOperand { addExpr(Inst, getImm(), isRV64Imm()); } + void addSImm10UnsignedOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + int64_t Imm; + [[maybe_unused]] bool IsConstant = evaluateConstantImm(getImm(), Imm); + assert(IsConstant); + Inst.addOperand(MCOperand::createImm(SignExtend64<10>(Imm))); + } + void addFPImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); if (isImm()) { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index f41ad419db1a7..4c8dcf376755b 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -339,7 +339,6 @@ enum OperandType : unsigned { OPERAND_SIMM6, OPERAND_SIMM6_NONZERO, OPERAND_SIMM10, - OPERAND_SIMM10_UNSIGNED, OPERAND_SIMM10_LSB0000_NONZERO, OPERAND_SIMM11, OPERAND_SIMM12, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index aa9e7b5635def..830cd27632102 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -20,18 +20,22 @@ def simm10 : RISCVSImmLeafOp<10>; +def SImm10UnsignedAsmOperand : SImmAsmOperand<10, "Unsigned"> { + let RenderMethod = "addSImm10UnsignedOperands"; +} + // A 10-bit signed immediate allowing range [-512, 1023] // but will decode to [-512, 511]. def simm10_unsigned : RISCVOp { - let ParserMatchClass = SImmAsmOperand<10, "Unsigned">; + let ParserMatchClass = SImm10UnsignedAsmOperand; let EncoderMethod = "getImmOpValue"; let DecoderMethod = "decodeSImmOperand<10>"; - let OperandType = "OPERAND_SIMM10_UNSIGNED"; + let OperandType = "OPERAND_SIMM10"; let MCOperandPredicate = [{ int64_t Imm; if (!MCOp.evaluateAsConstantImm(Imm)) return false; - return isInt<10>(Imm) || isUInt<10>(Imm); + return isInt<10>(Imm); }]; } diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s index c755acddc712e..c259c142f92b2 100644 --- a/llvm/test/MC/RISCV/rv32p-valid.s +++ b/llvm/test/MC/RISCV/rv32p-valid.s @@ -2,7 +2,7 @@ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-p < %s \ # RUN: | llvm-objdump --mattr=+experimental-p -M no-aliases -d -r --no-print-imm-hex - \ -# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ,CHECK-OBJ %s +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: clz a0, a1 # CHECK-ASM: encoding: [0x13,0x95,0x05,0x60] @@ -73,7 +73,6 @@ psabs.b t0, t1 # CHECK-ASM-AND-OBJ: plui.h gp, 32 # CHECK-ASM: encoding: [0x9b,0x21,0x20,0xf0] plui.h gp, 32 -# CHECK-OBJ: plui.h gp, -412 -# CHECK-ASM: plui.h gp, 612 +# CHECK-ASM-AND-OBJ: plui.h gp, -412 # CHECK-ASM: encoding: [0x9b,0xa1,0x64,0xf0] plui.h gp, 612 diff --git a/llvm/test/MC/RISCV/rv64p-valid.s b/llvm/test/MC/RISCV/rv64p-valid.s index 6c48ad3469b47..3ea6b00bbe11c 100644 --- a/llvm/test/MC/RISCV/rv64p-valid.s +++ b/llvm/test/MC/RISCV/rv64p-valid.s @@ -2,7 +2,7 @@ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s # RUN: llvm-mc -filetype=obj --triple=riscv64 -mattr=+experimental-p < %s \ # RUN: | llvm-objdump --triple=riscv64 --mattr=+experimental-p -M no-aliases --no-print-imm-hex -d -r - \ -# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ,CHECK-OBJ %s +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: clz a0, a1 # CHECK-ASM: encoding: [0x13,0x95,0x05,0x60] @@ -97,14 +97,12 @@ psabs.b a0, s2 # CHECK-ASM-AND-OBJ: plui.h s2, 4 # CHECK-ASM: encoding: [0x1b,0x29,0x04,0xf0] plui.h s2, 4 -# CHECK-OBJ: plui.h gp, -412 -# CHECK-ASM: plui.h gp, 612 +# CHECK-ASM-AND-OBJ: plui.h gp, -412 # CHECK-ASM: encoding: [0x9b,0xa1,0x64,0xf0] plui.h gp, 612 # CHECK-ASM-AND-OBJ: plui.w a2, 1 # CHECK-ASM: encoding: [0x1b,0x26,0x01,0xf2] plui.w a2, 1 -# CHECK-OBJ: plui.w a2, -1 -# CHECK-ASM: plui.w a2, 1023 +# CHECK-ASM-AND-OBJ: plui.w a2, -1 # CHECK-ASM: encoding: [0x1b,0xa6,0xff,0xf3] plui.w a2, 1023 From df20d291212542fd852690f0d18c07d9f131b206 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 14 Jul 2025 17:20:05 -0700 Subject: [PATCH 2/2] fixup! Address review comment --- llvm/lib/Target/RISCV/RISCVInstrInfoP.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index 830cd27632102..aef410fb4cc6e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -25,7 +25,7 @@ def SImm10UnsignedAsmOperand : SImmAsmOperand<10, "Unsigned"> { } // A 10-bit signed immediate allowing range [-512, 1023] -// but will decode to [-512, 511]. +// but represented as [-512, 511]. def simm10_unsigned : RISCVOp { let ParserMatchClass = SImm10UnsignedAsmOperand; let EncoderMethod = "getImmOpValue";