From d9473a16b9bb23bef8d1646f2b453c1e3a959c88 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 21 Jul 2025 17:22:52 +0800 Subject: [PATCH 1/4] [RISCV] Copy base instruction TSFlags in RVV pseudo TSFlags. NFC As pointed out in https://github.com/llvm/llvm-project/pull/149704/files#r2218484702, we currently define TSFlags for vector instruction behaviour on the underlying base instruction. But we normally operate on pseudos, so whenever we want to check the TSFlags it requires a pseudo table lookup to get the base instruction. This PR copies over these TSFlags to the pseudos' TSFlags so we can avoid the table lookup. To do this I needed to merge Pseudo and RISCVVPseudo so the latter extends the former. --- .../Target/RISCV/RISCVInstrInfoVPseudos.td | 249 +++++++----------- llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 6 +- llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 10 +- llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 30 +-- llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td | 10 +- llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 6 +- llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 15 +- 7 files changed, 127 insertions(+), 199 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index de9e55beb6a5e..7d3e799bb205f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -543,12 +543,17 @@ defset list AllWidenableBFloatToFloatVectors = { // This represents the information we need in codegen for each pseudo. // The definition should be consistent with `struct PseudoInfo` in // RISCVInstrInfo.h. -class RISCVVPseudo { +class RISCVVPseudo pattern, string opcodestr = "", string argstr = ""> + : Pseudo { Pseudo Pseudo = !cast(NAME); // Used as a key. Instruction BaseInstr = !cast(PseudoToVInst.VInst); // SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown). bits<8> SEW = 0; bit IncludeInInversePseudoTable = 1; + + // Set common TSFlags in RVInst from the base instruction. + let ElementsDependOn = !cast(BaseInstr).ElementsDependOn; + let DestEEW = !cast(BaseInstr).DestEEW; } // The actual table. @@ -785,10 +790,9 @@ class GetVTypeMinimalPredicates { class VPseudoUSLoadNoMask : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -801,11 +805,10 @@ class VPseudoUSLoadNoMask : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -820,10 +823,9 @@ class VPseudoUSLoadMask : - Pseudo<(outs RetClass:$rd, GPR:$vl), + RISCVVPseudo<(outs RetClass:$rd, GPR:$vl), (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -836,11 +838,10 @@ class VPseudoUSLoadFFNoMask : - Pseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -855,10 +856,9 @@ class VPseudoUSLoadFFMask : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -871,11 +871,10 @@ class VPseudoSLoadNoMask : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -895,10 +894,9 @@ class VPseudoILoadNoMask TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLX { let mayLoad = 1; let mayStore = 0; @@ -917,11 +915,10 @@ class VPseudoILoadMask TargetConstraintType = 1> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, IdxClass:$rs2, VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLX { let mayLoad = 1; let mayStore = 0; @@ -938,9 +935,8 @@ class VPseudoILoadMask : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew), []>, - RISCVVPseudo, RISCVVSE { let mayLoad = 0; let mayStore = 1; @@ -951,10 +947,9 @@ class VPseudoUSStoreNoMask : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins StClass:$rd, GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>, - RISCVVPseudo, RISCVVSE { let mayLoad = 0; let mayStore = 1; @@ -966,10 +961,9 @@ class VPseudoUSStoreMask : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, AVL:$vl, sew:$sew), []>, - RISCVVPseudo, RISCVVSE { let mayLoad = 0; let mayStore = 1; @@ -980,10 +974,9 @@ class VPseudoSStoreNoMask : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, sew:$sew), []>, - RISCVVPseudo, RISCVVSE { let mayLoad = 0; let mayStore = 1; @@ -994,10 +987,9 @@ class VPseudoSStoreMask : - Pseudo<(outs RegClass:$rd), + RISCVVPseudo<(outs RegClass:$rd), (ins RegClass:$passthru, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1008,10 +1000,9 @@ class VPseudoNullaryNoMask : } class VPseudoNullaryMask : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1026,8 +1017,7 @@ class VPseudoNullaryMask : // Nullary for pseudo instructions. They are expanded in // RISCVExpandPseudoInsts pass. class VPseudoNullaryPseudoM : - Pseudo<(outs VR:$rd), (ins AVL:$vl, sew_mask:$sew), []>, - RISCVVPseudo { + RISCVVPseudo<(outs VR:$rd), (ins AVL:$vl, sew_mask:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1041,10 +1031,9 @@ class VPseudoUnaryNoMask TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$passthru, OpClass:$rs2, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1059,9 +1048,8 @@ class VPseudoUnaryNoMaskNoPolicy TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), - (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []>, - RISCVVPseudo { + RISCVVPseudo<(outs RetClass:$rd), + (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1075,10 +1063,9 @@ class VPseudoUnaryNoMaskRoundingMode TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1097,10 +1084,9 @@ class VPseudoUnaryMask TargetConstraintType = 1, DAGOperand sewop = sew> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1117,11 +1103,10 @@ class VPseudoUnaryMaskRoundingMode TargetConstraintType = 1> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, VMaskOp:$vm, vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1155,9 +1140,8 @@ class VPseudoUnaryMask_NoExcept, - RISCVVPseudo { + RISCVVPseudo<(outs GPR:$rd), + (ins VR:$rs2, AVL:$vl, sew_mask:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1166,9 +1150,8 @@ class VPseudoUnaryNoMaskGPROut : } class VPseudoUnaryMaskGPROut : - Pseudo<(outs GPR:$rd), - (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []>, - RISCVVPseudo { + RISCVVPseudo<(outs GPR:$rd), + (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1180,10 +1163,9 @@ class VPseudoUnaryMaskGPROut : // Mask can be V0~V31 class VPseudoUnaryAnyMask : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, - VR:$vm, AVL:$vl, sew:$sew), []>, - RISCVVPseudo { + VR:$vm, AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1198,9 +1180,8 @@ class VPseudoBinaryNoMask TargetConstraintType = 1, DAGOperand sewop = sew> : - Pseudo<(outs RetClass:$rd), - (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []>, - RISCVVPseudo { + RISCVVPseudo<(outs RetClass:$rd), + (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1215,10 +1196,9 @@ class VPseudoBinaryNoMaskPolicy TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, - sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1235,10 +1215,9 @@ class VPseudoBinaryNoMaskRoundingMode TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1258,12 +1237,11 @@ class VPseudoBinaryMaskPolicyRoundingMode TargetConstraintType = 1> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, VMaskOp:$vm, vec_rm:$rm, AVL:$vl, - sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1286,10 +1264,9 @@ class VPseudoTiedBinaryNoMask TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew, - vec_policy:$policy), []>, - RISCVVPseudo { + vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1307,12 +1284,11 @@ class VPseudoTiedBinaryNoMaskRoundingMode TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$rs2, Op2Class:$rs1, vec_rm:$rm, AVL:$vl, sew:$sew, - vec_policy:$policy), []>, - RISCVVPseudo { + vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1331,10 +1307,9 @@ class VPseudoTiedBinaryNoMaskRoundingMode LMUL, bit Ordered>: - Pseudo<(outs), + RISCVVPseudo<(outs), (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl, sew:$sew),[]>, - RISCVVPseudo, RISCVVSX { let mayLoad = 0; let mayStore = 1; @@ -1345,10 +1320,9 @@ class VPseudoIStoreNoMask LMUL, class VPseudoIStoreMask LMUL, bit Ordered>: - Pseudo<(outs), + RISCVVPseudo<(outs), (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, VMaskOp:$vm, AVL:$vl, sew:$sew),[]>, - RISCVVPseudo, RISCVVSX { let mayLoad = 0; let mayStore = 1; @@ -1363,11 +1337,10 @@ class VPseudoBinaryMaskPolicy TargetConstraintType = 1> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1383,11 +1356,10 @@ class VPseudoBinaryMaskPolicy : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1401,13 +1373,12 @@ class VPseudoTernaryMaskPolicy : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op1Class:$rs2, Op2Class:$rs1, VMaskOp:$vm, vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1427,11 +1398,10 @@ class VPseudoBinaryMOutMask TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1451,11 +1421,10 @@ class VPseudoTiedBinaryMask TargetConstraintType = 1> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1473,13 +1442,12 @@ class VPseudoTiedBinaryMaskRoundingMode TargetConstraintType = 1> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, Op2Class:$rs1, VMaskOp:$vm, vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1503,13 +1471,12 @@ class VPseudoBinaryCarry TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), !if(CarryIn, (ins Op1Class:$rs2, Op2Class:$rs1, VMV0:$carry, AVL:$vl, sew:$sew), (ins Op1Class:$rs2, Op2Class:$rs1, - AVL:$vl, sew:$sew)), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew)), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1525,10 +1492,9 @@ class VPseudoTiedBinaryCarryIn TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMV0:$carry, AVL:$vl, sew:$sew), []>, - RISCVVPseudo { + VMV0:$carry, AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1544,10 +1510,9 @@ class VPseudoTernaryNoMask : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - AVL:$vl, sew:$sew), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1561,10 +1526,9 @@ class VPseudoTernaryNoMaskWithPolicy TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1580,10 +1544,9 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode TargetConstraintType = 1> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1600,10 +1563,9 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode NF> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1617,10 +1579,9 @@ class VPseudoUSSegLoadNoMask NF> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1636,10 +1597,9 @@ class VPseudoUSSegLoadMask NF> : - Pseudo<(outs RetClass:$rd, GPR:$vl), + RISCVVPseudo<(outs RetClass:$rd, GPR:$vl), (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1653,10 +1613,9 @@ class VPseudoUSSegLoadFFNoMask NF> : - Pseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1672,10 +1631,9 @@ class VPseudoUSSegLoadFFMask NF> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1689,11 +1647,10 @@ class VPseudoSSegLoadNoMask NF> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1712,10 +1669,9 @@ class VPseudoISegLoadNoMask LMUL, bits<4> NF, bit Ordered> : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, IdxClass:$offset, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLXSEG { let mayLoad = 1; let mayStore = 0; @@ -1734,11 +1690,10 @@ class VPseudoISegLoadMask LMUL, bits<4> NF, bit Ordered> : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVVLXSEG { let mayLoad = 1; let mayStore = 0; @@ -1756,9 +1711,8 @@ class VPseudoISegLoadMask NF> : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew), []>, - RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; let mayStore = 1; @@ -1770,10 +1724,9 @@ class VPseudoUSSegStoreNoMask NF> : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins ValClass:$rd, GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew), []>, - RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; let mayStore = 1; @@ -1786,10 +1739,9 @@ class VPseudoUSSegStoreMask NF> : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset, AVL:$vl, sew:$sew), []>, - RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; let mayStore = 1; @@ -1801,10 +1753,9 @@ class VPseudoSSegStoreNoMask NF> : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset, VMaskOp:$vm, AVL:$vl, sew:$sew), []>, - RISCVVPseudo, RISCVVSSEG { let mayLoad = 0; let mayStore = 1; @@ -1820,10 +1771,9 @@ class VPseudoISegStoreNoMask LMUL, bits<4> NF, bit Ordered> : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index, AVL:$vl, sew:$sew), []>, - RISCVVPseudo, RISCVVSXSEG { let mayLoad = 0; let mayStore = 1; @@ -1838,10 +1788,9 @@ class VPseudoISegStoreMask LMUL, bits<4> NF, bit Ordered> : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index, VMaskOp:$vm, AVL:$vl, sew:$sew), []>, - RISCVVPseudo, RISCVVSXSEG { let mayLoad = 0; let mayStore = 1; @@ -6745,16 +6694,14 @@ let Predicates = [HasVInstructions] in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { let HasSEWOp = 1, BaseInstr = VMV_X_S in def PseudoVMV_X_S: - Pseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew), []>, - Sched<[WriteVMovXS, ReadVMovXS]>, - RISCVVPseudo; + RISCVVPseudo<(outs GPR:$rd), (ins VR:$rs2, sew:$sew), []>, + Sched<[WriteVMovXS, ReadVMovXS]>; let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, isReMaterializable = 1, Constraints = "$rd = $passthru" in - def PseudoVMV_S_X: Pseudo<(outs VR:$rd), + def PseudoVMV_S_X: RISCVVPseudo<(outs VR:$rd), (ins VR:$passthru, GPR:$rs1, AVL:$vl, sew:$sew), []>, - Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>, - RISCVVPseudo; + Sched<[WriteVMovSX, ReadVMovSX_V, ReadVMovSX_X]>; } } // Predicates = [HasVInstructions] @@ -6767,18 +6714,16 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { foreach f = FPList in { let HasSEWOp = 1, BaseInstr = VFMV_F_S in def "PseudoVFMV_" # f.FX # "_S" : - Pseudo<(outs f.fprclass:$rd), + RISCVVPseudo<(outs f.fprclass:$rd), (ins VR:$rs2, sew:$sew), []>, - Sched<[WriteVMovFS, ReadVMovFS]>, - RISCVVPseudo; + Sched<[WriteVMovFS, ReadVMovFS]>; let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, isReMaterializable = 1, Constraints = "$rd = $passthru" in def "PseudoVFMV_S_" # f.FX : - Pseudo<(outs VR:$rd), + RISCVVPseudo<(outs VR:$rd), (ins VR:$passthru, f.fprclass:$rs1, AVL:$vl, sew:$sew), []>, - Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>, - RISCVVPseudo; + Sched<[WriteVMovSF, ReadVMovSF_V, ReadVMovSF_F]>; } } } // Predicates = [HasVInstructionsAnyF] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td index 5220815336441..786183421feed 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td @@ -448,11 +448,10 @@ class NDSRVInstVLN funct5, string opcodestr> } class VPseudoVLN8NoMask : - Pseudo<(outs RetClass:$rd), + RISCVVPseudo<(outs RetClass:$rd), (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVNDSVLN { let mayLoad = 1; let mayStore = 0; @@ -464,11 +463,10 @@ class VPseudoVLN8NoMask : } class VPseudoVLN8Mask : - Pseudo<(outs GetVRegNoV0.R:$rd), + RISCVVPseudo<(outs GetVRegNoV0.R:$rd), (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo, RISCVNDSVLN { let mayLoad = 1; let mayStore = 0; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td index 3912eb0d16c59..5395f3b3d52be 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td @@ -154,18 +154,16 @@ foreach m = MxList in { let VLMul = m.value in { let BaseInstr = RI_VEXTRACT in def PseudoRI_VEXTRACT_ # mx : - Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew), - []>, - RISCVVPseudo; + RISCVVPseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew), + []>; let HasVLOp = 1, BaseInstr = RI_VINSERT, HasVecPolicyOp = 1, Constraints = "$rd = $rs1" in def PseudoRI_VINSERT_ # mx : - Pseudo<(outs m.vrclass:$rd), + RISCVVPseudo<(outs m.vrclass:$rd), (ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), - []>, - RISCVVPseudo; + []>; } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 17fb75eb851c4..87e0b1b93bb0f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -243,10 +243,9 @@ let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvector", } class VPseudoVC_X : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1, - AVL:$vl, sew:$sew), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -255,10 +254,9 @@ class VPseudoVC_X : } class VPseudoVC_XV : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -268,10 +266,9 @@ class VPseudoVC_XV : class VPseudoVC_XVV : - Pseudo<(outs), + RISCVVPseudo<(outs), (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -280,10 +277,9 @@ class VPseudoVC_XVV : - Pseudo<(outs RDClass:$rd), + RISCVVPseudo<(outs RDClass:$rd), (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -293,10 +289,9 @@ class VPseudoVC_V_X : class VPseudoVC_V_XV : - Pseudo<(outs RDClass:$rd), + RISCVVPseudo<(outs RDClass:$rd), (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -306,10 +301,9 @@ class VPseudoVC_V_XV : - Pseudo<(outs RDClass:$rd), + RISCVVPseudo<(outs RDClass:$rd), (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index 4147c97a7a23a..a250ac8d3e260 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -230,9 +230,8 @@ class ZvkMxSet { } class VPseudoBinaryNoMask_Zvk : - Pseudo<(outs RetClass:$rd_wb), - (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + RISCVVPseudo<(outs RetClass:$rd_wb), + (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -246,10 +245,9 @@ class VPseudoBinaryNoMask_Zvk : class VPseudoTernaryNoMask_Zvk : - Pseudo<(outs RetClass:$rd_wb), + RISCVVPseudo<(outs RetClass:$rd_wb), (ins RetClass:$rd, Op1Class:$rs2, Op2Class:$rs1, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, - RISCVVPseudo { + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp index 15bd3466373a7..ee63e19350a9f 100644 --- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp @@ -33,7 +33,6 @@ namespace { class RISCVVLOptimizer : public MachineFunctionPass { const MachineRegisterInfo *MRI; const MachineDominatorTree *MDT; - const TargetInstrInfo *TII; public: static char ID; @@ -1292,8 +1291,7 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const { return false; } - assert(!RISCVII::elementsDependOnVL( - TII->get(RISCV::getRVVMCOpcode(MI.getOpcode())).TSFlags) && + assert(!RISCVII::elementsDependOnVL(MI.getDesc().TSFlags) && "Instruction shouldn't be supported if elements depend on VL"); assert(MI.getOperand(0).isReg() && @@ -1497,8 +1495,6 @@ bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) { if (!ST.hasVInstructions()) return false; - TII = ST.getInstrInfo(); - // For each instruction that defines a vector, compute what VL its // downstream users demand. for (MachineBasicBlock *MBB : post_order(&MF)) { diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp index 84ef53985484f..b249795dfe52d 100644 --- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp +++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp @@ -91,8 +91,7 @@ bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User, User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm(); unsigned SrcLog2SEW = Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm(); - unsigned SrcLog2EEW = RISCV::getDestLog2EEW( - TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())), SrcLog2SEW); + unsigned SrcLog2EEW = RISCV::getDestLog2EEW(Src.getDesc(), SrcLog2SEW); return SrcLog2EEW == UserLog2SEW; } @@ -170,8 +169,8 @@ bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const { if (!hasSameEEW(MI, *Src)) continue; - bool ElementsDependOnVL = RISCVII::elementsDependOnVL( - TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags); + bool ElementsDependOnVL = + RISCVII::elementsDependOnVL(Src->getDesc().TSFlags); if (ElementsDependOnVL || Src->mayRaiseFPException()) continue; @@ -760,11 +759,11 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const { else return false; - unsigned RVVTSFlags = - TII->get(RISCV::getRVVMCOpcode(True.getOpcode())).TSFlags; - if (RISCVII::elementsDependOnVL(RVVTSFlags) && !TrueVL.isIdenticalTo(MinVL)) + if (RISCVII::elementsDependOnVL(True.getDesc().TSFlags) && + !TrueVL.isIdenticalTo(MinVL)) return false; - if (RISCVII::elementsDependOnMask(RVVTSFlags) && !isAllOnesMask(Mask)) + if (RISCVII::elementsDependOnMask(True.getDesc().TSFlags) && + !isAllOnesMask(Mask)) return false; // Use a tumu policy, relaxing it to tail agnostic provided that the passthru From 7321018798c0e51225850381ac87e2795d094f27 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 22 Jul 2025 00:37:14 +0800 Subject: [PATCH 2/4] Indent tablgen properly --- .../Target/RISCV/RISCVInstrInfoVPseudos.td | 269 +++++++++--------- llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td | 13 +- llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td | 11 +- llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td | 24 +- 4 files changed, 166 insertions(+), 151 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 7d3e799bb205f..1b6db9b664771 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -791,8 +791,8 @@ class VPseudoUSLoadNoMask : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew, - vec_policy:$policy), []>, + (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, + sewop:$sew, vec_policy:$policy), []>, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -806,9 +806,9 @@ class VPseudoUSLoadNoMask : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - GPRMemZeroOffset:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, + (ins GetVRegNoV0.R:$passthru, + GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -824,8 +824,8 @@ class VPseudoUSLoadMask : RISCVVPseudo<(outs RetClass:$rd, GPR:$vl), - (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl, - sew:$sew, vec_policy:$policy), []>, + (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl, + sew:$sew, vec_policy:$policy), []>, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -839,9 +839,9 @@ class VPseudoUSLoadFFNoMask : RISCVVPseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), - (ins GetVRegNoV0.R:$passthru, - GPRMemZeroOffset:$rs1, - VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>, + (ins GetVRegNoV0.R:$passthru, + GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$avl, sew:$sew, + vec_policy:$policy), []>, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -857,8 +857,8 @@ class VPseudoUSLoadFFMask : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2, AVL:$vl, - sew:$sew, vec_policy:$policy), []>, + (ins RetClass:$dest, GPRMemZeroOffset:$rs1, GPR:$rs2, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -872,9 +872,9 @@ class VPseudoSLoadNoMask : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - GPRMemZeroOffset:$rs1, GPR:$rs2, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, + (ins GetVRegNoV0.R:$passthru, + GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm, AVL:$vl, + sew:$sew, vec_policy:$policy), []>, RISCVVLE { let mayLoad = 1; let mayStore = 0; @@ -895,8 +895,8 @@ class VPseudoILoadNoMask TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl, - sew:$sew, vec_policy:$policy), []>, + (ins RetClass:$dest, GPRMemZeroOffset:$rs1, IdxClass:$rs2, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVLX { let mayLoad = 1; let mayStore = 0; @@ -916,9 +916,9 @@ class VPseudoILoadMask TargetConstraintType = 1> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - GPRMemZeroOffset:$rs1, IdxClass:$rs2, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, + (ins GetVRegNoV0.R:$passthru, + GPRMemZeroOffset:$rs1, IdxClass:$rs2, VMaskOp:$vm, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVLX { let mayLoad = 1; let mayStore = 0; @@ -936,7 +936,8 @@ class VPseudoUSStoreNoMask : RISCVVPseudo<(outs), - (ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew), []>, + (ins StClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, + sewop:$sew), []>, RISCVVSE { let mayLoad = 0; let mayStore = 1; @@ -948,8 +949,8 @@ class VPseudoUSStoreNoMask : RISCVVPseudo<(outs), - (ins StClass:$rd, GPRMemZeroOffset:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew), []>, + (ins StClass:$rd, GPRMemZeroOffset:$rs1, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVSE { let mayLoad = 0; let mayStore = 1; @@ -962,8 +963,8 @@ class VPseudoUSStoreMask : RISCVVPseudo<(outs), - (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, - AVL:$vl, sew:$sew), []>, + (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, + AVL:$vl, sew:$sew), []>, RISCVVSE { let mayLoad = 0; let mayStore = 1; @@ -975,8 +976,8 @@ class VPseudoSStoreNoMask : RISCVVPseudo<(outs), - (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, - VMaskOp:$vm, AVL:$vl, sew:$sew), []>, + (ins StClass:$rd, GPRMemZeroOffset:$rs1, GPR:$rs2, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVSE { let mayLoad = 0; let mayStore = 1; @@ -988,8 +989,8 @@ class VPseudoSStoreMask : RISCVVPseudo<(outs RegClass:$rd), - (ins RegClass:$passthru, - AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins RegClass:$passthru, + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1001,8 +1002,9 @@ class VPseudoNullaryNoMask : class VPseudoNullaryMask : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins GetVRegNoV0.R:$passthru, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), + []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1032,8 +1034,8 @@ class VPseudoUnaryNoMask TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, OpClass:$rs2, - AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins RetClass:$passthru, OpClass:$rs2, + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1049,7 +1051,7 @@ class VPseudoUnaryNoMaskNoPolicy TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []> { + (ins OpClass:$rs2, AVL:$vl, sew_mask:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1064,8 +1066,8 @@ class VPseudoUnaryNoMaskRoundingMode TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins RetClass:$passthru, OpClass:$rs2, vec_rm:$rm, + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1085,8 +1087,8 @@ class VPseudoUnaryMask TargetConstraintType = 1, DAGOperand sewop = sew> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []> { + (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, + VMaskOp:$vm, AVL:$vl, sewop:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1104,9 +1106,9 @@ class VPseudoUnaryMaskRoundingMode TargetConstraintType = 1> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, - VMaskOp:$vm, vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins GetVRegNoV0.R:$passthru, OpClass:$rs2, + VMaskOp:$vm, vec_rm:$rm, + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1141,7 +1143,7 @@ class VPseudoUnaryMask_NoExcept { + (ins VR:$rs2, AVL:$vl, sew_mask:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1151,7 +1153,7 @@ class VPseudoUnaryNoMaskGPROut : class VPseudoUnaryMaskGPROut : RISCVVPseudo<(outs GPR:$rd), - (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []> { + (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, sew_mask:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1164,8 +1166,8 @@ class VPseudoUnaryMaskGPROut : class VPseudoUnaryAnyMask : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, Op1Class:$rs2, - VR:$vm, AVL:$vl, sew:$sew), []> { + (ins RetClass:$passthru, Op1Class:$rs2, + VR:$vm, AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1181,7 +1183,8 @@ class VPseudoBinaryNoMask TargetConstraintType = 1, DAGOperand sewop = sew> : RISCVVPseudo<(outs RetClass:$rd), - (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), []> { + (ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, sewop:$sew), + []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1197,8 +1200,8 @@ class VPseudoBinaryNoMaskPolicy TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, - sew:$sew, vec_policy:$policy), []> { + (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1216,8 +1219,9 @@ class VPseudoBinaryNoMaskRoundingMode TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, + vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), + []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1238,10 +1242,10 @@ class VPseudoBinaryMaskPolicyRoundingMode TargetConstraintType = 1> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, vec_rm:$rm, AVL:$vl, - sew:$sew, vec_policy:$policy), []> { + (ins GetVRegNoV0.R:$passthru, + Op1Class:$rs2, Op2Class:$rs1, + VMaskOp:$vm, vec_rm:$rm, AVL:$vl, + sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1265,8 +1269,8 @@ class VPseudoTiedBinaryNoMask TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew, - vec_policy:$policy), []> { + (ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, sew:$sew, + vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1285,10 +1289,10 @@ class VPseudoTiedBinaryNoMaskRoundingMode TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$rs2, Op2Class:$rs1, - vec_rm:$rm, - AVL:$vl, sew:$sew, - vec_policy:$policy), []> { + (ins RetClass:$rs2, Op2Class:$rs1, + vec_rm:$rm, + AVL:$vl, sew:$sew, + vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1308,8 +1312,8 @@ class VPseudoTiedBinaryNoMaskRoundingMode LMUL, bit Ordered>: RISCVVPseudo<(outs), - (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, AVL:$vl, - sew:$sew),[]>, + (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, + AVL:$vl, sew:$sew),[]>, RISCVVSX { let mayLoad = 0; let mayStore = 1; @@ -1321,8 +1325,8 @@ class VPseudoIStoreNoMask LMUL, class VPseudoIStoreMask LMUL, bit Ordered>: RISCVVPseudo<(outs), - (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, - VMaskOp:$vm, AVL:$vl, sew:$sew),[]>, + (ins StClass:$rd, GPRMemZeroOffset:$rs1, IdxClass:$rs2, + VMaskOp:$vm, AVL:$vl, sew:$sew),[]>, RISCVVSX { let mayLoad = 0; let mayStore = 1; @@ -1338,9 +1342,10 @@ class VPseudoBinaryMaskPolicy TargetConstraintType = 1> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins GetVRegNoV0.R:$passthru, + Op1Class:$rs2, Op2Class:$rs1, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), + []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1357,9 +1362,10 @@ class VPseudoTernaryMaskPolicy : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins GetVRegNoV0.R:$passthru, + Op1Class:$rs2, Op2Class:$rs1, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), + []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1374,11 +1380,11 @@ class VPseudoTernaryMaskPolicyRoundingMode : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, - vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins GetVRegNoV0.R:$passthru, + Op1Class:$rs2, Op2Class:$rs1, + VMaskOp:$vm, + vec_rm:$rm, + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1399,9 +1405,10 @@ class VPseudoBinaryMOutMask TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, - Op1Class:$rs2, Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins RetClass:$passthru, + Op1Class:$rs2, Op2Class:$rs1, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), + []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1422,9 +1429,10 @@ class VPseudoTiedBinaryMask TargetConstraintType = 1> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - Op2Class:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins GetVRegNoV0.R:$passthru, + Op2Class:$rs1, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), + []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1443,11 +1451,11 @@ class VPseudoTiedBinaryMaskRoundingMode TargetConstraintType = 1> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - Op2Class:$rs1, - VMaskOp:$vm, - vec_rm:$rm, - AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins GetVRegNoV0.R:$passthru, + Op2Class:$rs1, + VMaskOp:$vm, + vec_rm:$rm, + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1472,11 +1480,11 @@ class VPseudoBinaryCarry TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - !if(CarryIn, - (ins Op1Class:$rs2, Op2Class:$rs1, - VMV0:$carry, AVL:$vl, sew:$sew), - (ins Op1Class:$rs2, Op2Class:$rs1, - AVL:$vl, sew:$sew)), []> { + !if(CarryIn, + (ins Op1Class:$rs2, Op2Class:$rs1, + VMV0:$carry, AVL:$vl, sew:$sew), + (ins Op1Class:$rs2, Op2Class:$rs1, + AVL:$vl, sew:$sew)), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1493,8 +1501,8 @@ class VPseudoTiedBinaryCarryIn TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, - VMV0:$carry, AVL:$vl, sew:$sew), []> { + (ins RetClass:$passthru, Op1Class:$rs2, Op2Class:$rs1, + VMV0:$carry, AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1511,8 +1519,8 @@ class VPseudoTernaryNoMask : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - AVL:$vl, sew:$sew), []> { + (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1527,8 +1535,8 @@ class VPseudoTernaryNoMaskWithPolicy TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, + AVL:$vl, sew:$sew, vec_policy:$policy), []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1545,8 +1553,9 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode TargetConstraintType = 1> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, - vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), []> { + (ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2, + vec_rm:$rm, AVL:$vl, sew:$sew, vec_policy:$policy), + []> { let mayLoad = 0; let mayStore = 0; let hasSideEffects = 0; @@ -1564,8 +1573,8 @@ class VPseudoUSSegLoadNoMask NF> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, - sew:$sew, vec_policy:$policy), []>, + (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, + sew:$sew, vec_policy:$policy), []>, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1580,8 +1589,9 @@ class VPseudoUSSegLoadMask NF> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, + (ins GetVRegNoV0.R:$passthru, + GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1598,8 +1608,8 @@ class VPseudoUSSegLoadFFNoMask NF> : RISCVVPseudo<(outs RetClass:$rd, GPR:$vl), - (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl, - sew:$sew, vec_policy:$policy), []>, + (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$avl, + sew:$sew, vec_policy:$policy), []>, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1614,8 +1624,9 @@ class VPseudoUSSegLoadFFMask NF> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd, GPR:$vl), - (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, - VMaskOp:$vm, AVL:$avl, sew:$sew, vec_policy:$policy), []>, + (ins GetVRegNoV0.R:$passthru, + GPRMemZeroOffset:$rs1, VMaskOp:$vm, AVL:$avl, sew:$sew, + vec_policy:$policy), []>, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1632,8 +1643,8 @@ class VPseudoSSegLoadNoMask NF> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset, AVL:$vl, - sew:$sew, vec_policy:$policy), []>, + (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, GPR:$offset, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1648,9 +1659,9 @@ class VPseudoSSegLoadMask NF> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, - GPR:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew, - vec_policy:$policy), []>, + (ins GetVRegNoV0.R:$passthru, + GPRMemZeroOffset:$rs1, GPR:$offset, VMaskOp:$vm, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVLSEG { let mayLoad = 1; let mayStore = 0; @@ -1670,8 +1681,9 @@ class VPseudoISegLoadNoMask NF, bit Ordered> : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, IdxClass:$offset, AVL:$vl, - sew:$sew, vec_policy:$policy), []>, + (ins RetClass:$passthru, GPRMemZeroOffset:$rs1, + IdxClass:$offset, AVL:$vl, sew:$sew, + vec_policy:$policy), []>, RISCVVLXSEG { let mayLoad = 1; let mayStore = 0; @@ -1691,9 +1703,9 @@ class VPseudoISegLoadMask NF, bit Ordered> : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, GPRMemZeroOffset:$rs1, - IdxClass:$offset, VMaskOp:$vm, AVL:$vl, sew:$sew, - vec_policy:$policy), []>, + (ins GetVRegNoV0.R:$passthru, + GPRMemZeroOffset:$rs1, IdxClass:$offset, VMaskOp:$vm, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVVLXSEG { let mayLoad = 1; let mayStore = 0; @@ -1712,7 +1724,8 @@ class VPseudoUSSegStoreNoMask NF> : RISCVVPseudo<(outs), - (ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew), []>, + (ins ValClass:$rd, GPRMemZeroOffset:$rs1, AVL:$vl, sew:$sew), + []>, RISCVVSSEG { let mayLoad = 0; let mayStore = 1; @@ -1725,8 +1738,8 @@ class VPseudoUSSegStoreMask NF> : RISCVVPseudo<(outs), - (ins ValClass:$rd, GPRMemZeroOffset:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew), []>, + (ins ValClass:$rd, GPRMemZeroOffset:$rs1, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVSSEG { let mayLoad = 0; let mayStore = 1; @@ -1740,8 +1753,8 @@ class VPseudoSSegStoreNoMask NF> : RISCVVPseudo<(outs), - (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset, - AVL:$vl, sew:$sew), []>, + (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR:$offset, + AVL:$vl, sew:$sew), []>, RISCVVSSEG { let mayLoad = 0; let mayStore = 1; @@ -1754,8 +1767,8 @@ class VPseudoSSegStoreMask NF> : RISCVVPseudo<(outs), - (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset, - VMaskOp:$vm, AVL:$vl, sew:$sew), []>, + (ins ValClass:$rd, GPRMemZeroOffset:$rs1, GPR: $offset, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVSSEG { let mayLoad = 0; let mayStore = 1; @@ -1772,8 +1785,8 @@ class VPseudoISegStoreNoMask NF, bit Ordered> : RISCVVPseudo<(outs), - (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index, - AVL:$vl, sew:$sew), []>, + (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index, + AVL:$vl, sew:$sew), []>, RISCVVSXSEG { let mayLoad = 0; let mayStore = 1; @@ -1789,8 +1802,8 @@ class VPseudoISegStoreMask NF, bit Ordered> : RISCVVPseudo<(outs), - (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index, - VMaskOp:$vm, AVL:$vl, sew:$sew), []>, + (ins ValClass:$rd, GPRMemZeroOffset:$rs1, IdxClass: $index, + VMaskOp:$vm, AVL:$vl, sew:$sew), []>, RISCVVSXSEG { let mayLoad = 0; let mayStore = 1; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td index 786183421feed..1bb67f4cc7c59 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td @@ -449,9 +449,9 @@ class NDSRVInstVLN funct5, string opcodestr> class VPseudoVLN8NoMask : RISCVVPseudo<(outs RetClass:$rd), - (ins RetClass:$dest, - GPRMemZeroOffset:$rs1, - AVL:$vl, sew:$sew, vec_policy:$policy), []>, + (ins RetClass:$dest, + GPRMemZeroOffset:$rs1, + AVL:$vl, sew:$sew, vec_policy:$policy), []>, RISCVNDSVLN { let mayLoad = 1; let mayStore = 0; @@ -464,9 +464,10 @@ class VPseudoVLN8NoMask : class VPseudoVLN8Mask : RISCVVPseudo<(outs GetVRegNoV0.R:$rd), - (ins GetVRegNoV0.R:$passthru, - GPRMemZeroOffset:$rs1, - VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>, + (ins GetVRegNoV0.R:$passthru, + GPRMemZeroOffset:$rs1, + VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), + []>, RISCVNDSVLN { let mayLoad = 1; let mayStore = 0; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td index 5395f3b3d52be..ebcf079f300b3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXRivos.td @@ -154,16 +154,17 @@ foreach m = MxList in { let VLMul = m.value in { let BaseInstr = RI_VEXTRACT in def PseudoRI_VEXTRACT_ # mx : - RISCVVPseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew), - []>; + RISCVVPseudo<(outs GPR:$rd), + (ins m.vrclass:$rs2, uimm5:$idx, ixlenimm:$sew), + []>; let HasVLOp = 1, BaseInstr = RI_VINSERT, HasVecPolicyOp = 1, Constraints = "$rd = $rs1" in def PseudoRI_VINSERT_ # mx : RISCVVPseudo<(outs m.vrclass:$rd), - (ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl, - ixlenimm:$sew, ixlenimm:$policy), - []>; + (ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl, + ixlenimm:$sew, ixlenimm:$policy), + []>; } } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 87e0b1b93bb0f..a47dfe363c21e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -244,8 +244,8 @@ let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvector", class VPseudoVC_X : RISCVVPseudo<(outs), - (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1, - AVL:$vl, sew:$sew), []> { + (ins OpClass:$op1, payload5:$rs2, payload5:$rd, RS1Class:$r1, + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -255,8 +255,8 @@ class VPseudoVC_X : class VPseudoVC_XV : RISCVVPseudo<(outs), - (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []> { + (ins OpClass:$op1, payload5:$rd, RS2Class:$rs2, RS1Class:$r1, + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -267,8 +267,8 @@ class VPseudoVC_XV : class VPseudoVC_XVV : RISCVVPseudo<(outs), - (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []> { + (ins OpClass:$op1, RDClass:$rd, RS2Class:$rs2, RS1Class:$r1, + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -278,8 +278,8 @@ class VPseudoVC_XVV : RISCVVPseudo<(outs RDClass:$rd), - (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []> { + (ins OpClass:$op1, payload5:$rs2, RS1Class:$r1, + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -290,8 +290,8 @@ class VPseudoVC_V_X : class VPseudoVC_V_XV : RISCVVPseudo<(outs RDClass:$rd), - (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []> { + (ins OpClass:$op1, RS2Class:$rs2, RS1Class:$r1, + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; @@ -302,8 +302,8 @@ class VPseudoVC_V_XV : RISCVVPseudo<(outs RDClass:$rd), - (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1, - AVL:$vl, sew:$sew), []> { + (ins OpClass:$op1, RDClass:$rs3, RS2Class:$rs2, RS1Class:$r1, + AVL:$vl, sew:$sew), []> { let mayLoad = 0; let mayStore = 0; let HasVLOp = 1; From 2590e748be17d5a081a0262f9009105f27a74730 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Tue, 22 Jul 2025 15:52:47 +0800 Subject: [PATCH 3/4] Don't copy over TSFlags --- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 4 ---- llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 6 +++++- llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp | 15 ++++++++------- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 1b6db9b664771..abc575eb40c0d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -550,10 +550,6 @@ class RISCVVPseudo pattern, string opcodestr = "", // SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown). bits<8> SEW = 0; bit IncludeInInversePseudoTable = 1; - - // Set common TSFlags in RVInst from the base instruction. - let ElementsDependOn = !cast(BaseInstr).ElementsDependOn; - let DestEEW = !cast(BaseInstr).DestEEW; } // The actual table. diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp index ee63e19350a9f..15bd3466373a7 100644 --- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp @@ -33,6 +33,7 @@ namespace { class RISCVVLOptimizer : public MachineFunctionPass { const MachineRegisterInfo *MRI; const MachineDominatorTree *MDT; + const TargetInstrInfo *TII; public: static char ID; @@ -1291,7 +1292,8 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const { return false; } - assert(!RISCVII::elementsDependOnVL(MI.getDesc().TSFlags) && + assert(!RISCVII::elementsDependOnVL( + TII->get(RISCV::getRVVMCOpcode(MI.getOpcode())).TSFlags) && "Instruction shouldn't be supported if elements depend on VL"); assert(MI.getOperand(0).isReg() && @@ -1495,6 +1497,8 @@ bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) { if (!ST.hasVInstructions()) return false; + TII = ST.getInstrInfo(); + // For each instruction that defines a vector, compute what VL its // downstream users demand. for (MachineBasicBlock *MBB : post_order(&MF)) { diff --git a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp index b249795dfe52d..84ef53985484f 100644 --- a/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp +++ b/llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp @@ -91,7 +91,8 @@ bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User, User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm(); unsigned SrcLog2SEW = Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm(); - unsigned SrcLog2EEW = RISCV::getDestLog2EEW(Src.getDesc(), SrcLog2SEW); + unsigned SrcLog2EEW = RISCV::getDestLog2EEW( + TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())), SrcLog2SEW); return SrcLog2EEW == UserLog2SEW; } @@ -169,8 +170,8 @@ bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const { if (!hasSameEEW(MI, *Src)) continue; - bool ElementsDependOnVL = - RISCVII::elementsDependOnVL(Src->getDesc().TSFlags); + bool ElementsDependOnVL = RISCVII::elementsDependOnVL( + TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags); if (ElementsDependOnVL || Src->mayRaiseFPException()) continue; @@ -759,11 +760,11 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const { else return false; - if (RISCVII::elementsDependOnVL(True.getDesc().TSFlags) && - !TrueVL.isIdenticalTo(MinVL)) + unsigned RVVTSFlags = + TII->get(RISCV::getRVVMCOpcode(True.getOpcode())).TSFlags; + if (RISCVII::elementsDependOnVL(RVVTSFlags) && !TrueVL.isIdenticalTo(MinVL)) return false; - if (RISCVII::elementsDependOnMask(True.getDesc().TSFlags) && - !isAllOnesMask(Mask)) + if (RISCVII::elementsDependOnMask(RVVTSFlags) && !isAllOnesMask(Mask)) return false; // Use a tumu policy, relaxing it to tail agnostic provided that the passthru From 3f66dc8f44bef4402326be6daa3a8b3f89236902 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Wed, 23 Jul 2025 16:28:34 +0800 Subject: [PATCH 4/4] Default pattern to [] --- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index abc575eb40c0d..dfa532ae5edb6 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -543,7 +543,7 @@ defset list AllWidenableBFloatToFloatVectors = { // This represents the information we need in codegen for each pseudo. // The definition should be consistent with `struct PseudoInfo` in // RISCVInstrInfo.h. -class RISCVVPseudo pattern, string opcodestr = "", string argstr = ""> +class RISCVVPseudo pattern = [], string opcodestr = "", string argstr = ""> : Pseudo { Pseudo Pseudo = !cast(NAME); // Used as a key. Instruction BaseInstr = !cast(PseudoToVInst.VInst);