From 46168d0d4c00066dc13ea651d98b6d3b2af79833 Mon Sep 17 00:00:00 2001 From: Martin Wehking Date: Mon, 21 Jul 2025 12:18:19 +0000 Subject: [PATCH] Fix implicit vector conversion Previously, the unsigned NEON intrinsic variants of 'vqshrun_high_n' and 'vqrshrun_high_n' were using signed integer types for their first argument and return values. These should be unsigned according to developer.arm.com, however. Adjust the test cases accordingly. --- clang/include/clang/Basic/arm_neon.td | 4 ++-- clang/test/CodeGen/AArch64/neon-intrinsics.c | 12 ++++++------ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td index 0daef4ad1701f..ef196103035e8 100644 --- a/clang/include/clang/Basic/arm_neon.td +++ b/clang/include/clang/Basic/arm_neon.td @@ -964,11 +964,11 @@ def SLI_N : WInst<"vsli_n", "...I", "PlQPl", [ImmCheck<2, ImmCheckShiftLeft, 0>] // Right shift narrow high def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "<(; -def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "<(; def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "<(; -def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "<(; def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "<(; diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 6304245614342..035e1ca1b45e8 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -8585,7 +8585,7 @@ uint32x2_t test_vqshrun_n_s64(int64x2_t a) { // CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[VQSHRUN_N3]], <16 x i32> // CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]] // -int8x16_t test_vqshrun_high_n_s16(int8x8_t a, int16x8_t b) { +uint8x16_t test_vqshrun_high_n_s16(uint8x8_t a, int16x8_t b) { return vqshrun_high_n_s16(a, b, 3); } @@ -8598,7 +8598,7 @@ int8x16_t test_vqshrun_high_n_s16(int8x8_t a, int16x8_t b) { // CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[VQSHRUN_N3]], <8 x i32> // CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]] // -int16x8_t test_vqshrun_high_n_s32(int16x4_t a, int32x4_t b) { +uint16x8_t test_vqshrun_high_n_s32(uint16x4_t a, int32x4_t b) { return vqshrun_high_n_s32(a, b, 9); } @@ -8611,7 +8611,7 @@ int16x8_t test_vqshrun_high_n_s32(int16x4_t a, int32x4_t b) { // CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> [[VQSHRUN_N3]], <4 x i32> // CHECK-NEXT: ret <4 x i32> [[SHUFFLE_I]] // -int32x4_t test_vqshrun_high_n_s64(int32x2_t a, int64x2_t b) { +uint32x4_t test_vqshrun_high_n_s64(uint32x2_t a, int64x2_t b) { return vqshrun_high_n_s64(a, b, 19); } @@ -8810,7 +8810,7 @@ uint32x2_t test_vqrshrun_n_s64(int64x2_t a) { // CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <8 x i8> [[A]], <8 x i8> [[VQRSHRUN_N3]], <16 x i32> // CHECK-NEXT: ret <16 x i8> [[SHUFFLE_I]] // -int8x16_t test_vqrshrun_high_n_s16(int8x8_t a, int16x8_t b) { +uint8x16_t test_vqrshrun_high_n_s16(uint8x8_t a, int16x8_t b) { return vqrshrun_high_n_s16(a, b, 3); } @@ -8823,7 +8823,7 @@ int8x16_t test_vqrshrun_high_n_s16(int8x8_t a, int16x8_t b) { // CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <4 x i16> [[A]], <4 x i16> [[VQRSHRUN_N3]], <8 x i32> // CHECK-NEXT: ret <8 x i16> [[SHUFFLE_I]] // -int16x8_t test_vqrshrun_high_n_s32(int16x4_t a, int32x4_t b) { +uint16x8_t test_vqrshrun_high_n_s32(uint16x4_t a, int32x4_t b) { return vqrshrun_high_n_s32(a, b, 9); } @@ -8836,7 +8836,7 @@ int16x8_t test_vqrshrun_high_n_s32(int16x4_t a, int32x4_t b) { // CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i32> [[A]], <2 x i32> [[VQRSHRUN_N3]], <4 x i32> // CHECK-NEXT: ret <4 x i32> [[SHUFFLE_I]] // -int32x4_t test_vqrshrun_high_n_s64(int32x2_t a, int64x2_t b) { +uint32x4_t test_vqrshrun_high_n_s64(uint32x2_t a, int64x2_t b) { return vqrshrun_high_n_s64(a, b, 19); }