From 3b16b717e84ab3d390c6be82b468ddc6332fce22 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Tue, 22 Jul 2025 09:19:13 -0700 Subject: [PATCH] [RISCV] Correct alignment of one-active (de)interleave cases Noticed this while going to rewrite the load case as a DAG combine. I don't have a test case which demonstrates this leading to a miscompile, but it seems like it could be possible. --- llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp index 25817b6d2707f..878401ef4063f 100644 --- a/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp +++ b/llvm/lib/Target/RISCV/RISCVInterleavedAccess.cpp @@ -232,6 +232,7 @@ bool RISCVTargetLowering::lowerInterleavedLoad( Builder.CreateIntrinsic(Intrinsic::experimental_vp_strided_load, {VTy, BasePtr->getType(), Stride->getType()}, {BasePtr, Stride, Mask, VL}); + Alignment = commonAlignment(Alignment, Indices[0] * ScalarSizeInBytes); CI->addParamAttr(0, Attribute::getWithAlignment(CI->getContext(), Alignment)); Shuffles[0]->replaceAllUsesWith(CI); @@ -303,8 +304,9 @@ bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI, Intrinsic::experimental_vp_strided_store, {Data->getType(), BasePtr->getType(), Stride->getType()}, {Data, BasePtr, Stride, Mask, VL}); + Align Alignment = commonAlignment(SI->getAlign(), Index * ScalarSizeInBytes); CI->addParamAttr( - 1, Attribute::getWithAlignment(CI->getContext(), SI->getAlign())); + 1, Attribute::getWithAlignment(CI->getContext(), Alignment)); return true; }