[AArch64] Replace Glue with MVT::i32 when dealing with carries #150328
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There is no need for the Glue anyway, I am surprised it worked honestly.
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@llvm/pr-subscribers-backend-aarch64 Author: AZero13 (AZero13) ChangesThere is no need for the Glue anyway, I am surprised it worked honestly. Full diff: https://github.com/llvm/llvm-project/pull/150328.diff 4 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index ff23f76fadccd..75599c1bb0ae1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -4177,7 +4177,7 @@ static SDValue valueToCarryFlag(SDValue Value, SelectionDAG &DAG, bool Invert) {
SDValue Op0 = Invert ? DAG.getConstant(0, DL, VT) : Value;
SDValue Op1 = Invert ? Value : DAG.getConstant(1, DL, VT);
SDValue Cmp =
- DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::Glue), Op0, Op1);
+ DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, MVT::i32), Op0, Op1);
return Cmp.getValue(1);
}
@@ -4222,7 +4222,7 @@ static SDValue lowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG,
SDLoc DL(Op);
SDVTList VTs = DAG.getVTList(VT0, VT1);
- SDValue Sum = DAG.getNode(Opcode, DL, DAG.getVTList(VT0, MVT::Glue), OpLHS,
+ SDValue Sum = DAG.getNode(Opcode, DL, DAG.getVTList(VT0, MVT::i32), OpLHS,
OpRHS, OpCarryIn);
SDValue OutFlag =
@@ -11106,7 +11106,7 @@ SDValue AArch64TargetLowering::LowerSETCCCARRY(SDValue Op,
SDValue Carry = Op.getOperand(2);
// SBCS uses a carry not a borrow so the carry flag should be inverted first.
SDValue InvCarry = valueToCarryFlag(Carry, DAG, true);
- SDValue Cmp = DAG.getNode(AArch64ISD::SBCS, DL, DAG.getVTList(VT, MVT::Glue),
+ SDValue Cmp = DAG.getNode(AArch64ISD::SBCS, DL, DAG.getVTList(VT, MVT::i32),
LHS, RHS, InvCarry);
EVT OpVT = Op.getValueType();
diff --git a/llvm/test/CodeGen/AArch64/abds-neg.ll b/llvm/test/CodeGen/AArch64/abds-neg.ll
index ac7cb1f619557..432ffc30eec5e 100644
--- a/llvm/test/CodeGen/AArch64/abds-neg.ll
+++ b/llvm/test/CodeGen/AArch64/abds-neg.ll
@@ -200,8 +200,7 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
-; CHECK-NEXT: sbc x11, x3, x1
-; CHECK-NEXT: sbcs xzr, x3, x1
+; CHECK-NEXT: sbcs x11, x3, x1
; CHECK-NEXT: csel x8, x8, x10, lt
; CHECK-NEXT: csel x9, x9, x11, lt
; CHECK-NEXT: negs x0, x8
@@ -222,8 +221,7 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
-; CHECK-NEXT: sbc x11, x3, x1
-; CHECK-NEXT: sbcs xzr, x3, x1
+; CHECK-NEXT: sbcs x11, x3, x1
; CHECK-NEXT: csel x8, x8, x10, lt
; CHECK-NEXT: csel x9, x9, x11, lt
; CHECK-NEXT: negs x0, x8
@@ -389,14 +387,12 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_cmp_i128:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp x0, x2
-; CHECK-NEXT: sbc x8, x1, x3
-; CHECK-NEXT: subs x9, x2, x0
-; CHECK-NEXT: sbc x10, x3, x1
-; CHECK-NEXT: subs x11, x0, x2
-; CHECK-NEXT: sbcs xzr, x1, x3
-; CHECK-NEXT: csel x0, x11, x9, lt
-; CHECK-NEXT: csel x1, x8, x10, lt
+; CHECK-NEXT: subs x8, x2, x0
+; CHECK-NEXT: sbc x9, x3, x1
+; CHECK-NEXT: subs x10, x0, x2
+; CHECK-NEXT: sbcs x11, x1, x3
+; CHECK-NEXT: csel x0, x10, x8, lt
+; CHECK-NEXT: csel x1, x11, x9, lt
; CHECK-NEXT: ret
%cmp = icmp slt i128 %a, %b
%ab = sub i128 %a, %b
diff --git a/llvm/test/CodeGen/AArch64/abds.ll b/llvm/test/CodeGen/AArch64/abds.ll
index 62db30f17747c..ed1e6077948ee 100644
--- a/llvm/test/CodeGen/AArch64/abds.ll
+++ b/llvm/test/CodeGen/AArch64/abds.ll
@@ -183,8 +183,7 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
-; CHECK-NEXT: sbc x11, x3, x1
-; CHECK-NEXT: sbcs xzr, x3, x1
+; CHECK-NEXT: sbcs x11, x3, x1
; CHECK-NEXT: csel x0, x8, x10, lt
; CHECK-NEXT: csel x1, x9, x11, lt
; CHECK-NEXT: ret
@@ -202,8 +201,7 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
-; CHECK-NEXT: sbc x11, x3, x1
-; CHECK-NEXT: sbcs xzr, x3, x1
+; CHECK-NEXT: sbcs x11, x3, x1
; CHECK-NEXT: csel x0, x8, x10, lt
; CHECK-NEXT: csel x1, x9, x11, lt
; CHECK-NEXT: ret
@@ -279,8 +277,7 @@ define i128 @abd_minmax_i128(i128 %a, i128 %b) nounwind {
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
-; CHECK-NEXT: sbc x11, x3, x1
-; CHECK-NEXT: sbcs xzr, x3, x1
+; CHECK-NEXT: sbcs x11, x3, x1
; CHECK-NEXT: csel x0, x8, x10, lt
; CHECK-NEXT: csel x1, x9, x11, lt
; CHECK-NEXT: ret
@@ -358,8 +355,7 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
-; CHECK-NEXT: sbc x11, x3, x1
-; CHECK-NEXT: sbcs xzr, x3, x1
+; CHECK-NEXT: sbcs x11, x3, x1
; CHECK-NEXT: csel x0, x8, x10, lt
; CHECK-NEXT: csel x1, x9, x11, lt
; CHECK-NEXT: ret
@@ -607,8 +603,7 @@ define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
; CHECK-NEXT: subs x8, x0, x2
; CHECK-NEXT: sbc x9, x1, x3
; CHECK-NEXT: subs x10, x2, x0
-; CHECK-NEXT: sbc x11, x3, x1
-; CHECK-NEXT: sbcs xzr, x3, x1
+; CHECK-NEXT: sbcs x11, x3, x1
; CHECK-NEXT: csel x0, x8, x10, lt
; CHECK-NEXT: csel x1, x9, x11, lt
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/abdu-neg.ll b/llvm/test/CodeGen/AArch64/abdu-neg.ll
index 2118816ca7c58..8fb106e92866e 100644
--- a/llvm/test/CodeGen/AArch64/abdu-neg.ll
+++ b/llvm/test/CodeGen/AArch64/abdu-neg.ll
@@ -391,14 +391,12 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; CHECK-LABEL: abd_cmp_i128:
; CHECK: // %bb.0:
-; CHECK-NEXT: cmp x0, x2
-; CHECK-NEXT: sbc x8, x1, x3
-; CHECK-NEXT: subs x9, x2, x0
-; CHECK-NEXT: sbc x10, x3, x1
-; CHECK-NEXT: subs x11, x0, x2
-; CHECK-NEXT: sbcs xzr, x1, x3
-; CHECK-NEXT: csel x0, x11, x9, lo
-; CHECK-NEXT: csel x1, x8, x10, lo
+; CHECK-NEXT: subs x8, x2, x0
+; CHECK-NEXT: sbc x9, x3, x1
+; CHECK-NEXT: subs x10, x0, x2
+; CHECK-NEXT: sbcs x11, x1, x3
+; CHECK-NEXT: csel x0, x10, x8, lo
+; CHECK-NEXT: csel x1, x11, x9, lo
; CHECK-NEXT: ret
%cmp = icmp ult i128 %a, %b
%ab = sub i128 %a, %b
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topperc
reviewed
Jul 23, 2025
AZero13
changed the title
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Thank you. @topperc Can you please merge? |
When CI finishes. |
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Isn't it a duplicate of #150313? |
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There is no need for the Glue anyway, I am surprised it worked honestly.