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[AArch64][InstCombine] Canonicalize whilelo intrinsic #151553

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Merged
merged 5 commits into from
Sep 12, 2025
Merged

[AArch64][InstCombine] Canonicalize whilelo intrinsic #151553

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f4711c6
[AArch64][InstCombine] Canonicalize whilelo intrinsic
MDevereau Jul 23, 2025
90ba31b
Add i64 test, rename tests, add nxv2i1 test
MDevereau Aug 1, 2025
e400fe1
Remove loads from tests
MDevereau Aug 1, 2025
614b6f9
Add test for (0,0)
MDevereau Sep 10, 2025
61572eb
Remove 16 bit tests
MDevereau Sep 11, 2025
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11 changes: 11 additions & 0 deletions llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2696,6 +2696,15 @@ static std::optional<Instruction *> instCombineDMB(InstCombiner &IC,
return std::nullopt;
}

static std::optional<Instruction *> instCombineWhilelo(InstCombiner &IC,
IntrinsicInst &II) {
return IC.replaceInstUsesWith(
II,
IC.Builder.CreateIntrinsic(Intrinsic::get_active_lane_mask,
{II.getType(), II.getOperand(0)->getType()},
{II.getOperand(0), II.getOperand(1)}));
}

static std::optional<Instruction *> instCombinePTrue(InstCombiner &IC,
IntrinsicInst &II) {
if (match(II.getOperand(0), m_ConstantInt<AArch64SVEPredPattern::all>()))
Expand Down Expand Up @@ -2830,6 +2839,8 @@ AArch64TTIImpl::instCombineIntrinsic(InstCombiner &IC,
return instCombineSVEDupqLane(IC, II);
case Intrinsic::aarch64_sve_insr:
return instCombineSVEInsr(IC, II);
case Intrinsic::aarch64_sve_whilelo:
return instCombineWhilelo(IC, II);
case Intrinsic::aarch64_sve_ptrue:
return instCombinePTrue(IC, II);
case Intrinsic::aarch64_sve_uxtb:
Expand Down
66 changes: 66 additions & 0 deletions llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-whilelo.ll
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@@ -0,0 +1,66 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -passes=instcombine < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"


define <vscale x 4 x float> @const_whilelo_nxv4i32(ptr %0) #0 {
; CHECK-LABEL: define <vscale x 4 x float> @const_whilelo_nxv4i32(
; CHECK-SAME: ptr [[TMP0:%.*]]) {
; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 4)
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@david-arm david-arm Aug 1, 2025

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It might be worth adding at least one test for the i64 variant too?

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@MDevereau MDevereau Aug 1, 2025

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Thanks. I've addressed all of your comments

; CHECK-NEXT: [[LOAD:%.*]] = tail call <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0(ptr nonnull [[TMP0]], i32 1, <vscale x 4 x i1> [[MASK]], <vscale x 4 x float> zeroinitializer)
; CHECK-NEXT: ret <vscale x 4 x float> [[LOAD]]
;
%mask = tail call <vscale x 4 x i1> @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 0, i32 4)
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@david-arm david-arm Aug 1, 2025

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Can you add a test for the nxv2i1 variant as well?

%load = tail call <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0(ptr nonnull %0, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x float> zeroinitializer)
ret <vscale x 4 x float> %load
}

define <vscale x 8 x float> @const_whilelo_nxv8f32(ptr %0) #0 {
; CHECK-LABEL: define <vscale x 8 x float> @const_whilelo_nxv8f32(
; CHECK-SAME: ptr [[TMP0:%.*]]) {
; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 0, i32 8)
; CHECK-NEXT: [[LOAD:%.*]] = tail call <vscale x 8 x float> @llvm.masked.load.nxv8f32.p0(ptr nonnull [[TMP0]], i32 1, <vscale x 8 x i1> [[MASK]], <vscale x 8 x float> zeroinitializer)
; CHECK-NEXT: ret <vscale x 8 x float> [[LOAD]]
;
%mask = tail call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 0, i32 8)
%load = tail call <vscale x 8 x float> @llvm.masked.load.nxv8f32.p0(ptr nonnull %0, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x float> zeroinitializer)
ret <vscale x 8 x float> %load
}

define <vscale x 8 x i16> @const_whilelo_nxv8i16(ptr %0) #0 {
; CHECK-LABEL: define <vscale x 8 x i16> @const_whilelo_nxv8i16(
; CHECK-SAME: ptr [[TMP0:%.*]]) {
; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 0, i32 8)
; CHECK-NEXT: [[LOAD:%.*]] = tail call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr nonnull [[TMP0]], i32 1, <vscale x 8 x i1> [[MASK]], <vscale x 8 x i16> zeroinitializer)
; CHECK-NEXT: ret <vscale x 8 x i16> [[LOAD]]
;
%mask = tail call <vscale x 8 x i1> @llvm.aarch64.sve.whilelo.nxv8i1.i16(i32 0, i32 8)
%load = tail call <vscale x 8 x i16> @llvm.masked.load.nxv8i16.p0(ptr nonnull %0, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x i16> zeroinitializer)
ret <vscale x 8 x i16> %load
}

define <vscale x 16 x i8> @const_whilelo_nxv16i8(ptr %0) #0 {
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@david-arm david-arm Aug 1, 2025

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nit: Can you name the tests according to the predicate variant, i.e. nxv16i1, nxv8i1, etc, since you're actually testing these variants of the whilelo intrinsic. Thanks!

; CHECK-LABEL: define <vscale x 16 x i8> @const_whilelo_nxv16i8(
; CHECK-SAME: ptr [[TMP0:%.*]]) {
; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 0, i32 16)
; CHECK-NEXT: [[LOAD:%.*]] = tail call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr nonnull [[TMP0]], i32 1, <vscale x 16 x i1> [[MASK]], <vscale x 16 x i8> zeroinitializer)
; CHECK-NEXT: ret <vscale x 16 x i8> [[LOAD]]
;
%mask = tail call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i8(i32 0, i32 16)
%load = tail call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr nonnull %0, i32 1, <vscale x 16 x i1> %mask, <vscale x 16 x i8> zeroinitializer)
ret <vscale x 16 x i8> %load
}


define <vscale x 16 x i8> @whilelo_nxv16i8(ptr %0, i32 %a, i32 %b) #0 {
; CHECK-LABEL: define <vscale x 16 x i8> @whilelo_nxv16i8(
; CHECK-SAME: ptr [[TMP0:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) {
; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i32(i32 [[A]], i32 [[B]])
; CHECK-NEXT: [[LOAD:%.*]] = tail call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr nonnull [[TMP0]], i32 1, <vscale x 16 x i1> [[MASK]], <vscale x 16 x i8> zeroinitializer)
; CHECK-NEXT: ret <vscale x 16 x i8> [[LOAD]]
;
%mask = tail call <vscale x 16 x i1> @llvm.aarch64.sve.whilelo.nxv16i1.i8(i32 %a, i32 %b)
%load = tail call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0(ptr nonnull %0, i32 1, <vscale x 16 x i1> %mask, <vscale x 16 x i8> zeroinitializer)
ret <vscale x 16 x i8> %load
}