llvm · RKSimon · Aug 4, 2025 · Aug 3, 2025
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -1550,7 +1550,7 @@ void PEIImpl::replaceFrameIndices(MachineBasicBlock *BB, MachineFunction &MF,
       // If this instruction has a FrameIndex operand, we need to
       // use that target machine register info object to eliminate
       // it.
-      TRI.eliminateFrameIndex(MI, SPAdj, i, RS);
+      TRI.eliminateFrameIndex(MI, SPAdj, i);
 
       // Reset the iterator if we were at the beginning of the BB.
       if (AtBeginning) {

diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -24,7 +24,6 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/CodeGen/WinEHFuncInfo.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/IR/EHPersonalities.h"
@@ -2679,7 +2678,7 @@ StackOffset X86FrameLowering::getFrameIndexReference(const MachineFunction &MF,
   // object.
   // We need to factor in additional offsets applied during the prologue to the
   // frame, base, and stack pointer depending on which is used.
-  int64_t Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
+  int Offset = MFI.getObjectOffset(FI) - getOffsetOfLocalArea();
   const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
   unsigned CSSize = X86FI->getCalleeSavedFrameSize();
   uint64_t StackSize = MFI.getStackSize();
@@ -4213,14 +4212,6 @@ void X86FrameLowering::processFunctionBeforeFrameFinalized(
   // emitPrologue if it gets called and emits CFI.
   MF.setHasWinCFI(false);
 
-  MachineFrameInfo &MFI = MF.getFrameInfo();
-  // If the frame is big enough that we might need to scavenge a register to
-  // handle huge offsets, reserve a stack slot for that now.
-  if (!isInt<32>(MFI.estimateStackSize(MF))) {
-    int FI = MFI.CreateStackObject(SlotSize, Align(SlotSize), false);
-    RS->addScavengingFrameIndex(FI);
-  }
-
   // If we are using Windows x64 CFI, ensure that the stack is always 8 byte
   // aligned. The format doesn't support misaligned stack adjustments.
   if (MF.getTarget().getMCAsmInfo()->usesWindowsCFI())

diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -13,7 +13,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86RegisterInfo.h"
-#include "MCTargetDesc/X86BaseInfo.h"
 #include "X86FrameLowering.h"
 #include "X86MachineFunctionInfo.h"
 #include "X86Subtarget.h"
@@ -22,8 +21,8 @@
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/CodeGen/LiveRegMatrix.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/CodeGen/TargetFrameLowering.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TileShapeInfo.h"
@@ -908,7 +907,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
 
   // Determine base register and offset.
-  int64_t FIOffset;
+  int FIOffset;
   Register BasePtr;
   if (MI.isReturn()) {
     assert((!hasStackRealignment(MF) ||
@@ -959,37 +958,11 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   }
 
   if (MI.getOperand(FIOperandNum+3).isImm()) {
-    int64_t Imm = MI.getOperand(FIOperandNum + 3).getImm();
-    int64_t Offset = FIOffset + Imm;
-    bool FitsIn32Bits = isInt<32>(Offset);
-    // If the offset will not fit in a 32-bit displacement, then for 64-bit
-    // targets, scavenge a register to hold it. Otherwise...
-    if (Is64Bit && !FitsIn32Bits) {
-      assert(RS && "RegisterScavenger was NULL");
-      const X86InstrInfo *TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
-      const DebugLoc &DL = MI.getDebugLoc();
-
-      RS->enterBasicBlockEnd(MBB);
-      RS->backward(std::next(II));
-
-      Register ScratchReg = RS->scavengeRegisterBackwards(
-          X86::GR64RegClass, II, /*RestoreAfter=*/false, /*SPAdj=*/0,
-          /*AllowSpill=*/true);
-      assert(ScratchReg != 0 && "scratch reg was 0");
-      RS->setRegUsed(ScratchReg);
-
-      BuildMI(MBB, II, DL, TII->get(X86::MOV64ri), ScratchReg).addImm(Offset);
-
-      MI.getOperand(FIOperandNum + 3).setImm(0);
-      MI.getOperand(FIOperandNum + 2).setReg(ScratchReg);
-
-      return false;
-    }
-
-    // ... for 32-bit targets, this is a bug!
-    if (!Is64Bit && !FitsIn32Bits)
-      MI.emitGenericError(("64-bit offset calculated but target is 32-bit"));
-
+    // Offset is a 32-bit integer.
+    int Imm = (int)(MI.getOperand(FIOperandNum + 3).getImm());
+    int Offset = FIOffset + Imm;
+    assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) &&
+           "Requesting 64-bit offset in 32-bit immediate!");
     if (Offset != 0 || !tryOptimizeLEAtoMOV(II))
       MI.getOperand(FIOperandNum + 3).ChangeToImmediate(Offset);
   } else {

diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h
@@ -13,7 +13,6 @@
 #ifndef LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
 #define LLVM_LIB_TARGET_X86_X86REGISTERINFO_H
 
-#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
 #define GET_REGINFO_HEADER
@@ -181,10 +180,6 @@ class X86RegisterInfo final : public X86GenRegisterInfo {
   constrainRegClassToNonRex2(const TargetRegisterClass *RC) const;
 
   bool isNonRex2RegClass(const TargetRegisterClass *RC) const;
-
-  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
-    return true;
-  }
 };
 
 } // End llvm namespace

diff --git a/llvm/test/CodeGen/X86/avx512f-large-stack.ll b/llvm/test/CodeGen/X86/avx512f-large-stack.ll
diff --git a/llvm/test/CodeGen/X86/huge-stack.ll b/llvm/test/CodeGen/X86/huge-stack.ll
@@ -5,70 +5,20 @@
 define void @foo() unnamed_addr #0 {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movabsq $8589934472, %rax # imm = 0x1FFFFFF88
+; CHECK-NEXT:    movabsq $8589934462, %rax # imm = 0x1FFFFFF7E
 ; CHECK-NEXT:    subq %rax, %rsp
-; CHECK-NEXT:    .cfi_def_cfa_offset 8589934480
-; CHECK-NEXT:    movabsq $4294967177, %rax # imm = 0xFFFFFF89
-; CHECK-NEXT:    movb $42, (%rsp,%rax)
-; CHECK-NEXT:    movb $43, -118(%rsp)
-; CHECK-NEXT:    movabsq $8589934472, %rax # imm = 0x1FFFFFF88
+; CHECK-NEXT:    .cfi_def_cfa_offset 8589934470
+; CHECK-NEXT:    movb $42, -129(%rsp)
+; CHECK-NEXT:    movb $43, -128(%rsp)
+; CHECK-NEXT:    movabsq $8589934462, %rax # imm = 0x1FFFFFF7E
 ; CHECK-NEXT:    addq %rax, %rsp
 ; CHECK-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-NEXT:    retq
-  %large1 = alloca %large, align 1
-  %large2 = alloca %large, align 1
-  %ptrLarge1 = getelementptr inbounds %large, ptr %large1, i64 0, i64 0
-  store i8 42, ptr %ptrLarge1, align 1
-  %ptrLarge2 = getelementptr inbounds %large, ptr %large2, i64 0, i64 0
-  store i8 43, ptr %ptrLarge2, align 1
+  %1 = alloca %large, align 1
+  %2 = alloca %large, align 1
+  %3 = getelementptr inbounds %large, ptr %1, i64 0, i64 0
+  store i8 42, ptr %3, align 1
+  %4 = getelementptr inbounds %large, ptr %2, i64 0, i64 0
+  store i8 43, ptr %4, align 1
   ret void
 }
-
-declare ptr @baz(ptr, ptr, ptr, ptr)
-
-define ptr @scavenge_spill() unnamed_addr #0 {
-; CHECK-LABEL: scavenge_spill:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    movabsq $25769803816, %rax # imm = 0x600000028
-; CHECK-NEXT:    subq %rax, %rsp
-; CHECK-NEXT:    .cfi_def_cfa_offset 25769803824
-; CHECK-NEXT:    movabsq $21474836521, %rax # imm = 0x500000029
-; CHECK-NEXT:    leaq (%rsp,%rax), %rdi
-; CHECK-NEXT:    movabsq $17179869226, %rax # imm = 0x40000002A
-; CHECK-NEXT:    leaq (%rsp,%rax), %rsi
-; CHECK-NEXT:    movq %rsi, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    movabsq $12884901931, %rax # imm = 0x30000002B
-; CHECK-NEXT:    leaq (%rsp,%rax), %rdx
-; CHECK-NEXT:    movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    movabsq $8589934636, %rax # imm = 0x20000002C
-; CHECK-NEXT:    leaq (%rsp,%rax), %rcx
-; CHECK-NEXT:    movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    callq baz@PLT
-; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rsi # 8-byte Reload
-; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload
-; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rcx # 8-byte Reload
-; CHECK-NEXT:    movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill
-; CHECK-NEXT:    leaq 46(%rsp), %rdi
-; CHECK-NEXT:    callq baz@PLT
-; CHECK-NEXT:    # kill: def $rcx killed $rax
-; CHECK-NEXT:    movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload
-; CHECK-NEXT:    movabsq $25769803816, %rcx # imm = 0x600000028
-; CHECK-NEXT:    addq %rcx, %rsp
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:    retq
-  %large1 = alloca %large, align 1
-  %ptrLarge1 = getelementptr inbounds %large, ptr %large1, i64 0, i64 0
-  %large2 = alloca %large, align 1
-  %ptrLarge2 = getelementptr inbounds %large, ptr %large2, i64 0, i64 0
-  %large3 = alloca %large, align 1
-  %ptrLarge3 = getelementptr inbounds %large, ptr %large3, i64 0, i64 0
-  %large4 = alloca %large, align 1
-  %ptrLarge4 = getelementptr inbounds %large, ptr %large4, i64 0, i64 0
-  %large5 = alloca %large, align 1
-  %ptrLarge5 = getelementptr inbounds %large, ptr %large5, i64 0, i64 0
-  %ret1 = call ptr @baz(ptr %ptrLarge1, ptr %ptrLarge2, ptr %ptrLarge3, ptr %ptrLarge4)
-  %large6 = alloca %large, align 1
-  %ptrLarge6 = getelementptr inbounds %large, ptr %large6, i64 0, i64 0
-  %ret2 = call ptr @baz(ptr %ptrLarge6, ptr %ptrLarge2, ptr %ptrLarge3, ptr %ptrLarge4)
-  ret ptr %ret1
-}
diff --git a/llvm/test/CodeGen/X86/large-displacements-fastisel.ll b/llvm/test/CodeGen/X86/large-displacements-fastisel.ll
diff --git a/llvm/test/CodeGen/X86/large-displacements.ll b/llvm/test/CodeGen/X86/large-displacements.ll
diff --git a/llvm/test/CodeGen/X86/merge-huge-sp-updates.ll b/llvm/test/CodeGen/X86/merge-huge-sp-updates.ll
@@ -22,8 +22,8 @@ entry:
   call void @bar(i64 0, i64 0, i64 0, i64 0, i64 0, ptr null, ptr %rhs, ptr null, ptr %rhs)
 ; CHECK: call{{.*}}bar
 ; CHECK: addq{{.*}}$2147483647, %rsp
-; CHECK: addq{{.*}}$372037601, %rsp
-; CHECK: .cfi_adjust_cfa_offset -2519521248
+; CHECK: addq{{.*}}$372037585, %rsp
+; CHECK: .cfi_adjust_cfa_offset -2519521232
   ret void
 }
 

diff --git a/llvm/test/CodeGen/X86/stack-clash-extra-huge.ll b/llvm/test/CodeGen/X86/stack-clash-extra-huge.ll
@@ -16,35 +16,35 @@ define i32 @foo() local_unnamed_addr #0 {
 ; CHECK-X64-NEXT:    cmpq %r11, %rsp
 ; CHECK-X64-NEXT:    jne .LBB0_1
 ; CHECK-X64-NEXT:  # %bb.2:
-; CHECK-X64-NEXT:    subq $3992, %rsp # imm = 0xF98
+; CHECK-X64-NEXT:    subq $3976, %rsp # imm = 0xF88
 ; CHECK-X64-NEXT:    .cfi_def_cfa_register %rsp
-; CHECK-X64-NEXT:    .cfi_def_cfa_offset 4799999904
-; CHECK-X64-NEXT:    movl $1, 280(%rsp)
-; CHECK-X64-NEXT:    movl $1, 28680(%rsp)
-; CHECK-X64-NEXT:    movl -112(%rsp), %eax
-; CHECK-X64-NEXT:    movabsq $4799999896, %rcx # imm = 0x11E1A2F98
+; CHECK-X64-NEXT:    .cfi_def_cfa_offset 4799999888
+; CHECK-X64-NEXT:    movl $1, 264(%rsp)
+; CHECK-X64-NEXT:    movl $1, 28664(%rsp)
+; CHECK-X64-NEXT:    movl -128(%rsp), %eax
+; CHECK-X64-NEXT:    movabsq $4799999880, %rcx # imm = 0x11E1A2F88
 ; CHECK-X64-NEXT:    addq %rcx, %rsp
 ; CHECK-X64-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-X64-NEXT:    retq
 ;
 ; CHECK-X86-LABEL: foo:
 ; CHECK-X86:       # %bb.0:
 ; CHECK-X86-NEXT:    ud2
-; CHECK-X86-NEXT:    .cfi_def_cfa_offset 4800000032
-; CHECK-X86-NEXT:    movl $1, 408(%esp)
-; CHECK-X86-NEXT:    movl $1, 28808(%esp)
-; CHECK-X86-NEXT:    movl 16(%esp), %eax
+; CHECK-X86-NEXT:    .cfi_def_cfa_offset 4800000016
+; CHECK-X86-NEXT:    movl $1, 392(%esp)
+; CHECK-X86-NEXT:    movl $1, 28792(%esp)
+; CHECK-X86-NEXT:    movl (%esp), %eax
 ; CHECK-X86-NEXT:    ud2
 ; CHECK-X86-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-X86-NEXT:    retl
 ;
 ; CHECK-X32-LABEL: foo:
 ; CHECK-X32:       # %bb.0:
 ; CHECK-X32-NEXT:    ud2
-; CHECK-X32-NEXT:    .cfi_def_cfa_offset 4799999904
-; CHECK-X32-NEXT:    movl $1, 280(%esp)
-; CHECK-X32-NEXT:    movl $1, 28680(%esp)
-; CHECK-X32-NEXT:    movl -112(%esp), %eax
+; CHECK-X32-NEXT:    .cfi_def_cfa_offset 4799999888
+; CHECK-X32-NEXT:    movl $1, 264(%esp)
+; CHECK-X32-NEXT:    movl $1, 28664(%esp)
+; CHECK-X32-NEXT:    movl -128(%esp), %eax
 ; CHECK-X32-NEXT:    ud2
 ; CHECK-X32-NEXT:    .cfi_def_cfa_offset 8
 ; CHECK-X32-NEXT:    retq