[GlobalISel] Add computeNumSignBits for SHL #152067
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-aarch64 Author: Yi-Chi Lee (yichi170) ChangesThis patch ports the Related to #150515. Full diff: https://github.com/llvm/llvm-project/pull/152067.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 974fc40de6222..b27aa475e13d4 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -1892,6 +1892,38 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
FirstAnswer = std::min<uint64_t>(FirstAnswer + *C, TyBits);
break;
}
+ case TargetOpcode::G_SHL: {
+ Register Src1 = MI.getOperand(1).getReg();
+ Register Src2 = MI.getOperand(2).getReg();
+ if (std::optional<ConstantRange> ShAmtRange =
+ getValidShiftAmountRange(Src2, DemandedElts, Depth + 1)) {
+ uint64_t MaxShAmt = ShAmtRange->getUnsignedMax().getZExtValue();
+ uint64_t MinShAmt = ShAmtRange->getUnsignedMin().getZExtValue();
+
+ MachineInstr &ExtMI = *MRI.getVRegDef(Src1);
+ unsigned ExtOpc = ExtMI.getOpcode();
+
+ if (ExtOpc == TargetOpcode::G_SEXT || ExtOpc == TargetOpcode::G_ZEXT ||
+ ExtOpc == TargetOpcode::G_ANYEXT) {
+ LLT ExtTy = MRI.getType(Src1);
+ Register Extendee = ExtMI.getOperand(1).getReg();
+ LLT ExtendeeTy = MRI.getType(Extendee);
+ uint64_t SizeDiff =
+ ExtTy.getScalarSizeInBits() - ExtendeeTy.getScalarSizeInBits();
+
+ if (SizeDiff <= MinShAmt) {
+ unsigned Tmp =
+ SizeDiff + computeNumSignBits(Extendee, DemandedElts, Depth + 1);
+ if (MaxShAmt < Tmp)
+ return Tmp - MaxShAmt;
+ }
+ }
+ unsigned Tmp = computeNumSignBits(Src1, DemandedElts, Depth + 1);
+ if (MaxShAmt < Tmp)
+ return Tmp - MaxShAmt;
+ }
+ break;
+ }
case TargetOpcode::G_TRUNC: {
Register Src = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(Src);
@@ -2051,6 +2083,7 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
// Okay, we know that the sign bit in Mask is set. Use CLO to determine
// the number of identical bits in the top of the input value.
Mask <<= Mask.getBitWidth() - TyBits;
+ LLVM_DEBUG(dbgs() << "Mask.countl_one(): " << Mask.countl_one() << "\n");
return std::max(FirstAnswer, Mask.countl_one());
}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
new file mode 100644
index 0000000000000..9e9c1413259fa
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-shl.mir
@@ -0,0 +1,110 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple aarch64 -passes="print<gisel-value-tracking>" %s -o - 2>&1 | FileCheck %s
+
+---
+name: Cst
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @Cst
+ ; CHECK-NEXT: %0:_ KnownBits:11100000 SignBits:3
+ ; CHECK-NEXT: %1:_ KnownBits:00000010 SignBits:6
+ ; CHECK-NEXT: %2:_ KnownBits:10000000 SignBits:1
+ %0:_(s8) = G_CONSTANT i8 224
+ %1:_(s8) = G_CONSTANT i8 2
+ %2:_(s8) = G_SHL %0, %1
+...
+---
+name: CstBig
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @CstBig
+ ; CHECK-NEXT: %0:_ KnownBits:11111001 SignBits:5
+ ; CHECK-NEXT: %1:_ KnownBits:00000110 SignBits:5
+ ; CHECK-NEXT: %2:_ KnownBits:01000000 SignBits:1
+ %0:_(s8) = G_CONSTANT i8 249
+ %1:_(s8) = G_CONSTANT i8 6
+ %2:_(s8) = G_SHL %0, %1
+...
+---
+name: ScalarVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = COPY $b1
+ %2:_(s8) = G_SHL %0, %1
+...
+---
+name: ScalarCst
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @ScalarCst
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000011 SignBits:6
+ ; CHECK-NEXT: %2:_ KnownBits:?????000 SignBits:1
+ %0:_(s8) = COPY $b0
+ %1:_(s8) = G_CONSTANT i8 3
+ %2:_(s8) = G_SHL %0, %1
+...
+---
+name: VectorVar
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorVar
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:???????????????? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(<4 x s16>) = COPY $d1
+ %2:_(<4 x s16>) = G_SHL %0, %1
+...
+---
+name: VectorCst
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:?????????????000 SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %1:_(s16) = G_CONSTANT i16 3
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %1, %1, %1, %1
+ %3:_(<4 x s16>) = G_SHL %0, %2
+...
+---
+name: VectorCst36
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst36
+ ; CHECK-NEXT: %0:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %1:_ KnownBits:0000000000000110 SignBits:13
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %3:_ KnownBits:0000000000000?1? SignBits:13
+ ; CHECK-NEXT: %4:_ KnownBits:000000????????00 SignBits:7
+ %0:_(s16) = G_CONSTANT i16 3
+ %1:_(s16) = G_CONSTANT i16 6
+ %2:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %0, %1, %1, %0
+ %4:_(<4 x s16>) = G_SHL %2, %3
+...
+
+---
+name: VectorCst3unknown
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @VectorCst3unknown
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
+ ; CHECK-NEXT: %3:_ KnownBits:???????????????? SignBits:1
+ ; CHECK-NEXT: %4:_ KnownBits:???????????????? SignBits:1
+ %0:_(<4 x s16>) = COPY $d0
+ %2:_(s16) = COPY $h0
+ %1:_(s16) = G_CONSTANT i16 3
+ %3:_(<4 x s16>) = G_BUILD_VECTOR %1, %2, %2, %1
+ %4:_(<4 x s16>) = G_SHL %0, %3
+...
|
davemgreen
reviewed
Aug 5, 2025
davemgreen
reviewed
Aug 10, 2025
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davemgreen
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davemgreen
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The tests Look good - can we add these as some simple additions for when more sign bits are now know (and some edge cases).
---
name: SHLless
body: |
bb.1:
; CHECK-LABEL: name: @SHLless
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
; CHECK-NEXT: %2:_ KnownBits:0000000000000011 SignBits:14
; CHECK-NEXT: %3:_ KnownBits:?????????????000 SignBits:6
%0:_(s8) = COPY $b0
%1:_(s16) = G_SEXT %0(s8)
%2:_(s16) = G_CONSTANT i16 3
%3:_(s16) = G_SHL %1, %2
...
---
name: SHLeq
body: |
bb.1:
; CHECK-LABEL: name: @SHLeq
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
; CHECK-NEXT: %2:_ KnownBits:0000000000001000 SignBits:12
; CHECK-NEXT: %3:_ KnownBits:????????00000000 SignBits:1
%0:_(s8) = COPY $b0
%1:_(s16) = G_SEXT %0(s8)
%2:_(s16) = G_CONSTANT i16 8
%3:_(s16) = G_SHL %1, %2
...
---
name: SHLmore
body: |
bb.1:
; CHECK-LABEL: name: @SHLmore
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:???????????????? SignBits:9
; CHECK-NEXT: %2:_ KnownBits:0000000000001101 SignBits:12
; CHECK-NEXT: %3:_ KnownBits:???0000000000000 SignBits:1
%0:_(s8) = COPY $b0
%1:_(s16) = G_SEXT %0(s8)
%2:_(s16) = G_CONSTANT i16 13
%3:_(s16) = G_SHL %1, %2
...
---
name: SignBitsThroughZext
body: |
bb.1:
; CHECK-LABEL: name: @SignBitsThroughZext
; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1
; CHECK-NEXT: %1:_ KnownBits:0000000000000011 SignBits:14
; CHECK-NEXT: %2:_ KnownBits:???????? SignBits:4
; CHECK-NEXT: %3:_ KnownBits:00000000???????? SignBits:8
; CHECK-NEXT: %4:_ KnownBits:0000000000001000 SignBits:12
; CHECK-NEXT: %5:_ KnownBits:????????00000000 SignBits:4
%0:_(s8) = COPY $b0
%1:_(s16) = G_CONSTANT i16 3
%2:_(s8) = G_ASHR %0, %1
%3:_(s16) = G_ZEXT %2
%4:_(s16) = G_CONSTANT i16 8
%5:_(s16) = G_SHL %3, %4
...
Otherwise this LGTM - thanks.
Collaborator
|
@yichi170 did you get a chance to add a few extra test cases? This looked good to me otherwise and would be good to get it in. |
Contributor
Author
|
@davemgreen Sorry for the late reply. I didn't notice your message about the additional tests. Will start working on it. |
Contributor
Author
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@davemgreen I updated the test! Let me know if there is anything that needs to be added. |
davemgreen
approved these changes
Sep 10, 2025
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davemgreen
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Sorry I missed the update! LGTM, thanks for adding the tests.
Are you happy for us to hit submit?
Contributor
Author
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Yes, I don't have the permission to merge the PR. Thank you so much! |
Collaborator
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/181/builds/27670 Here is the relevant piece of the build log for the reference |
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This patch ports the
ISD::SHLhandling from SelectionDAG’sComputeNumSignBitsto GlobalISel.Related to #150515.