Skip to content

[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have sufficient leading zero/sign bits #152273

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 12 commits into from
Aug 18, 2025
+87 −0
Merged

[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have sufficient leading zero/sign bits #152273

Show file tree
Hide file tree
Changes from 10 commits
Commits
Show all changes
12 commits
Select commit Hold shift + click to select a range
80e303c
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 6, 2025
24287f7
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 7, 2025
c8cc2a9
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 8, 2025
1115256
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 8, 2025
08138a2
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 8, 2025
728b37d
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 8, 2025
44609a3
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 9, 2025
2d268fc
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 16, 2025
32041fb
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 16, 2025
4e1af14
Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have suffici…
houngkoungting Aug 17, 2025
c4ea7bd
[DAG] Fold trunc(avg(x,y)) for avgceil/floor u/s nodes if they have s…
houngkoungting Aug 18, 2025
6f84361
Merge branch 'main' into main
RKSimon Aug 18, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
37 changes: 37 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16294,6 +16294,43 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
// because targets may prefer a wider type during later combines and invert
// this transform.
switch (N0.getOpcode()) {
case ISD::AVGCEILU:
case ISD::AVGFLOORU:
if (!LegalOperations && N0.hasOneUse() &&
TLI.isOperationLegal(N0.getOpcode(), VT)) {
SDValue X = N0.getOperand(0);
SDValue Y = N0.getOperand(1);
unsigned SrcBits = X.getScalarValueSizeInBits();
unsigned DstBits = VT.getScalarSizeInBits();
KnownBits KnownX = DAG.computeKnownBits(X);
KnownBits KnownY = DAG.computeKnownBits(Y);
Copy link
Contributor

@jayfoad jayfoad Aug 18, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

computeKnownBits can be expensive. You should rearrange this code so that you only call computeKnownBits(Y) if the test on the result of computeKnownBits(X) succeeds.

if (KnownX.countMinLeadingZeros() >= (SrcBits - DstBits) &&
KnownY.countMinLeadingZeros() >= (SrcBits - DstBits)) {
Copy link
Contributor

@jayfoad jayfoad Aug 18, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Suggested change
if (KnownX.countMinLeadingZeros() >= (SrcBits - DstBits) &&
KnownY.countMinLeadingZeros() >= (SrcBits - DstBits)) {
if (KnownX.countMaxActiveBits() <= DstBits &&
KnownY.countMaxActiveBits() <= DstBits) {

Then you don't need SrcBits.

Copy link
Collaborator

@RKSimon RKSimon Aug 18, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

You could even do this:

APInt UpperBits = APInt::getHighBitsSet(SrcBits, SrcBits - DstBits);
if (DAG.MaskedValueIsZero(X, UpperBits) &&
    DAG.MaskedValueIsZero(Y, UpperBits)) {

Copy link
Contributor

@jayfoad jayfoad Aug 18, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Or APInt::getBitsSetFrom(SrcBits, DstBits). (Sometimes I think we have too many different helper functions!)

SDValue Tx = DAG.getNode(ISD::TRUNCATE, DL, VT, X);
Copy link
Collaborator

@RKSimon RKSimon Aug 6, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

NeededLeadingZeros = SrcBits - DstBits; ? (NeededSignBits is correct though you could use ComputeMaxSignificantBits instead if you wish)

Copy link
Collaborator

@RKSimon RKSimon Aug 7, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Sorry I think you misunderstood - you need to use computeKnownBits.countMinLeadingZeros() >= (SrcBits - DstBits)

SDValue Ty = DAG.getNode(ISD::TRUNCATE, DL, VT, Y);
return DAG.getNode(N0.getOpcode(), DL, VT, Tx, Ty);
}
}
break;
case ISD::AVGCEILS:
case ISD::AVGFLOORS:
if (!LegalOperations && N0.hasOneUse() &&
TLI.isOperationLegal(N0.getOpcode(), VT)) {
SDValue X = N0.getOperand(0);
SDValue Y = N0.getOperand(1);
unsigned SignBitsX = DAG.ComputeNumSignBits(X);
unsigned SignBitsY = DAG.ComputeNumSignBits(Y);
unsigned SrcBits = X.getScalarValueSizeInBits();
unsigned DstBits = VT.getScalarSizeInBits();
unsigned NeededSignBits = SrcBits - DstBits + 1;

if (SignBitsX >= NeededSignBits && SignBitsY >= NeededSignBits) {
Copy link
Collaborator

@RKSimon RKSimon Aug 18, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more. 

 if (DAG.ComputeNumSignBits(X) >= NeededSignBits &&
     DAG.ComputeNumSignBits(Y) >= NeededSignBits) {

SDValue Tx = DAG.getNode(ISD::TRUNCATE, DL, VT, X);
SDValue Ty = DAG.getNode(ISD::TRUNCATE, DL, VT, Y);
return DAG.getNode(N0.getOpcode(), DL, VT, Tx, Ty);
}
}
break;
Copy link
Collaborator

@RKSimon RKSimon Aug 12, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

You should be able to reuse the ISD::ABD code later in the switch statement now - its has near-identical logic

case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
Expand Down
53 changes: 53 additions & 0 deletions llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,53 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-- -O2 -mattr=+neon < %s | FileCheck %s

define <8 x i8> @avgceil_u_i8_to_i16(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: avgceil_u_i8_to_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: urhadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
%a16 = zext <8 x i8> %a to <8 x i16>
%b16 = zext <8 x i8> %b to <8 x i16>
%avg16 = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %a16, <8 x i16> %b16)
%r = trunc <8 x i16> %avg16 to <8 x i8>
ret <8 x i8> %r
}


define <8 x i8> @test_avgceil_s(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: test_avgceil_s:
; CHECK: // %bb.0:
; CHECK-NEXT: srhadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
%a16 = sext <8 x i8> %a to <8 x i16>
%b16 = sext <8 x i8> %b to <8 x i16>
%avg16 = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %a16, <8 x i16> %b16)
%res = trunc <8 x i16> %avg16 to <8 x i8>
ret <8 x i8> %res
}

define <8 x i8> @avgfloor_u_i8_to_i16(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: avgfloor_u_i8_to_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: uhadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
%a16 = zext <8 x i8> %a to <8 x i16>
%b16 = zext <8 x i8> %b to <8 x i16>
%avg16 = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %a16, <8 x i16> %b16)
%res = trunc <8 x i16> %avg16 to <8 x i8>
ret <8 x i8> %res
}

define <8 x i8> @test_avgfloor_s(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: test_avgfloor_s:
; CHECK: // %bb.0:
; CHECK-NEXT: shadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: ret
%a16 = sext <8 x i8> %a to <8 x i16>
%b16 = sext <8 x i8> %b to <8 x i16>
%avg16 = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %a16, <8 x i16> %b16)
%res = trunc <8 x i16> %avg16 to <8 x i8>
ret <8 x i8> %res
}