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45 changes: 45 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -16294,6 +16294,51 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
// because targets may prefer a wider type during later combines and invert
// this transform.
switch (N0.getOpcode()) {
case ISD::AVGCEILU:
case ISD::AVGFLOORU:
if (!LegalOperations && N0.hasOneUse() &&
TLI.isOperationLegal(N0.getOpcode(), VT)) {
SDValue X = N0.getOperand(0);
SDValue Y = N0.getOperand(1);

KnownBits KnownX = DAG.computeKnownBits(X);
KnownBits KnownY = DAG.computeKnownBits(Y);

unsigned SrcBits = X.getScalarValueSizeInBits();
unsigned DstBits = VT.getScalarSizeInBits();
unsigned NeededLeadingZeros = SrcBits - DstBits + 1;
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NeededLeadingZeros = SrcBits - DstBits; ? (NeededSignBits is correct though you could use ComputeMaxSignificantBits instead if you wish)

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Sorry I think you misunderstood - you need to use computeKnownBits.countMinLeadingZeros() >= (SrcBits - DstBits)


if (KnownX.countMinLeadingZeros() >= NeededLeadingZeros &&
KnownY.countMinLeadingZeros() >= NeededLeadingZeros) {
SDValue Tx = DAG.getNode(ISD::TRUNCATE, DL, VT, X);
SDValue Ty = DAG.getNode(ISD::TRUNCATE, DL, VT, Y);
return DAG.getNode(N0.getOpcode(), DL, VT, Tx, Ty);
}
}
break;

case ISD::AVGCEILS:
case ISD::AVGFLOORS:
if (!LegalOperations && N0.hasOneUse() &&
TLI.isOperationLegal(N0.getOpcode(), VT)) {
SDValue X = N0.getOperand(0);
SDValue Y = N0.getOperand(1);

unsigned SignBitsX = DAG.ComputeNumSignBits(X);
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 if (DAG.ComputeNumSignBits(X) >= NeededSignBits &&
     DAG.ComputeNumSignBits(Y) >= NeededSignBits) {

unsigned SignBitsY = DAG.ComputeNumSignBits(Y);

unsigned SrcBits = X.getScalarValueSizeInBits();
unsigned DstBits = VT.getScalarSizeInBits();
unsigned NeededSignBits = SrcBits - DstBits + 1;

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You should be able to reuse the ISD::ABD code later in the switch statement now - its has near-identical logic

if (SignBitsX >= NeededSignBits && SignBitsY >= NeededSignBits) {
SDValue Tx = DAG.getNode(ISD::TRUNCATE, DL, VT, X);
SDValue Ty = DAG.getNode(ISD::TRUNCATE, DL, VT, Y);
return DAG.getNode(N0.getOpcode(), DL, VT, Tx, Ty);
}
}
break;

case ISD::ADD:
case ISD::SUB:
case ISD::MUL:
Expand Down
43 changes: 43 additions & 0 deletions llvm/test/CodeGen/AArch64/trunc-avg-fold.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
; RUN: llc -mtriple=aarch64-- -O2 -mattr=+neon < %s | FileCheck %s

; CHECK-LABEL: test_avgceil_u
; CHECK: uhadd v0.8b, v0.8b, v1.8b
define <8 x i8> @test_avgceil_u(<8 x i16> %a, <8 x i16> %b) {
%ta = trunc <8 x i16> %a to <8 x i8>
%tb = trunc <8 x i16> %b to <8 x i8>
%res = call <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8> %ta, <8 x i8> %tb)
ret <8 x i8> %res
}

; CHECK-LABEL: test_avgceil_s
; CHECK: shadd v0.8b, v0.8b, v1.8b
define <8 x i8> @test_avgceil_s(<8 x i16> %a, <8 x i16> %b) {
%ta = trunc <8 x i16> %a to <8 x i8>
%tb = trunc <8 x i16> %b to <8 x i8>
%res = call <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8> %ta, <8 x i8> %tb)
ret <8 x i8> %res
}

; CHECK-LABEL: test_avgfloor_u
; CHECK: urhadd v0.8b, v0.8b, v1.8b
define <8 x i8> @test_avgfloor_u(<8 x i16> %a, <8 x i16> %b) {
%ta = trunc <8 x i16> %a to <8 x i8>
%tb = trunc <8 x i16> %b to <8 x i8>
%res = call <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8> %ta, <8 x i8> %tb)
ret <8 x i8> %res
}

; CHECK-LABEL: test_avgfloor_s
; CHECK: srhadd v0.8b, v0.8b, v1.8b
define <8 x i8> @test_avgfloor_s(<8 x i16> %a, <8 x i16> %b) {
%ta = trunc <8 x i16> %a to <8 x i8>
%tb = trunc <8 x i16> %b to <8 x i8>
%res = call <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8> %ta, <8 x i8> %tb)
ret <8 x i8> %res
}

declare <8 x i8> @llvm.aarch64.neon.uhadd.v8i8(<8 x i8>, <8 x i8>)
declare <8 x i8> @llvm.aarch64.neon.shadd.v8i8(<8 x i8>, <8 x i8>)
declare <8 x i8> @llvm.aarch64.neon.urhadd.v8i8(<8 x i8>, <8 x i8>)
declare <8 x i8> @llvm.aarch64.neon.srhadd.v8i8(<8 x i8>, <8 x i8>)