From 611c67f3cf72882f364abd325c5c1b2ec738bdc6 Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Wed, 6 Aug 2025 13:15:43 -0700 Subject: [PATCH] [AMDGPU] Add XNACK_STATE_PRIV and _MASK gfx1250 registers Co-authored-by: Pierre Vanhoutryve --- llvm/lib/Target/AMDGPU/SIDefines.h | 4 +++ .../Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp | 4 +++ llvm/test/MC/AMDGPU/gfx1250_asm_operands.s | 25 +++++++++++++++++++ .../AMDGPU/gfx1250_dasm_operands.txt | 12 +++++++++ 4 files changed, 45 insertions(+) diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h index deadb7aed0f69..2d0102fffe5ea 100644 --- a/llvm/lib/Target/AMDGPU/SIDefines.h +++ b/llvm/lib/Target/AMDGPU/SIDefines.h @@ -536,6 +536,10 @@ enum Id { // HwRegCode, (6) [5:0] ID_SQ_PERF_SNAPSHOT_DATA1 = 22, ID_SQ_PERF_SNAPSHOT_PC_LO = 23, ID_SQ_PERF_SNAPSHOT_PC_HI = 24, + + // GFX1250 + ID_XNACK_STATE_PRIV = 33, + ID_XNACK_MASK_gfx1250 = 34, }; enum Offset : unsigned { // Offset, (5) [10:6] diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp index e433b85489e6e..3d9455fc51a39 100644 --- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp +++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp @@ -223,6 +223,10 @@ static constexpr CustomOperand Operands[] = { {{"HW_REG_SQ_PERF_SNAPSHOT_PC_LO"}, ID_SQ_PERF_SNAPSHOT_PC_LO, isGFX940}, {{"HW_REG_SQ_PERF_SNAPSHOT_PC_HI"}, ID_SQ_PERF_SNAPSHOT_PC_HI, isGFX940}, + // GFX1250 + {{"HW_REG_XNACK_STATE_PRIV"}, ID_XNACK_STATE_PRIV, isGFX1250}, + {{"HW_REG_XNACK_MASK"}, ID_XNACK_MASK_gfx1250, isGFX1250}, + // Aliases {{"HW_REG_HW_ID"}, ID_HW_ID1, isGFX10}, }; diff --git a/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s b/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s index 8b7465b5df574..100fc981c4f81 100644 --- a/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s +++ b/llvm/test/MC/AMDGPU/gfx1250_asm_operands.s @@ -27,3 +27,28 @@ s_mov_b64 s[0:1], src_shared_limit s_getreg_b32 s1, hwreg(33) // GFX1250: encoding: [0x21,0xf8,0x81,0xb8] + +s_getreg_b32 s1, hwreg(HW_REG_XNACK_STATE_PRIV) +// GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU +// GFX1250: encoding: [0x21,0xf8,0x81,0xb8] + +s_getreg_b32 s1, hwreg(34) +// GFX1250: encoding: [0x22,0xf8,0x81,0xb8] + +s_getreg_b32 s1, hwreg(HW_REG_XNACK_MASK) +// GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU +// GFX1250: encoding: [0x22,0xf8,0x81,0xb8] + +s_setreg_b32 hwreg(33), s1 +// GFX1250: encoding: [0x21,0xf8,0x01,0xb9] + +s_setreg_b32 hwreg(HW_REG_XNACK_STATE_PRIV), s1 +// GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU +// GFX1250: encoding: [0x21,0xf8,0x01,0xb9] + +s_setreg_b32 hwreg(34), s1 +// GFX1250: encoding: [0x22,0xf8,0x01,0xb9] + +s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s1 +// GFX1200-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid hardware register: not supported on this GPU +// GFX1250: encoding: [0x22,0xf8,0x01,0xb9] diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt index a3e7e570ab9b6..d72009bc017f4 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_dasm_operands.txt @@ -20,3 +20,15 @@ # GFX1250: s_mov_b64 s[0:1], src_shared_limit ; encoding: [0xec,0x01,0x80,0xbe] 0xec,0x01,0x80,0xbe + +# GFX1250: s_getreg_b32 s1, hwreg(HW_REG_XNACK_STATE_PRIV) ; encoding: [0x21,0xf8,0x81,0xb8] +0x21,0xf8,0x81,0xb8 + +# GFX1250: s_getreg_b32 s1, hwreg(HW_REG_XNACK_MASK) ; encoding: [0x22,0xf8,0x81,0xb8] +0x22,0xf8,0x81,0xb8 + +# GFX1250: s_setreg_b32 hwreg(HW_REG_XNACK_STATE_PRIV), s1 ; encoding: [0x21,0xf8,0x01,0xb9] +0x21,0xf8,0x01,0xb9 + +# GFX1250: s_setreg_b32 hwreg(HW_REG_XNACK_MASK), s1 ; encoding: [0x22,0xf8,0x01,0xb9] +0x22,0xf8,0x01,0xb9