From efeb4ae30a18e0c6b3783f3186a59ae1dcd3dc03 Mon Sep 17 00:00:00 2001 From: XChy Date: Fri, 8 Aug 2025 04:15:08 +0800 Subject: [PATCH 1/2] [SelectionDAGBuilder] Look for appropriate INLINEASM_BR instruction to verify --- .../SelectionDAG/SelectionDAGBuilder.cpp | 13 +++-- llvm/test/CodeGen/X86/callbr-asm-loop.ll | 50 +++++++++++++++++++ 2 files changed, 59 insertions(+), 4 deletions(-) create mode 100644 llvm/test/CodeGen/X86/callbr-asm-loop.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index d0815e9f51822..f096148f865cb 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -12737,17 +12737,22 @@ static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg) { assert(MI->getOpcode() == TargetOpcode::COPY && "start of copy chain MUST be COPY"); Reg = MI->getOperand(1).getReg(); + + // If the copied register in the first copy must be virtual. + assert(Reg.isVirtual() && "expected COPY of virtual register"); MI = MRI.def_begin(Reg)->getParent(); + // There may be an optional second copy. if (MI->getOpcode() == TargetOpcode::COPY) { assert(Reg.isVirtual() && "expected COPY of virtual register"); Reg = MI->getOperand(1).getReg(); assert(Reg.isPhysical() && "expected COPY of physical register"); - MI = MRI.def_begin(Reg)->getParent(); + } else { + // The start of the chain must be an INLINEASM_BR. + assert(MI->getOpcode() == TargetOpcode::INLINEASM_BR && + "end of copy chain MUST be INLINEASM_BR"); } - // The start of the chain must be an INLINEASM_BR. - assert(MI->getOpcode() == TargetOpcode::INLINEASM_BR && - "end of copy chain MUST be INLINEASM_BR"); + return Reg; } diff --git a/llvm/test/CodeGen/X86/callbr-asm-loop.ll b/llvm/test/CodeGen/X86/callbr-asm-loop.ll new file mode 100644 index 0000000000000..83affd7e86097 --- /dev/null +++ b/llvm/test/CodeGen/X86/callbr-asm-loop.ll @@ -0,0 +1,50 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 + +; RUN: llc -O0 -mtriple=i686-- < %s | FileCheck %s + +; Test that causes multiple defs of %eax. +; FIXME: The testcase hangs with -O1/2/3 enabled. +define i32 @loop1() { +; CHECK-LABEL: loop1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: pushl %esi +; CHECK-NEXT: .cfi_def_cfa_offset 8 +; CHECK-NEXT: .cfi_offset %esi, -8 +; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: .LBB0_1: # %tailrecurse +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: movl $1, %edx +; CHECK-NEXT: #APP +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: movl %eax, %ecx +; CHECK-NEXT: movl %edx, %esi +; CHECK-NEXT: jmp .LBB0_3 +; CHECK-NEXT: .LBB0_2: # Inline asm indirect target +; CHECK-NEXT: # %tailrecurse.tailrecurse.backedge_crit_edge +; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: # Label of block must be emitted +; CHECK-NEXT: .LBB0_3: # %tailrecurse.backedge +; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 +; CHECK-NEXT: jmp .LBB0_1 +; CHECK-NEXT: .LBB0_4: # Inline asm indirect target +; CHECK-NEXT: # %lab2.split +; CHECK-NEXT: # Label of block must be emitted +; CHECK-NEXT: movl %edx, %eax +; CHECK-NEXT: popl %esi +; CHECK-NEXT: .cfi_def_cfa_offset 4 +; CHECK-NEXT: retl +entry: + br label %tailrecurse + +tailrecurse: + %0 = callbr { i32, i32 } asm "", "={ax},={dx},0,1,!i,!i"(i32 0, i32 1) #1 + to label %tailrecurse.backedge [label %tailrecurse.backedge, label %lab2.split] + +tailrecurse.backedge: + br label %tailrecurse + +lab2.split: + %asmresult5 = extractvalue { i32, i32 } %0, 1 + ret i32 %asmresult5 +} From adb984c0d45b70d3d2e2597143b940f7a13766ff Mon Sep 17 00:00:00 2001 From: XChy Date: Tue, 12 Aug 2025 20:07:21 +0800 Subject: [PATCH 2/2] add nounwind --- llvm/test/CodeGen/X86/callbr-asm-loop.ll | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/X86/callbr-asm-loop.ll b/llvm/test/CodeGen/X86/callbr-asm-loop.ll index 83affd7e86097..999b04c4f4838 100644 --- a/llvm/test/CodeGen/X86/callbr-asm-loop.ll +++ b/llvm/test/CodeGen/X86/callbr-asm-loop.ll @@ -4,12 +4,10 @@ ; Test that causes multiple defs of %eax. ; FIXME: The testcase hangs with -O1/2/3 enabled. -define i32 @loop1() { +define i32 @loop1() nounwind { ; CHECK-LABEL: loop1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: pushl %esi -; CHECK-NEXT: .cfi_def_cfa_offset 8 -; CHECK-NEXT: .cfi_offset %esi, -8 ; CHECK-NEXT: jmp .LBB0_1 ; CHECK-NEXT: .LBB0_1: # %tailrecurse ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 @@ -32,7 +30,6 @@ define i32 @loop1() { ; CHECK-NEXT: # Label of block must be emitted ; CHECK-NEXT: movl %edx, %eax ; CHECK-NEXT: popl %esi -; CHECK-NEXT: .cfi_def_cfa_offset 4 ; CHECK-NEXT: retl entry: br label %tailrecurse