From 48fee3b54c6c4a41824bb585956c5717a861942b Mon Sep 17 00:00:00 2001 From: "Mikhail R. Gadelha" Date: Tue, 12 Aug 2025 13:14:57 -0300 Subject: [PATCH 1/3] [RISCV][VLOPT] Added support for the zvbc and the remaining zvbb instructions Signed-off-by: Mikhail R. Gadelha --- llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 22 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll | 18 ++++++---------- 2 files changed, 28 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp index 28c8f401321fd..d5aad3aac77f8 100644 --- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp @@ -497,6 +497,10 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) { case RISCV::VANDN_VX: // Vector Reverse Bits in Elements case RISCV::VBREV_V: + // Vector Reverse Bytes in Bytes + case RISCV::VBREV8_V: + // Vector Reverse Bytes + case RISCV::VREV8_V: // Vector Count Leading Zeros case RISCV::VCLZ_V: // Vector Count Trailing Zeros @@ -510,6 +514,13 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) { case RISCV::VROR_VI: case RISCV::VROR_VV: case RISCV::VROR_VX: + // Vector Carry-less Multiplication Instructions (Zvbc) + // Vector Carry-less Multiply + case RISCV::VCLMUL_VV: + case RISCV::VCLMUL_VX: + // Vector Carry-less Multiply Return High Half + case RISCV::VCLMULH_VV: + case RISCV::VCLMULH_VX: return MILog2SEW; // Vector Widening Shift Left Logical (Zvbb) @@ -1046,6 +1057,10 @@ static bool isSupportedInstr(const MachineInstr &MI) { case RISCV::VANDN_VX: // Vector Reverse Bits in Elements case RISCV::VBREV_V: + // Vector Reverse Bytes in Bytes + case RISCV::VBREV8_V: + // Vector Reverse Bytes + case RISCV::VREV8_V: // Vector Count Leading Zeros case RISCV::VCLZ_V: // Vector Count Trailing Zeros @@ -1063,6 +1078,13 @@ static bool isSupportedInstr(const MachineInstr &MI) { case RISCV::VWSLL_VI: case RISCV::VWSLL_VX: case RISCV::VWSLL_VV: + // Vector Carry-less Multiplication Instructions (Zvbc) + // Vector Carry-less Multiply + case RISCV::VCLMUL_VV: + case RISCV::VCLMUL_VX: + // Vector Carry-less Multiply Return High Half + case RISCV::VCLMULH_VV: + case RISCV::VCLMULH_VX: // Vector Mask Instructions // Vector Mask-Register Logical Instructions // vmsbf.m set-before-first mask bit diff --git a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll index d91670214513c..e7baffd8bf8d5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll @@ -3438,9 +3438,8 @@ define @vbrev_v( %a, iXLen %vl) { define @vbrev8_v( %a, iXLen %vl) { ; CHECK-LABEL: vbrev8_v: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; CHECK-NEXT: vbrev8.v v10, v8 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; CHECK-NEXT: vbrev8.v v10, v8 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call @llvm.riscv.vbrev8.nxv4i32( undef, %a, iXLen -1) @@ -3451,9 +3450,8 @@ define @vbrev8_v( %a, iXLen %vl) { define @vrev8_v( %a, iXLen %vl) { ; CHECK-LABEL: vrev8_v: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma -; CHECK-NEXT: vrev8.v v10, v8 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma +; CHECK-NEXT: vrev8.v v10, v8 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call @llvm.riscv.vrev8.nxv4i32( undef, %a, iXLen -1) @@ -3560,9 +3558,8 @@ define @vrol_vx( %a, iXLen %b, iXLen %vl) { define @vclmul_vv( %a, %b, iXLen %vl) { ; CHECK-LABEL: vclmul_vv: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-NEXT: vclmul.vv v10, v8, v10 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma +; CHECK-NEXT: vclmul.vv v10, v8, v10 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call @llvm.riscv.vclmul.nxv2i64.nxv2i64( undef, %a, %b, iXLen -1) @@ -3573,9 +3570,8 @@ define @vclmul_vv( %a, % define @vclmul_vx( %a, i32 %b, iXLen %vl) { ; CHECK-LABEL: vclmul_vx: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, ma -; CHECK-NEXT: vclmul.vx v10, v8, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma +; CHECK-NEXT: vclmul.vx v10, v8, a0 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call @llvm.riscv.vclmul.nxv2i64.i32( undef, %a, i32 %b, iXLen -1) @@ -3586,9 +3582,8 @@ define @vclmul_vx( %a, i32 %b, iXLen %vl) { define @vclmulh_vv( %a, %b, iXLen %vl) { ; CHECK-LABEL: vclmulh_vv: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma -; CHECK-NEXT: vclmulh.vv v10, v8, v10 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma +; CHECK-NEXT: vclmulh.vv v10, v8, v10 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call @llvm.riscv.vclmulh.nxv2i64.nxv2i64( undef, %a, %b, iXLen -1) @@ -3599,9 +3594,8 @@ define @vclmulh_vv( %a, define @vclmulh_vx( %a, i32 %b, iXLen %vl) { ; CHECK-LABEL: vclmulh_vx: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a2, zero, e64, m2, ta, ma -; CHECK-NEXT: vclmulh.vx v10, v8, a0 ; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma +; CHECK-NEXT: vclmulh.vx v10, v8, a0 ; CHECK-NEXT: vadd.vv v8, v10, v8 ; CHECK-NEXT: ret %1 = call @llvm.riscv.vclmulh.nxv2i64.i32( undef, %a, i32 %b, iXLen -1) From fd0768408face785844c38e584fcbb33783d4cec Mon Sep 17 00:00:00 2001 From: "Mikhail R. Gadelha" Date: Wed, 13 Aug 2025 11:14:20 -0300 Subject: [PATCH 2/3] Update llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp Co-authored-by: Luke Lau --- llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp index d5aad3aac77f8..73308ee2f30e0 100644 --- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp @@ -497,7 +497,7 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) { case RISCV::VANDN_VX: // Vector Reverse Bits in Elements case RISCV::VBREV_V: - // Vector Reverse Bytes in Bytes + // Vector Reverse Bits in Bytes case RISCV::VBREV8_V: // Vector Reverse Bytes case RISCV::VREV8_V: From 653798e7109806465dfa1b89ac97e239043b67b1 Mon Sep 17 00:00:00 2001 From: "Mikhail R. Gadelha" Date: Wed, 13 Aug 2025 11:14:27 -0300 Subject: [PATCH 3/3] Update llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp Co-authored-by: Luke Lau --- llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp index 73308ee2f30e0..f013898e85203 100644 --- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp @@ -1057,7 +1057,7 @@ static bool isSupportedInstr(const MachineInstr &MI) { case RISCV::VANDN_VX: // Vector Reverse Bits in Elements case RISCV::VBREV_V: - // Vector Reverse Bytes in Bytes + // Vector Reverse Bits in Bytes case RISCV::VBREV8_V: // Vector Reverse Bytes case RISCV::VREV8_V: