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[PowerPC] Remove some unused SDNodes and FastISel workaround (NFC) #153964

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Merged
merged 1 commit into from
Aug 16, 2025
Merged

[PowerPC] Remove some unused SDNodes and FastISel workaround (NFC) #153964

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7 changes: 2 additions & 5 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1787,11 +1787,8 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
case PPCISD::PADDI_DTPREL:
return "PPCISD::PADDI_DTPREL";
case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
case PPCISD::SC: return "PPCISD::SC";
case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
case PPCISD::RFEBB: return "PPCISD::RFEBB";
case PPCISD::VADD_SPLAT:
return "PPCISD::VADD_SPLAT";
case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN";
case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128";
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14 changes: 0 additions & 14 deletions llvm/lib/Target/PowerPC/PPCISelLowering.h
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Expand Up @@ -430,20 +430,6 @@ namespace llvm {
/// optimizations due to constant folding.
VADD_SPLAT,

/// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
/// operand identifies the operating system entry point.
SC,

/// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
CLRBHRB,

/// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
/// history rolling buffer entry.
MFBHRBE,

/// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
RFEBB,

/// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
/// endian. Maps to an xxswapd instruction that corrects an lxvd2x
/// or stxvd2x instruction. The chain is necessary because the
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29 changes: 6 additions & 23 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.td
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Expand Up @@ -365,16 +365,6 @@ def PPCeh_sjlj_longjmp : SDNode<"PPCISD::EH_SJLJ_LONGJMP",
SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
[SDNPHasChain, SDNPSideEffect]>;

def SDT_PPCsc : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
def PPCsc : SDNode<"PPCISD::SC", SDT_PPCsc,
[SDNPHasChain, SDNPSideEffect]>;

def PPCclrbhrb : SDNode<"PPCISD::CLRBHRB", SDTNone,
[SDNPHasChain, SDNPSideEffect]>;
def PPCmfbhrbe : SDNode<"PPCISD::MFBHRBE", SDTIntBinOp, [SDNPHasChain]>;
def PPCrfebb : SDNode<"PPCISD::RFEBB", SDT_PPCsc,
[SDNPHasChain, SDNPSideEffect]>;

def PPCvcmp : SDNode<"PPCISD::VCMP" , SDT_PPCvcmp, []>;
def PPCvcmp_rec : SDNode<"PPCISD::VCMP_rec", SDT_PPCvcmp, [SDNPOutGlue]>;

Expand Down Expand Up @@ -1673,7 +1663,7 @@ let isBranch = 1, isTerminator = 1, Size = 0 in {
// System call.
let PPC970_Unit = 7 in {
def SC : SCForm<17, 1, 0, (outs), (ins i32imm:$LEV),
"sc $LEV", IIC_BrB, [(PPCsc (i32 imm:$LEV))]>;
"sc $LEV", IIC_BrB, []>;
}

// We mark SCV as having no scheduling model since it is only meant to be used
Expand All @@ -1685,21 +1675,14 @@ let Predicates = [IsISA3_0], hasNoSchedulingInfo = 1 in {
}

// Branch history rolling buffer.
def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB,
[(PPCclrbhrb)]>,
def CLRBHRB : XForm_0<31, 430, (outs), (ins), "clrbhrb", IIC_BrB, []>,
PPC970_DGroup_Single;
// The $dmy argument used for MFBHRBE is not needed; however, including
// it avoids automatic generation of PPCFastISel::fastEmit_i(), which
// interferes with necessary special handling (see PPCFastISel.cpp).
def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT),
(ins u10imm:$imm, u10imm:$dmy),
"mfbhrbe $RT, $imm", IIC_BrB,
[(set i32:$RT,
(PPCmfbhrbe imm:$imm, imm:$dmy))]>,

def MFBHRBE : XFXForm_3p<31, 302, (outs gprc:$RT), (ins u10imm:$imm),
"mfbhrbe $RT, $imm", IIC_BrB, []>,
PPC970_DGroup_First;

def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S",
IIC_BrB, [(PPCrfebb (i32 imm:$S))]>,
def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$S), "rfebb $S", IIC_BrB, []>,
PPC970_DGroup_Single;

def : InstAlias<"rfebb", (RFEBB 1)>;
Expand Down