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[RISCV] Add P-ext MC support for pli.dh, pli.db, and plui.dh. #153972

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Merged
merged 5 commits into from
Aug 18, 2025
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[RISCV] Add P-ext MC support for pli.dh, pli.db, and plui.dh. #153972

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7a053f3
[RISCV] Use simm8 instead of uimm8 for pli.b
topperc Aug 16, 2025
14f03a7
fixup! Accept [-128,255]
topperc Aug 16, 2025
63d3552
[RISCV] Add P-ext MC support for pli.dh, pli.db, and plui.dh.
topperc Aug 16, 2025
ebb0c29
Update llvm/lib/Target/RISCV/RISCVInstrInfoP.td
topperc Aug 18, 2025
e653187
Merge remote-tracking branch 'origin/main' into pr/pair-loadimm
topperc Aug 18, 2025
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12 changes: 12 additions & 0 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -903,6 +903,7 @@ struct RISCVOperand final : public MCParsedAsmOperand {
VK == RISCV::S_QC_ABS20;
}

bool isSImm8Unsigned() const { return isSImm<8>() || isUImm<8>(); }
bool isSImm10Unsigned() const { return isSImm<10>() || isUImm<10>(); }

bool isUImm20LUI() const {
Expand Down Expand Up @@ -1199,6 +1200,14 @@ struct RISCVOperand final : public MCParsedAsmOperand {
addExpr(Inst, getImm(), isRV64Imm());
}

void addSImm8UnsignedOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
int64_t Imm;
[[maybe_unused]] bool IsConstant = evaluateConstantImm(getImm(), Imm);
assert(IsConstant);
Inst.addOperand(MCOperand::createImm(SignExtend64<8>(Imm)));
}

void addSImm10UnsignedOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
int64_t Imm;
Expand Down Expand Up @@ -1547,6 +1556,9 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
return generateImmOutOfRangeError(
Operands, ErrorInfo, 0, (1 << 9) - 8,
"immediate must be a multiple of 8 bytes in the range");
case Match_InvalidSImm8Unsigned:
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 7),
(1 << 8) - 1);
case Match_InvalidSImm10:
return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 9),
(1 << 9) - 1);
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
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Expand Up @@ -346,6 +346,7 @@ enum OperandType : unsigned {
OPERAND_SIMM5_PLUS1,
OPERAND_SIMM6,
OPERAND_SIMM6_NONZERO,
OPERAND_SIMM8,
OPERAND_SIMM10,
OPERAND_SIMM10_LSB0000_NONZERO,
OPERAND_SIMM11,
Expand Down
130 changes: 97 additions & 33 deletions llvm/lib/Target/RISCV/RISCVInstrInfoP.td
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Expand Up @@ -18,7 +18,26 @@
// Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===//

def simm10 : RISCVSImmLeafOp<10>;
def simm10 : RISCVSImmOp<10>;

def SImm8UnsignedAsmOperand : SImmAsmOperand<8, "Unsigned"> {
let RenderMethod = "addSImm8UnsignedOperands";
}

// A 8-bit signed immediate allowing range [-128, 255]
// but represented as [-128, 255].
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@pfusik pfusik Sep 10, 2025

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What do you mean by "but" if the two ranges are identical?

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@topperc topperc Sep 10, 2025

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Looks like I reintroduced the issue Sam commented on here #153913 (comment)

def simm8_unsigned : RISCVOp {
let ParserMatchClass = SImm8UnsignedAsmOperand;
let EncoderMethod = "getImmOpValue";
let DecoderMethod = "decodeSImmOperand<8>";
let OperandType = "OPERAND_SIMM10";
let MCOperandPredicate = [{
int64_t Imm;
if (!MCOp.evaluateAsConstantImm(Imm))
return false;
return isInt<8>(Imm);
}];
}

def SImm10UnsignedAsmOperand : SImmAsmOperand<10, "Unsigned"> {
let RenderMethod = "addSImm10UnsignedOperands";
Expand All @@ -43,49 +62,40 @@ def simm10_unsigned : RISCVOp {
// Instruction class templates
//===----------------------------------------------------------------------===//

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class PLI_i<bits<7> funct7, string opcodestr>
: RVInst<(outs GPR:$rd), (ins simm10:$imm10), opcodestr, "$rd, $imm10", [],
// Common base for pli.b/h/w and plui.h/w
class RVPLoadImm_i<bits<7> funct7, dag ins, string opcodestr,
string argstr>
: RVInst<(outs GPR:$rd), ins, opcodestr, argstr, [],
InstFormatOther> {
bits<10> imm10;
bits<5> rd;

let Inst{31-25} = funct7;
let Inst{24-16} = imm10{8-0};
let Inst{15} = imm10{9};
let Inst{14-12} = 0b010;
let Inst{11-7} = rd;
let Inst{6-0} = OPC_OP_IMM_32.Value;

let hasSideEffects = 0;
let mayLoad = 0;
let mayStore = 0;
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class PLUI_i<bits<7> funct7, string opcodestr>
: RVInst<(outs GPR:$rd), (ins simm10_unsigned:$imm10), opcodestr,
"$rd, $imm10", [], InstFormatOther> {
// Base for pli.h/w.
class PLI_i<bits<7> funct7, string opcodestr>
: RVPLoadImm_i<funct7, (ins simm10:$imm10), opcodestr, "$rd, $imm10"> {
bits<10> imm10;
bits<5> rd;

let Inst{31-25} = funct7;
let Inst{24} = imm10{0};
let Inst{23-15} = imm10{9-1};
let Inst{14-12} = 0b010;
let Inst{11-7} = rd;
let Inst{6-0} = OPC_OP_IMM_32.Value;
let Inst{24-16} = imm10{8-0};
let Inst{15} = imm10{9};
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class PLI_B_i<bits<8> funct8, string opcodestr>
: RVInst<(outs GPR:$rd), (ins uimm8:$uimm8), opcodestr, "$rd, $uimm8", [],
InstFormatOther> {
bits<8> uimm8;
bits<5> rd;
// Base for plui.h/w.
class PLUI_i<bits<7> funct7, string opcodestr>
: RVPLoadImm_i<funct7, (ins simm10_unsigned:$imm10), opcodestr,
"$rd, $imm10"> {
bits<10> imm10;

let Inst{31-24} = funct8;
let Inst{23-16} = uimm8;
let Inst{15} = 0b0;
let Inst{14-12} = 0b010;
let Inst{11-7} = rd;
let Inst{6-0} = OPC_OP_IMM_32.Value;
let Inst{24} = imm10{0};
let Inst{23-15} = imm10{9-1};
}

let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
Expand Down Expand Up @@ -161,14 +171,33 @@ class RVPBinary_rr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class RVPTernary_rrr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
: RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd_wb),
(ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
(ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr,
"$rd, $rs1, $rs2"> {
let Inst{31} = 0b1;
let Inst{30-27} = f;
let Inst{26-25} = w;

let Constraints = "$rd = $rd_wb";
}

// Common base for pli.b/h/w and plui.h/w
class RVPPairLoadImm_i<bits<7> funct7, dag ins, string opcodestr,
string argstr>
: RVInst<(outs GPRPairRV32:$rd), ins, opcodestr, argstr, [],
InstFormatOther> {
bits<5> rd;

let Inst{31-25} = funct7;
let Inst{14-12} = 0b010;
let Inst{11-8} = rd{4-1};
let Inst{7} = 0b0;
let Inst{6-0} = OPC_OP_IMM_32.Value;

let hasSideEffects = 0;
let mayLoad = 0;
let mayStore = 0;
}

//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -210,8 +239,16 @@ let Predicates = [HasStdExtP] in
def PLI_H : PLI_i<0b1011000, "pli.h">;
let Predicates = [HasStdExtP, IsRV64] in
def PLI_W : PLI_i<0b1011001, "pli.w">;
let Predicates = [HasStdExtP] in
def PLI_B : PLI_B_i<0b10110100, "pli.b">;
let Predicates = [HasStdExtP] in {
def PLI_B : RVPLoadImm_i<0b1011010, (ins simm8_unsigned:$imm8), "pli.b",
"$rd, $imm8"> {
bits<8> imm8;

let Inst{24} = 0b0;
let Inst{23-16} = imm8;
let Inst{15} = 0b0;
}
}

let Predicates = [HasStdExtP] in {
def PSEXT_H_B : RVPUnary_ri<0b00, 0b00100, "psext.h.b">;
Expand Down Expand Up @@ -559,3 +596,30 @@ let Predicates = [HasStdExtP, IsRV64] in {
def PPACKT_W : RVPBinary_rr<0b0110, 0b01, 0b100, "ppackt.w">;
def PACKT_RV64 : RVPBinary_rr<0b0110, 0b11, 0b100, "packt">;
} // Predicates = [HasStdExtP, IsRV64]

let Predicates = [HasStdExtP, IsRV32] in {
def PLI_DH : RVPPairLoadImm_i<0b0011000, (ins simm10:$imm10), "pli.dh",
"$rd, $imm10"> {
bits<10> imm10;

let Inst{24-16} = imm10{8-0};
let Inst{15} = imm10{9};
}

def PLI_DB : RVPPairLoadImm_i<0b0011010, (ins simm8_unsigned:$imm8), "pli.db",
"$rd, $imm8"> {
bits<8> imm8;

let Inst{24} = 0b0;
let Inst{23-16} = imm8;
let Inst{15} = 0b0;
}

def PLUI_DH : RVPPairLoadImm_i<0b0111000, (ins simm10_unsigned:$imm10),
"plui.dh", "$rd, $imm10"> {
bits<10> imm10;

let Inst{24} = imm10{0};
let Inst{23-15} = imm10{9-1};
}
}
10 changes: 9 additions & 1 deletion llvm/test/MC/RISCV/rv32p-invalid.s
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Expand Up @@ -4,7 +4,7 @@
# Imm overflow
pli.h a0, 0x400 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [-512, 511]
plui.h a1, 0x400 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-512, 1023]
pli.b a0, 0x200 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [0, 255]
pli.b a0, 0x200 # CHECK: :[[@LINE]]:11: error: immediate must be an integer in the range [-128, 255]

pslli.b a6, a7, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 7]
pslli.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15]
Expand Down Expand Up @@ -106,3 +106,11 @@ ppack.w t5, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the follow
ppackbt.w t5, s0, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
ppacktb.w t5, t1, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
ppackt.w t3, a0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set

pli.dh a1, 1 # CHECK: :[[@LINE]]:8: error: register must be even
pli.db s1, 1 # CHECK: :[[@LINE]]:8: error: register must be even
plui.dh t2, 1 # CHECK: :[[@LINE]]:9: error: register must be even

pli.dh a0, 0x400 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-512, 511]
pli.db a0, 0x200 # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-128, 255]
plui.dh a0, 0x400 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [-512, 1023]
19 changes: 19 additions & 0 deletions llvm/test/MC/RISCV/rv32p-valid.s
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Expand Up @@ -61,6 +61,9 @@ pli.h a5, 16
# CHECK-ASM-AND-OBJ: pli.b a6, 16
# CHECK-ASM: encoding: [0x1b,0x28,0x10,0xb4]
pli.b a6, 16
# CHECK-ASM-AND-OBJ: pli.b a6, -128
# CHECK-ASM: encoding: [0x1b,0x28,0x80,0xb4]
pli.b a6, -128
# CHECK-ASM-AND-OBJ: psext.h.b a7, a0
# CHECK-ASM: encoding: [0x9b,0x28,0x45,0xe0]
psext.h.b a7, a0
Expand Down Expand Up @@ -373,3 +376,19 @@ ppackt.h t3, s0, s0
# CHECK-ASM-AND-OBJ: packt a2, t3, t1
# CHECK-ASM: encoding: [0x3b,0x46,0x6e,0xb2]
packt a2, t3, t1

# CHECK-ASM-AND-OBJ: pli.dh a4, 16
# CHECK-ASM: encoding: [0x1b,0x27,0x10,0x30]
pli.dh a4, 16
# CHECK-ASM-AND-OBJ: pli.db a6, 16
# CHECK-ASM: encoding: [0x1b,0x28,0x10,0x34]
pli.db a6, 16
# CHECK-ASM-AND-OBJ: pli.db a6, -128
# CHECK-ASM: encoding: [0x1b,0x28,0x80,0x34]
pli.db a6, -128
# CHECK-ASM-AND-OBJ: plui.dh tp, 32
# CHECK-ASM: encoding: [0x1b,0x22,0x08,0x70]
plui.dh tp, 32
# CHECK-ASM-AND-OBJ: plui.dh tp, -412
# CHECK-ASM: encoding: [0x1b,0x22,0x99,0x70]
plui.dh tp, 612
5 changes: 5 additions & 0 deletions llvm/test/MC/RISCV/rv64p-invalid.s
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Expand Up @@ -65,3 +65,8 @@ mulsu.h00 a4, s4, s6 # CHECK: :[[@LINE]]:1: error: instruction requires the foll
maccsu.h00 s4, s4, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
mulsu.h11 s8, s4, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
maccsu.h11 s0, a2, s6 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set

# FIXME: This error doesn't make sense. Should say that we need RV32I.
pli.dh a0, 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
pli.db s0, 1 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
plui.dh t1, 1 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
6 changes: 6 additions & 0 deletions llvm/test/MC/RISCV/rv64p-valid.s
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Expand Up @@ -79,6 +79,12 @@ pli.w a5, 5
# CHECK-ASM-AND-OBJ: pli.b a6, 6
# CHECK-ASM: encoding: [0x1b,0x28,0x06,0xb4]
pli.b a6, 6
# CHECK-ASM-AND-OBJ: pli.b a6, -1
# CHECK-ASM: encoding: [0x1b,0x28,0xff,0xb4]
pli.b a6, -1
# CHECK-ASM-AND-OBJ: pli.b a6, -1
# CHECK-ASM: encoding: [0x1b,0x28,0xff,0xb4]
pli.b a6, 255
# CHECK-ASM-AND-OBJ: psext.h.b t3, a2
# CHECK-ASM: encoding: [0x1b,0x2e,0x46,0xe0]
psext.h.b t3, a2
Expand Down