[X86] Remove TuningPOPCNTFalseDeps from AlderLake

[boomanaiden154]

This false dependency issue was fixed in CannonLake looking at the data from uops.info. This is confirmed not to be an issue based on benchmarking data in #153983. Setting this can potentially lead to extra xor instructions whihc could consume extra frontend/renaming resources.

None of the other CPUs that have had this fixed have the tuning flag.

Fixes #153983.

[llvmbot]

@llvm/pr-subscribers-backend-x86

Author: Aiden Grossman (boomanaiden154)

Changes

This false dependency issue was fixed in CannonLake looking at the data from uops.info. This is confirmed not to be an issue based on benchmarking data in #153983. Setting this can potentially lead to extra xor instructions whihc could consume extra frontend/renaming resources.

None of the other CPUs that have had this fixed have the tuning flag.

Fixes #153983.

---

Full diff: https://github.com/llvm/llvm-project/pull/154004.diff

2 Files Affected:

• (modified) llvm/lib/Target/X86/X86.td (+3-1)
• (modified) llvm/test/CodeGen/X86/bitcnt-false-dep.ll (+9)

diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 990b381341f07..3d34ea3bed318 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1291,7 +1291,9 @@ def ProcessorFeatures {
   list<SubtargetFeature> ADLAdditionalTuning = [TuningPERMFalseDeps,
                                                 TuningPreferMovmskOverVTest,
                                                 TuningFastImmVectorShift];
-  list<SubtargetFeature> ADLTuning = !listconcat(SKLTuning, ADLAdditionalTuning);
+  list<SubtargetFeature> ADLRemoveTuning = [TuningPOPCNTFalseDeps];
+  list<SubtargetFeature> ADLTuning =
+      !listremove(!listconcat(SKLTuning, ADLAdditionalTuning), ADLRemoveTuning);
   list<SubtargetFeature> ADLFeatures =
     !listconcat(TRMFeatures, ADLAdditionalFeatures);
 
diff --git a/llvm/test/CodeGen/X86/bitcnt-false-dep.ll b/llvm/test/CodeGen/X86/bitcnt-false-dep.ll
index 5f576c8586285..793cbb8f75bdc 100644
--- a/llvm/test/CodeGen/X86/bitcnt-false-dep.ll
+++ b/llvm/test/CodeGen/X86/bitcnt-false-dep.ll
@@ -1,6 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=haswell | FileCheck %s --check-prefix=HSW
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=skylake | FileCheck %s --check-prefix=SKL
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=skx | FileCheck %s --check-prefix=SKL
+; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=alderlake | FileCheck %s --check-prefix=ADL
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=silvermont -mattr=+lzcnt,+bmi | FileCheck %s --check-prefix=SKL
 ; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=goldmont -mattr=+lzcnt,+bmi | FileCheck %s --check-prefix=SKL
 
@@ -37,6 +38,10 @@ ret:
 ;SKL-LABEL:@loopdep_popcnt32
 ;SKL: xorl [[GPR0:%e[a-d]x]], [[GPR0]]
 ;SKL-NEXT: popcntl {{.*}}, [[GPR0]]
+
+;ADL-LABEL:@loopdep_popcnt32
+;ADL-NOT: xor
+;ADL: popcntl
 }
 
 define i64 @loopdep_popcnt64(ptr nocapture %x, ptr nocapture %y) nounwind {
@@ -63,6 +68,10 @@ ret:
 ;SKL-LABEL:@loopdep_popcnt64
 ;SKL: xorl %e[[GPR0:[a-d]x]], %e[[GPR0]]
 ;SKL-NEXT: popcntq {{.*}}, %r[[GPR0]]
+
+;ADL-LABEL:@loopdep_popcnt64
+;ADL-NOT: xor
+;ADL: popcntq
 }
 
 define i32 @loopdep_tzct32(ptr nocapture %x, ptr nocapture %y) nounwind {

[ms178]

Could you please take a look if that is also true for TuningLZCNTFalseDeps? I've applied the patch below locally which also implements [FeatureERMSB, FeatureFSRM] for Raptor Lake and it seems to perform fine, but that might be an idea for another patch.

--- a/llvm/lib/Target/X86/X86.td	2025-08-17 08:57:51.604276317 +0200
+++ b/llvm/lib/Target/X86/X86.td	2025-08-17 09:07:22.804296154 +0200
@@ -1291,10 +1292,23 @@ def ProcessorFeatures {
   list<SubtargetFeature> ADLAdditionalTuning = [TuningPERMFalseDeps,
                                                 TuningPreferMovmskOverVTest,
                                                 TuningFastImmVectorShift];
-  list<SubtargetFeature> ADLTuning = !listconcat(SKLTuning, ADLAdditionalTuning);
+  // Remove inherited false-dependency tunings that do not apply on Alder/Raptor Lake
+  list<SubtargetFeature> ADLRemoveTuning = [TuningPOPCNTFalseDeps,
+                                            TuningLZCNTFalseDeps];
+  list<SubtargetFeature> ADLTuning =
+    !listremove(!listconcat(SKLTuning, ADLAdditionalTuning), ADLRemoveTuning);
   list<SubtargetFeature> ADLFeatures =
     !listconcat(TRMFeatures, ADLAdditionalFeatures);
 
+  // Raptor Lake (client, no AVX-512): enable fast string ops + prefer 128-bit compute
+  list<SubtargetFeature> RLAdditionalFeatures = [FeatureERMSB, FeatureFSRM];
+  list<SubtargetFeature> RLFeatures =
+    !listconcat(ADLFeatures, RLAdditionalFeatures);
+
+  list<SubtargetFeature> RLAdditionalTuning = [TuningPrefer128Bit];
+  list<SubtargetFeature> RLTuning =
+    !listconcat(ADLTuning, RLAdditionalTuning);
+
   // Gracemont
   list<SubtargetFeature> GRTTuning = [TuningMacroFusion,
                                       TuningSlow3OpsLEA,
@@ -1866,7 +1880,7 @@ foreach P = ["sierraforest", "grandridge
                 ProcessorFeatures.GRTTuning>;
 }
 def : ProcModel<"raptorlake", AlderlakePModel,
-                ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
+                ProcessorFeatures.RLFeatures, ProcessorFeatures.RLTuning>;
 def : ProcModel<"meteorlake", AlderlakePModel,
                 ProcessorFeatures.ADLFeatures, ProcessorFeatures.ADLTuning>;
 def : ProcModel<"arrowlake", AlderlakePModel,

[sharkautarch]

@ms178 afaik, ADLTuning doesn’t have TuningLZCNTFalseDeps in the first place, since SKLTuning doesn’t have that either:

llvm-project/llvm/lib/Target/X86/X86.td

Line 981 in 66a2d1b

TuningPOPCNTFalseDeps,

And to answer your question about whether Alderlake has lzcnt/tzcnt false deps: it’s the same as with popcnt: only for r/m16

[ms178]

TuningLZCNTFalseDeps

@sharkautarch Maybe I am reading it wrong, but doesn't Syklake inherit TuningLZCNTFalseDeps via Haswell and Broadwell tuning, hence it gets passed down to ADLTuning as well at the moment? At least TuningLZCNTFalseDeps is set in the Haswell section (

llvm-project/llvm/lib/Target/X86/X86.td

Line 950 in 66a2d1b

TuningLZCNTFalseDeps,

) and cannot see it getting unset in the later models.

[sharkautarch]

ssed down to ADLTuning as well at the moment? At least TuningLZCNTFalseDeps is set in the Haswell section (

@ms178
That's the SKLFeatures that inherits from BDWFeatures, which in turn inherits from HSWFeatures, and so on
But ADLTuning does not include anything from SKLFeatures, it only inherits from SKLTuning, which is an entirely separate thing
And SKLTuning does not inherit tunings from any other field

llvm-project/llvm/lib/Target/X86/X86.td

Line 1294 in 66a2d1b

list<SubtargetFeature> ADLTuning = !listconcat(SKLTuning, ADLAdditionalTuning);

llvm-project/llvm/lib/Target/X86/X86.td

Line 971 in 66a2d1b

list<SubtargetFeature> SKLTuning = [TuningFastGather,

[phoebewang]

LGTM.

[RKSimon]

LGTM with one minor

[RKSimon]

Can this file be generated with the update script and we share more prefixes?

[boomanaiden154]

Not sure if there are specific features that you have in mind for update_llc_test_checks.py that I'm unfamiliar with, but I don't think it makes a ton of sense here.

We end up having to assert the codegen for the entire function rather than just the bit counting instructions/xors that we're interested in. The new ADL lines will also still be unique as well.

Happy to follow up postcommit if there is a simpler way to do this.