[RISCV] Add changes to have better coverage for qc.insb and qc.insbi

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -16112,6 +16112,13 @@ static SDValue combineXorToBitfieldInsert(SDNode *N, SelectionDAG &DAG,
                                         m_Value(Inserted))))))
     return SDValue();
 
+  KnownBits Known = DAG.computeKnownBits(Inserted);
+
+  // Check if all zero bits in CMask are also zero in Inserted
+  APInt CMaskZeroBits = ~CMask;
+  if (!CMaskZeroBits.isSubsetOf(Known.Zero))
+    return SDValue();
+
   if (N->getValueType(0) != MVT::i32)
     return SDValue();
 

llvm/test/CodeGen/RISCV/xqcibm-insbi.ll

@@ -170,3 +170,24 @@ define i64 @insb_i64(i64 %in1, i64 %in2) {
   %xor2 = xor i64 %xor1, %in1
   ret i64 %xor2
 }
+
+define i8 @tgt2_insb_neg(i8 %x, i8 %y) {
+; RV32I-LABEL: tgt2_insb_neg:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a2, a0, -2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    xor a0, a0, a2
+; RV32I-NEXT:    ret
+;
+; RV32XQCIBM-LABEL: tgt2_insb_neg:
+; RV32XQCIBM:       # %bb.0:
+; RV32XQCIBM-NEXT:    andi a2, a0, -2
+; RV32XQCIBM-NEXT:    xor a0, a0, a1
+; RV32XQCIBM-NEXT:    xor a0, a0, a2
+; RV32XQCIBM-NEXT:    ret
+  %and = and i8 %x, -2
+  %xor1 = xor i8 %and, %y
+  %xor2 = xor i8 %x, %xor1
+  ret i8 %xor2
+}
+