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[CIR] Fix access to bitfields inside a union #154398

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Merged
merged 3 commits into from
Aug 19, 2025
Merged

[CIR] Fix access to bitfields inside a union #154398

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9627944
[CIR] Fix access to bitfields inside a union
Andres-Salamanca Aug 19, 2025
4ce62aa
Change test return and update getMember to use field index
Andres-Salamanca Aug 19, 2025
a0967f0
Rename test function
Andres-Salamanca Aug 19, 2025
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5 changes: 3 additions & 2 deletions clang/lib/CIR/CodeGen/CIRGenExpr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -372,9 +372,10 @@ Address CIRGenFunction::getAddrOfBitFieldStorage(LValue base,
unsigned index) {
mlir::Location loc = getLoc(field->getLocation());
cir::PointerType fieldPtr = cir::PointerType::get(fieldType);
cir::GetMemberOp sea = getBuilder().createGetMember(
loc, fieldPtr, base.getPointer(), field->getName(), index);
auto rec = cast<cir::RecordType>(base.getAddress().getElementType());
cir::GetMemberOp sea = getBuilder().createGetMember(
loc, fieldPtr, base.getPointer(), field->getName(),
rec.isUnion() ? field->getFieldIndex() : index);
CharUnits offset = CharUnits::fromQuantity(
rec.getElementOffset(cgm.getDataLayout().layout, index));
return Address(sea, base.getAlignment().alignmentAtOffset(offset));
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41 changes: 41 additions & 0 deletions clang/test/CIR/CodeGen/bitfield-union.c
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Expand Up @@ -28,3 +28,44 @@ typedef union {

demo d;
zero_bit z;

void main() {
demo d;
d.x = 1;
d.y = 2;
d.z = 0;
}

// CIR: #bfi_y = #cir.bitfield_info<name = "y", storage_type = !u8i, size = 4, offset = 0, is_signed = true>
// CIR: #bfi_z = #cir.bitfield_info<name = "z", storage_type = !u8i, size = 8, offset = 0, is_signed = true>

// CIR: cir.func no_proto dso_local @main
// CIR: [[ALLOC:%.*]] = cir.alloca !rec_demo, !cir.ptr<!rec_demo>, ["d"] {alignment = 4 : i64}
// CIR: [[ONE:%.*]] = cir.const #cir.int<1> : !s32i
// CIR: [[X:%.*]] = cir.get_member [[ALLOC]][0] {name = "x"} : !cir.ptr<!rec_demo> -> !cir.ptr<!s32i>
// CIR: cir.store align(4) [[ONE]], [[X]] : !s32i, !cir.ptr<!s32i>
// CIR: [[TWO:%.*]] = cir.const #cir.int<2> : !s32i
// CIR: [[Y:%.*]] = cir.get_member [[ALLOC]][1] {name = "y"} : !cir.ptr<!rec_demo> -> !cir.ptr<!u8i>
// CIR: [[SET:%.*]] = cir.set_bitfield align(4) (#bfi_y, [[Y]] : !cir.ptr<!u8i>, [[TWO]] : !s32i) -> !s32i
// CIR: [[ZERO:%.*]] = cir.const #cir.int<0> : !s32i
// CIR: [[Z:%.*]] = cir.get_member [[ALLOC]][2] {name = "z"} : !cir.ptr<!rec_demo> -> !cir.ptr<!u8i>
// CIR: [[SET2:%.*]] = cir.set_bitfield align(4) (#bfi_z, [[Z]] : !cir.ptr<!u8i>, [[ZERO]] : !s32i) -> !s32i
// CIR: cir.return

// LLVM: define dso_local void @main
// LLVM: [[ALLOC:%.*]] = alloca %union.demo, i64 1, align 4
// LLVM: store i32 1, ptr [[ALLOC]], align 4
// LLVM: [[BFLOAD:%.*]] = load i8, ptr [[ALLOC]], align 4
// LLVM: [[CLEAR:%.*]] = and i8 [[BFLOAD]], -16
// LLVM: [[SET:%.*]] = or i8 [[CLEAR]], 2
// LLVM: store i8 [[SET]], ptr [[ALLOC]], align 4
// LLVM: store i8 0, ptr [[ALLOC]], align 4

// OGCG: define dso_local void @main
// OGCG: [[ALLOC:%.*]] = alloca %union.demo, align 4
// OGCG: store i32 1, ptr [[ALLOC]], align 4
// OGCG: [[BFLOAD:%.*]] = load i8, ptr [[ALLOC]], align 4
// OGCG: [[CLEAR:%.*]] = and i8 [[BFLOAD]], -16
// OGCG: [[SET:%.*]] = or i8 [[CLEAR]], 2
// OGCG: store i8 [[SET]], ptr [[ALLOC]], align 4
// OGCG: store i8 0, ptr [[ALLOC]], align 4