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Add PowerPC/AIX related release notes to LLVM 21.1.0 #154465

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Aug 21, 2025
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Add PowerPC/AIX related release notes to LLVM 21.1.0 #154465

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10 changes: 10 additions & 0 deletions clang/docs/ReleaseNotes.rst
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Expand Up @@ -1131,9 +1131,19 @@ CUDA/HIP Language Changes
CUDA Support
^^^^^^^^^^^^

PowerPC Support
^^^^^^^^^^^^^^^

* Add `__dmr1024` type for Dense Math Facility.
* Add prototype for Dense Math Facility integer calculation builtins.

AIX Support
^^^^^^^^^^^

* Fixed `-print-runtime-dir` to fallback to the target subdirectory (rather than OS subdirectory) if the runtime path is not found.
* Fixed `-print-runtime-dir` to find the correct runtime path if the triple has "unknown" as the environment component.
* Changed AIX targets to use the per-target runtime directories for compiler runtimes (i.e. `lib/clang/20/lib/aix` became `lib/clang/21/lib/powerpc-ibm-aix` and `clang/21/lib/powerpc64-ibm-aix`).

NetBSD Support
^^^^^^^^^^^^^^

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18 changes: 18 additions & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -159,6 +159,18 @@ Changes to the MIPS Backend
Changes to the PowerPC Backend
------------------------------

* Add spill and restore for DMR and DMRp registers.
* Prototype various Dense Math Facility instructions, and intrinsics for basic enablement, insert/extract, integer and FP calculations.
* Add prototype for Dense Math Facility cryptography instructions.
* Implement load/stores prototype for v1024i1, v2048i1.
* Support conversion between f16 and f128.
* Change default for auto gen stxvp for cpu=future.
* Setup initial JITLink build support for XCOFF.
* Add an API to derive the default feature set from a CPU name within the TargetParser
(e.g. `pwr10` -> `+vsx`,`+isa3_1`,`+mma`). Clang now uses this to populate the `target-feature`
list when `-mcpu` is provided for PowerPC.
* Various bug fixes and codegen improvements.

Changes to the RISC-V Backend
-----------------------------

Expand Down Expand Up @@ -220,6 +232,7 @@ Changes to the RISC-V Backend
* Removed -mattr=+no-rvc-hints that could be used to disable parsing and generation of RVC hints.
* Adds assembler support for the Andes `XAndesvsintload` (Andes Vector INT4 Load extension).
* Adds assembler support for the Andes `XAndesbfhcvt` (Andes Scalar BFLOAT16 Conversion extension).
* Add combine for shadd family of instructions.
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@amy-kwan amy-kwan Aug 20, 2025

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@stefanp-synopsys FYI, we added this to the LLVM 21.x release notes from your patch: [RISCV] Add combine for shadd family of instructions.

If you don't think this is necessary to add, we can remove this.


Changes to the WebAssembly Backend
----------------------------------
Expand Down Expand Up @@ -352,6 +365,11 @@ Other Changes
communication with the distributor.
([#47468](https://github.com/llvm/llvm-project/issues/47468)).

Changes to the Profile Runtime
---------------------

* On AIX, avoid using mmap when reading profile files from a non-local filesystem.

External Open Source Projects Using LLVM {{env.config.release}}
===============================================================

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