diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
index edcf2473d45cd..632c6a2fba1b6 100644
--- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
+++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td
@@ -1407,7 +1407,7 @@ let isBarrier = 1, isTerminator = 1 in {
     let r = 0x04;
   }
 
-  def BREAK_N : RRRN_Inst<0x0C, (outs), (ins uimm4:$imm),
+  def BREAK_N : RRRN_Inst<0x0D, (outs), (ins uimm4:$imm),
                          "break.n\t$imm", []>, Requires<[HasDensity, HasDebug]> {
     bits<4> imm;
 
diff --git a/llvm/test/MC/Disassembler/Xtensa/debug.txt b/llvm/test/MC/Disassembler/Xtensa/debug.txt
index 1321f09a973c3..5438760c43cfa 100644
--- a/llvm/test/MC/Disassembler/Xtensa/debug.txt
+++ b/llvm/test/MC/Disassembler/Xtensa/debug.txt
@@ -9,7 +9,7 @@
 # CHECK-DEBUG: break 1, 1
 # CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
 
-[0x2c,0xf1]
+[0x2d,0xf1]
 # CHECK-DEBUG: break.n 1
 # CHECK-CORE: [[#@LINE-2]]:2: warning: invalid instruction encoding
 
diff --git a/llvm/test/MC/Xtensa/debug.s b/llvm/test/MC/Xtensa/debug.s
index 36b1f110d120b..4ca6368d19f1c 100644
--- a/llvm/test/MC/Xtensa/debug.s
+++ b/llvm/test/MC/Xtensa/debug.s
@@ -11,7 +11,7 @@ break 1, 1
 
 # Instruction format RRRN
 # CHECK-INST: break.n 1
-# CHECK: encoding: [0x2c,0xf1]
+# CHECK: encoding: [0x2d,0xf1]
 break.n 1
 
 # Instruction format RRR