diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index d72af06ac566e..e1bc6d0239111 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -1260,17 +1260,6 @@ void SIFoldOperandsImpl::foldOperand( return; const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg); - if (!DestReg.isPhysical() && DestRC == &AMDGPU::AGPR_32RegClass) { - std::optional UseImmVal = OpToFold.getEffectiveImmVal(); - if (UseImmVal && TII->isInlineConstant( - *UseImmVal, AMDGPU::OPERAND_REG_INLINE_C_INT32)) { - UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64)); - UseMI->getOperand(1).ChangeToImmediate(*UseImmVal); - CopiesToReplace.push_back(UseMI); - return; - } - } - // Allow immediates COPYd into sgpr_lo16 to be further folded while // still being legal if not further folded if (DestRC == &AMDGPU::SGPR_LO16RegClass) { @@ -1283,7 +1272,8 @@ void SIFoldOperandsImpl::foldOperand( // MOV. Find a compatible mov instruction with the value. for (unsigned MovOp : {AMDGPU::S_MOV_B32, AMDGPU::V_MOV_B32_e32, AMDGPU::S_MOV_B64, - AMDGPU::V_MOV_B64_PSEUDO, AMDGPU::V_MOV_B16_t16_e64}) { + AMDGPU::V_MOV_B64_PSEUDO, AMDGPU::V_MOV_B16_t16_e64, + AMDGPU::V_ACCVGPR_WRITE_B32_e64, AMDGPU::AV_MOV_B32_IMM_PSEUDO}) { const MCInstrDesc &MovDesc = TII->get(MovOp); assert(MovDesc.getNumDefs() > 0 && MovDesc.operands()[0].RegClass != -1); diff --git a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll index 8b2f0a7ed63c1..51caa84450ff3 100644 --- a/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll +++ b/llvm/test/CodeGen/AMDGPU/attributor-flatscratchinit-undefined-behavior2.ll @@ -166,14 +166,13 @@ define amdgpu_kernel void @with_private_to_flat_addrspacecast_cc_kernel(ptr addr ; GFX942-ARCH-FLAT: ; %bb.0: ; GFX942-ARCH-FLAT-NEXT: s_load_dword s2, s[4:5], 0x0 ; GFX942-ARCH-FLAT-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX942-ARCH-FLAT-NEXT: s_mov_b32 s0, 0 -; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v2, s0 +; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v2, 0 ; GFX942-ARCH-FLAT-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-ARCH-FLAT-NEXT: s_cmp_lg_u32 s2, -1 -; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s1, s1, 0 -; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s2, s2, 0 -; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v0, s2 -; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v1, s1 +; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s0, s1, 0 +; GFX942-ARCH-FLAT-NEXT: s_cselect_b32 s1, s2, 0 +; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v0, s1 +; GFX942-ARCH-FLAT-NEXT: v_mov_b32_e32 v1, s0 ; GFX942-ARCH-FLAT-NEXT: flat_store_dword v[0:1], v2 sc0 sc1 ; GFX942-ARCH-FLAT-NEXT: s_waitcnt vmcnt(0) ; GFX942-ARCH-FLAT-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll index fadcc39c95f47..fc8883924dfbc 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-scratch.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-scratch.ll @@ -463,8 +463,7 @@ define amdgpu_kernel void @store_load_sindex_kernel(i32 %idx) { ; GFX942-LABEL: store_load_sindex_kernel: ; GFX942: ; %bb.0: ; %bb ; GFX942-NEXT: s_load_dword s0, s[4:5], 0x24 -; GFX942-NEXT: s_mov_b32 s1, 15 -; GFX942-NEXT: v_mov_b32_e32 v0, s1 +; GFX942-NEXT: v_mov_b32_e32 v0, 15 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: s_lshl_b32 s1, s0, 2 ; GFX942-NEXT: s_and_b32 s0, s0, 15 @@ -611,9 +610,8 @@ define amdgpu_ps void @store_load_sindex_foo(i32 inreg %idx) { ; ; GFX942-LABEL: store_load_sindex_foo: ; GFX942: ; %bb.0: ; %bb -; GFX942-NEXT: s_mov_b32 s2, 15 ; GFX942-NEXT: s_lshl_b32 s1, s0, 2 -; GFX942-NEXT: v_mov_b32_e32 v0, s2 +; GFX942-NEXT: v_mov_b32_e32 v0, 15 ; GFX942-NEXT: s_and_b32 s0, s0, 15 ; GFX942-NEXT: scratch_store_dword off, v0, s1 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) @@ -1590,8 +1588,7 @@ define amdgpu_kernel void @store_load_sindex_small_offset_kernel(i32 %idx) { ; GFX942-NEXT: s_load_dword s0, s[4:5], 0x24 ; GFX942-NEXT: scratch_load_dword v0, off, off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) -; GFX942-NEXT: s_mov_b32 s1, 15 -; GFX942-NEXT: v_mov_b32_e32 v0, s1 +; GFX942-NEXT: v_mov_b32_e32 v0, 15 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: s_lshl_b32 s1, s0, 2 ; GFX942-NEXT: s_and_b32 s0, s0, 15 @@ -1808,10 +1805,9 @@ define amdgpu_ps void @store_load_sindex_small_offset_foo(i32 inreg %idx) { ; GFX942-NEXT: scratch_load_dword v0, off, off sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_lshl_b32 s1, s0, 2 -; GFX942-NEXT: s_mov_b32 s2, 15 ; GFX942-NEXT: s_and_b32 s0, s0, 15 ; GFX942-NEXT: s_addk_i32 s1, 0x100 -; GFX942-NEXT: v_mov_b32_e32 v0, s2 +; GFX942-NEXT: v_mov_b32_e32 v0, 15 ; GFX942-NEXT: s_lshl_b32 s0, s0, 2 ; GFX942-NEXT: scratch_store_dword off, v0, s1 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) @@ -2888,8 +2884,7 @@ define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) { ; GFX942-NEXT: s_load_dword s0, s[4:5], 0x24 ; GFX942-NEXT: scratch_load_dword v0, off, off offset:4 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) -; GFX942-NEXT: s_mov_b32 s1, 15 -; GFX942-NEXT: v_mov_b32_e32 v0, s1 +; GFX942-NEXT: v_mov_b32_e32 v0, 15 ; GFX942-NEXT: s_waitcnt lgkmcnt(0) ; GFX942-NEXT: s_lshl_b32 s1, s0, 2 ; GFX942-NEXT: s_and_b32 s0, s0, 15 @@ -3106,10 +3101,9 @@ define amdgpu_ps void @store_load_sindex_large_offset_foo(i32 inreg %idx) { ; GFX942-NEXT: scratch_load_dword v0, off, off offset:4 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) ; GFX942-NEXT: s_lshl_b32 s1, s0, 2 -; GFX942-NEXT: s_mov_b32 s2, 15 ; GFX942-NEXT: s_and_b32 s0, s0, 15 ; GFX942-NEXT: s_addk_i32 s1, 0x4004 -; GFX942-NEXT: v_mov_b32_e32 v0, s2 +; GFX942-NEXT: v_mov_b32_e32 v0, 15 ; GFX942-NEXT: s_lshl_b32 s0, s0, 2 ; GFX942-NEXT: scratch_store_dword off, v0, s1 sc0 sc1 ; GFX942-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir index a079ee1296f41..6f2e33900a79a 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-imm-copy-agpr.mir @@ -91,8 +91,8 @@ body: | bb.0: ; GCN-LABEL: name: v_mov_b64_pseudo_lit_copy_sub0_to_agpr_32 ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec - ; GCN-NEXT: [[COPY:%[0-9]+]]:agpr_32 = COPY [[V_MOV_B]].sub0 - ; GCN-NEXT: $agpr0 = COPY [[COPY]] + ; GCN-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[V_MOV_B]].sub0, implicit $exec + ; GCN-NEXT: $agpr0 = COPY [[V_ACCVGPR_WRITE_B32_e64_]] ; GCN-NEXT: S_ENDPGM 0 %0:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec %1:agpr_32 = COPY %0.sub0 @@ -108,8 +108,8 @@ body: | bb.0: ; GCN-LABEL: name: v_mov_b64_pseudo_lit_copy_sub1_to_agpr_32 ; GCN: [[V_MOV_B:%[0-9]+]]:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec - ; GCN-NEXT: [[COPY:%[0-9]+]]:agpr_32 = COPY [[V_MOV_B]].sub1 - ; GCN-NEXT: $agpr0 = COPY [[COPY]] + ; GCN-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[V_MOV_B]].sub1, implicit $exec + ; GCN-NEXT: $agpr0 = COPY [[V_ACCVGPR_WRITE_B32_e64_]] ; GCN-NEXT: S_ENDPGM 0 %0:vreg_64_align2 = V_MOV_B64_PSEUDO 4290672329592, implicit $exec %1:agpr_32 = COPY %0.sub1 @@ -133,3 +133,329 @@ body: | S_ENDPGM 0, implicit %1 ... + +--- +name: s_mov_b32_imm_0_copy_to_agpr_32 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b32_imm_0_copy_to_agpr_32 + ; GCN: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec + ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ACCVGPR_WRITE_B32_e64_]] + %0:sreg_32 = S_MOV_B32 0, implicit $exec + %1:agpr_32 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b32_imm_neg16_copy_to_agpr_32 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b32_imm_neg16_copy_to_agpr_32 + ; GCN: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 -16, implicit $exec + ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ACCVGPR_WRITE_B32_e64_]] + %0:sreg_32 = S_MOV_B32 -16, implicit $exec + %1:agpr_32 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b32_imm_65_copy_to_agpr_32 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b32_imm_65_copy_to_agpr_32 + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65, implicit $exec + ; GCN-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[S_MOV_B32_]], implicit $exec + ; GCN-NEXT: S_ENDPGM 0, implicit [[V_ACCVGPR_WRITE_B32_e64_]] + %0:sreg_32 = S_MOV_B32 65, implicit $exec + %1:agpr_32 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b32_imm_0_copy_to_av_32 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b32_imm_0_copy_to_av_32 + ; GCN: [[AV_MOV_:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec + ; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]] + %0:sreg_32 = S_MOV_B32 0, implicit $exec + %1:av_32 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b32_imm_neg16_copy_to_av_32 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b32_imm_neg16_copy_to_av_32 + ; GCN: [[AV_MOV_:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO -16, implicit $exec + ; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]] + %0:sreg_32 = S_MOV_B32 -16, implicit $exec + %1:av_32 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b32_imm_65_copy_to_av_32 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b32_imm_65_copy_to_av_32 + ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65, implicit $exec + ; GCN-NEXT: [[AV_MOV_:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO [[S_MOV_B32_]], implicit $exec + ; GCN-NEXT: S_ENDPGM 0, implicit [[AV_MOV_]] + %0:sreg_32 = S_MOV_B32 65, implicit $exec + %1:av_32 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_0_copy_to_areg_64 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_0_copy_to_areg_64 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64 = COPY [[S_MOV_B64_]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64 0, implicit $exec + %1:areg_64 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_0_copy_to_areg_64_align2 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_0_copy_to_areg_64_align2 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[S_MOV_B64_]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64 0, implicit $exec + %1:areg_64_align2 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_neg16_copy_to_areg_64 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_neg16_copy_to_areg_64 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -16, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64 = COPY [[S_MOV_B64_]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64 -16, implicit $exec + %1:areg_64 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_neg16_copy_to_areg_64_align2 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_neg16_copy_to_areg_64_align2 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -16, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[S_MOV_B64_]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64 -16, implicit $exec + %1:areg_64_align2 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_0_copy_to_av_64 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_0_copy_to_av_64 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:av_64 = COPY [[S_MOV_B64_]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64 0, implicit $exec + %1:av_64 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_0_copy_to_av_64_align2 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_0_copy_to_av_64_align2 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY [[S_MOV_B64_]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64 0, implicit $exec + %1:av_64_align2 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_neg16_copy_to_av_64 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_neg16_copy_to_av_64 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -16, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:av_64 = COPY [[S_MOV_B64_]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64 -16, implicit $exec + %1:av_64 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_neg16_copy_to_av_64_align2 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_neg16_copy_to_av_64_align2 + ; GCN: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -16, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY [[S_MOV_B64_]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64 -16, implicit $exec + %1:av_64_align2 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_areg_64 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_areg_64 + ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64 = COPY [[S_MOV_B]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744030759878656, implicit $exec + %1:areg_64 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_areg_64_align2 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_areg_64_align2 + ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[S_MOV_B]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744030759878656, implicit $exec + %1:areg_64_align2 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_areg_64 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_areg_64 + ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -21474836480, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64 = COPY [[S_MOV_B]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744052234715136, implicit $exec + %1:areg_64 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_areg_64_align2 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_areg_64_align2 + ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -21474836480, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:areg_64_align2 = COPY [[S_MOV_B]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744052234715136, implicit $exec + %1:areg_64_align2 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_av_64 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_av_64 + ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:av_64 = COPY [[S_MOV_B]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744030759878656, implicit $exec + %1:av_64 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_av_64_align2 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_pseudo_literal_32_halves_copy_to_av_64_align2 + ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -42949672960, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY [[S_MOV_B]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64_IMM_PSEUDO 18446744030759878656, implicit $exec + %1:av_64_align2 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_av_64 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_av_64 + ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -9223372036854775784, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:av_64 = COPY [[S_MOV_B]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64_IMM_PSEUDO -9223372036854775784, implicit $exec + %1:av_64 = COPY %0 + S_ENDPGM 0, implicit %1 + +... + +--- +name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_av_64_align2 +tracksRegLiveness: true +body: | + bb.0: + ; GCN-LABEL: name: s_mov_b64_imm_pseudo_inlineimm_32_halves_copy_to_av_64_align2 + ; GCN: [[S_MOV_B:%[0-9]+]]:sreg_64 = S_MOV_B64_IMM_PSEUDO -9223372036854775784, implicit $exec + ; GCN-NEXT: [[COPY:%[0-9]+]]:av_64_align2 = COPY [[S_MOV_B]] + ; GCN-NEXT: S_ENDPGM 0, implicit [[COPY]] + %0:sreg_64 = S_MOV_B64_IMM_PSEUDO -9223372036854775784, implicit $exec + %1:av_64_align2 = COPY %0 + S_ENDPGM 0, implicit %1 + +... diff --git a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir index 9a51f457a567a..ddf2aa34ecd87 100644 --- a/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir +++ b/llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir @@ -191,8 +191,8 @@ body: | bb.0: ; GCN-LABEL: name: v_mov_b32_imm_literal_copy_v_to_agpr_32 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 999, implicit $exec - ; GCN-NEXT: [[COPY:%[0-9]+]]:agpr_32 = COPY [[V_MOV_B32_e32_]] - ; GCN-NEXT: $agpr0 = COPY [[COPY]] + ; GCN-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 [[V_MOV_B32_e32_]], implicit $exec + ; GCN-NEXT: $agpr0 = COPY [[V_ACCVGPR_WRITE_B32_e64_]] ; GCN-NEXT: S_ENDPGM 0 %0:vgpr_32 = V_MOV_B32_e32 999, implicit $exec %1:agpr_32 = COPY %0 @@ -207,9 +207,8 @@ tracksRegLiveness: true body: | bb.0: ; GCN-LABEL: name: s_mov_b32_inlineimm_copy_s_to_av_32 - ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32 - ; GCN-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[S_MOV_B32_]] - ; GCN-NEXT: $agpr0 = COPY [[COPY]] + ; GCN: [[AV_MOV_:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO 32, implicit $exec + ; GCN-NEXT: $agpr0 = COPY [[AV_MOV_]] ; GCN-NEXT: S_ENDPGM 0 %0:sreg_32 = S_MOV_B32 32 %1:av_32 = COPY %0 @@ -224,9 +223,8 @@ tracksRegLiveness: true body: | bb.0: ; GCN-LABEL: name: v_mov_b32_inlineimm_copy_v_to_av_32 - ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 32, implicit $exec - ; GCN-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[V_MOV_B32_e32_]] - ; GCN-NEXT: $agpr0 = COPY [[COPY]] + ; GCN: [[AV_MOV_:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO 32, implicit $exec + ; GCN-NEXT: $agpr0 = COPY [[AV_MOV_]] ; GCN-NEXT: S_ENDPGM 0 %0:vgpr_32 = V_MOV_B32_e32 32, implicit $exec %1:av_32 = COPY %0 @@ -242,8 +240,8 @@ body: | bb.0: ; GCN-LABEL: name: s_mov_b32_imm_literal_copy_s_to_av_32 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 999 - ; GCN-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[S_MOV_B32_]] - ; GCN-NEXT: $agpr0 = COPY [[COPY]] + ; GCN-NEXT: [[AV_MOV_:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO [[S_MOV_B32_]], implicit $exec + ; GCN-NEXT: $agpr0 = COPY [[AV_MOV_]] ; GCN-NEXT: S_ENDPGM 0 %0:sreg_32 = S_MOV_B32 999 %1:av_32 = COPY %0 @@ -259,8 +257,8 @@ body: | bb.0: ; GCN-LABEL: name: v_mov_b32_imm_literal_copy_v_to_av_32 ; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 999, implicit $exec - ; GCN-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[V_MOV_B32_e32_]] - ; GCN-NEXT: $agpr0 = COPY [[COPY]] + ; GCN-NEXT: [[AV_MOV_:%[0-9]+]]:av_32 = AV_MOV_B32_IMM_PSEUDO [[V_MOV_B32_e32_]], implicit $exec + ; GCN-NEXT: $agpr0 = COPY [[AV_MOV_]] ; GCN-NEXT: S_ENDPGM 0 %0:vgpr_32 = V_MOV_B32_e32 999, implicit $exec %1:av_32 = COPY %0 diff --git a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll index 6110b3101020a..d39daaade677f 100644 --- a/llvm/test/CodeGen/AMDGPU/mfma-loop.ll +++ b/llvm/test/CodeGen/AMDGPU/mfma-loop.ll @@ -708,103 +708,72 @@ define amdgpu_kernel void @test_mfma_loop_unfoldable_seq(ptr addrspace(1) %arg) ; GFX908-LABEL: test_mfma_loop_unfoldable_seq: ; GFX908: ; %bb.0: ; %entry ; GFX908-NEXT: v_mov_b32_e32 v0, 0x431a0000 -; GFX908-NEXT: s_mov_b32 s0, 16 -; GFX908-NEXT: v_mov_b32_e32 v1, 1.0 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x43190000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x43160000 ; GFX908-NEXT: v_accvgpr_write_b32 a31, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43190000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a30, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a30, v1 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x43180000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x43170000 +; GFX908-NEXT: v_accvgpr_write_b32 a27, v2 ; GFX908-NEXT: v_accvgpr_write_b32 a29, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43170000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a28, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43160000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a27, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a28, v1 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x43150000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x43140000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x43130000 ; GFX908-NEXT: v_accvgpr_write_b32 a26, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43140000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a25, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43130000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a24, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a25, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a24, v2 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x43120000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x43110000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x43100000 ; GFX908-NEXT: v_accvgpr_write_b32 a23, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43110000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a22, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43100000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a21, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a22, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a21, v2 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x430f0000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x430e0000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x430d0000 ; GFX908-NEXT: v_accvgpr_write_b32 a20, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x430e0000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a19, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x430d0000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a18, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a19, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a18, v2 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x430c0000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x430b0000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x430a0000 ; GFX908-NEXT: v_accvgpr_write_b32 a17, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x430b0000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a16, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x430a0000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a15, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a16, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a15, v2 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x43090000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x43080000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x43070000 ; GFX908-NEXT: v_accvgpr_write_b32 a14, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43080000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a13, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43070000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a12, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a13, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a12, v2 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x43060000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x43050000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x43040000 ; GFX908-NEXT: v_accvgpr_write_b32 a11, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43050000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a10, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43040000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a9, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a10, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a9, v2 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x43030000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x43020000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x43010000 ; GFX908-NEXT: v_accvgpr_write_b32 a8, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43020000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a7, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x43010000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a6, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a7, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a6, v2 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x43000000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x42fe0000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x42fc0000 ; GFX908-NEXT: v_accvgpr_write_b32 a5, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x42fe0000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a4, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x42fc0000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a3, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a4, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a3, v2 ; GFX908-NEXT: v_mov_b32_e32 v0, 0x42fa0000 -; GFX908-NEXT: s_nop 1 +; GFX908-NEXT: v_mov_b32_e32 v1, 0x42f80000 +; GFX908-NEXT: v_mov_b32_e32 v2, 0x42f60000 ; GFX908-NEXT: v_accvgpr_write_b32 a2, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x42f80000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a1, v0 -; GFX908-NEXT: v_mov_b32_e32 v0, 0x42f60000 -; GFX908-NEXT: s_nop 1 -; GFX908-NEXT: v_accvgpr_write_b32 a0, v0 +; GFX908-NEXT: v_accvgpr_write_b32 a1, v1 +; GFX908-NEXT: v_accvgpr_write_b32 a0, v2 +; GFX908-NEXT: s_mov_b32 s0, 16 ; GFX908-NEXT: v_mov_b32_e32 v0, 2.0 +; GFX908-NEXT: v_mov_b32_e32 v1, 1.0 ; GFX908-NEXT: .LBB3_1: ; %for.cond.preheader ; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX908-NEXT: s_nop 1 diff --git a/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll b/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll index 89b90d7cd74f6..fb971e42115f8 100644 --- a/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll +++ b/llvm/test/CodeGen/AMDGPU/undef-handling-crash-in-ra.ll @@ -19,22 +19,24 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x ; CHECK-NEXT: s_mov_b64 s[4:5], src_private_base ; CHECK-NEXT: s_waitcnt lgkmcnt(0) ; CHECK-NEXT: s_cmp_lg_u32 s68, -1 -; CHECK-NEXT: s_cselect_b32 s4, s5, 0 -; CHECK-NEXT: s_cselect_b32 s5, s68, 0 +; CHECK-NEXT: s_mov_b64 s[38:39], s[6:7] +; CHECK-NEXT: s_mov_b32 s4, 0 +; CHECK-NEXT: s_cselect_b32 s5, s5, 0 +; CHECK-NEXT: s_cselect_b32 s6, s68, 0 ; CHECK-NEXT: s_add_u32 s50, s34, 48 +; CHECK-NEXT: v_mov_b32_e32 v47, s5 +; CHECK-NEXT: s_mov_b32 s5, s4 ; CHECK-NEXT: s_addc_u32 s51, s35, 0 -; CHECK-NEXT: v_mov_b32_e32 v46, s5 -; CHECK-NEXT: v_mov_b32_e32 v47, s4 +; CHECK-NEXT: v_pk_mov_b32 v[62:63], s[4:5], s[4:5] op_sel:[0,1] ; CHECK-NEXT: s_getpc_b64 s[4:5] ; CHECK-NEXT: s_add_u32 s4, s4, G@gotpcrel32@lo+4 ; CHECK-NEXT: s_addc_u32 s5, s5, G@gotpcrel32@hi+12 -; CHECK-NEXT: v_pk_mov_b32 v[56:57], s[64:65], s[64:65] op_sel:[0,1] -; CHECK-NEXT: s_load_dwordx2 s[64:65], s[4:5], 0x0 -; CHECK-NEXT: s_mov_b32 s54, 0 -; CHECK-NEXT: s_mov_b32 s55, s54 +; CHECK-NEXT: s_load_dwordx2 s[54:55], s[4:5], 0x0 ; CHECK-NEXT: s_mov_b32 s53, s14 -; CHECK-NEXT: v_pk_mov_b32 v[62:63], s[54:55], s[54:55] op_sel:[0,1] +; CHECK-NEXT: v_mov_b32_e32 v46, s6 +; CHECK-NEXT: v_pk_mov_b32 v[56:57], s[64:65], s[64:65] op_sel:[0,1] ; CHECK-NEXT: s_mov_b64 s[4:5], s[48:49] +; CHECK-NEXT: s_mov_b64 s[6:7], s[38:39] ; CHECK-NEXT: s_mov_b64 s[8:9], s[50:51] ; CHECK-NEXT: s_mov_b32 s12, s14 ; CHECK-NEXT: s_mov_b32 s13, s15 @@ -44,14 +46,13 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x ; CHECK-NEXT: s_mov_b32 s33, s16 ; CHECK-NEXT: s_mov_b32 s52, s15 ; CHECK-NEXT: s_mov_b64 s[36:37], s[10:11] -; CHECK-NEXT: s_mov_b64 s[38:39], s[6:7] ; CHECK-NEXT: v_mov_b32_e32 v40, v0 ; CHECK-NEXT: v_mov_b32_e32 v60, s66 ; CHECK-NEXT: v_mov_b32_e32 v61, s67 ; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[62:63] ; CHECK-NEXT: ; kill: def $sgpr15 killed $sgpr15 ; CHECK-NEXT: s_waitcnt lgkmcnt(0) -; CHECK-NEXT: s_swappc_b64 s[30:31], s[64:65] +; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55] ; CHECK-NEXT: flat_load_dwordx2 v[58:59], v[56:57] ; CHECK-NEXT: v_mov_b32_e32 v0, 0 ; CHECK-NEXT: v_mov_b32_e32 v1, 0x3ff00000 @@ -67,7 +68,7 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x ; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[62:63] ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: ; kill: def $sgpr15 killed $sgpr15 -; CHECK-NEXT: s_swappc_b64 s[30:31], s[64:65] +; CHECK-NEXT: s_swappc_b64 s[30:31], s[54:55] ; CHECK-NEXT: flat_load_dwordx2 v[0:1], v[46:47] glc ; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CHECK-NEXT: v_mov_b32_e32 v1, s67 @@ -76,7 +77,7 @@ define amdgpu_kernel void @foo(ptr addrspace(5) %ptr5, ptr %p0, double %v0, <4 x ; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: flat_store_dwordx2 v[56:57], v[60:61] ; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen offset:4 -; CHECK-NEXT: v_mov_b32_e32 v1, s54 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 ; CHECK-NEXT: v_cmp_lt_i32_e32 vcc, 0, v42 ; CHECK-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen ; CHECK-NEXT: ; implicit-def: $vgpr4