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[X86][GISEL] - Legalize G_FPTOUI & G_UITOFP for X87 #155562

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[X86][GISEL] - Legalize G_FPTOUI & G_UITOFP for X87 #155562

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fbce4a4
[X86][GISEL] - Legalize G_FPTOUI for X87
pawan-nirpal-031 Aug 27, 2025
9bf22ad
[X86][GISEL] - Legalize G_UITOFP in X87 mode
pawan-nirpal-031 Sep 1, 2025
cccb00f
Merge branch 'llvm:main' into main
pawan-nirpal-031 Oct 25, 2025
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80 changes: 73 additions & 7 deletions llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -496,12 +496,17 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.widenScalarToNextPow2(1);

getActionDefinitionsBuilder(G_FPTOUI)
.legalFor(HasAVX512, {{s32, s32}, {s32, s64}, {s64, s32}, {s64, s64}})
.legalIf([=](const LegalityQuery &Query) {
return HasAVX512 && typeInSet(0, {s32, s64})(Query) &&
typeInSet(1, {s32, s64})(Query);
})
Comment on lines +509 to +512
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@e-kud e-kud Oct 26, 2025

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I think it is the part of code before refactoring legalizer to legalFor usage. We should be fine with existing legalFor.

.customIf([=](const LegalityQuery &Query) {
return !HasAVX512 &&
((HasSSE1 && typeIs(1, s32)(Query)) ||
(HasSSE2 && typeIs(1, s64)(Query))) &&
scalarNarrowerThan(0, Is64Bit ? 64 : 32)(Query);
if (!HasAVX512 && (((typeIs(1, s32)(Query) && HasSSE1) ||
(typeIs(1, s64)(Query) && HasSSE2)) &&
scalarNarrowerThan(0, Is64Bit ? 64 : 32)(Query)))
return true;
return typeInSet(0, {s16, s32, s64})(Query) &&
typeInSet(1, {s32, s64, s80})(Query);
})
// TODO: replace with customized legalization using
// specifics of cvttsd2si. The selection of this node requires
Expand All @@ -513,7 +518,7 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
(HasSSE2 && typeIs(1, s64)(Query))) &&
(Is64Bit && typeIs(0, s64)(Query));
})
.clampScalar(0, s32, sMaxScalar)
.clampScalar(0, s16, sMaxScalar)
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@e-kud e-kud Oct 26, 2025

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Maybe clamp to s16 only if no SSE available?

.widenScalarToNextPow2(0)
.clampScalar(1, s32, HasSSE2 ? s64 : s32)
.widenScalarToNextPow2(1);
Expand Down Expand Up @@ -744,7 +749,68 @@ bool X86LegalizerInfo::legalizeFPTOUI(MachineInstr &MI,
return true;
}

return false;
MachineFunction &MF = *MI.getMF();
TypeSize MemSize = DstTy.getSizeInBytes();
MachinePointerInfo PtrInfo;
Align Alignmt = Helper.getStackTemporaryAlignment(DstTy);
auto SlotPointer = Helper.createStackTemporary(MemSize, Alignmt, PtrInfo);

if (DstTy == s64) {
// As x87 cmov is unsupported at the momement, we need to use the following
// arithmatic algorithm to do fptoui computation. y_tmp = y - sint_max.
// y_res = fptosi(y - !sign(y_tmp)sint_max) + !sign(y_tmp)sint_max

const LLT s1 = LLT::scalar(1);
const LLT s80 = LLT::scalar(80);
const llvm::fltSemantics &Sem =
(SrcTy != s80 ? getFltSemanticForLLT(SrcTy)
: APFloat::x87DoubleExtended());

APFloat SintMaxFP = APFloat::getZero(Sem);
SintMaxFP.convertFromAPInt(APInt::getOneBitSet(64, 63), false,
APFloat::rmNearestTiesToEven);
Register SintMax = MIRBuilder.buildFConstant(SrcTy, SintMaxFP).getReg(0);

Register YTmp = MIRBuilder.buildFSub(SrcTy, Src, SintMax).getReg(0);

APFloat ZeroFP = APFloat::getZero(Sem);
Register Zero = MIRBuilder.buildFConstant(SrcTy, ZeroFP).getReg(0);
Register Sign =
MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, s1, YTmp, Zero).getReg(0);

Register One = MIRBuilder.buildConstant(s1, 1).getReg(0);
Register NSign = MIRBuilder.buildXor(s1, Sign, One).getReg(0);

Register NSign64 = MIRBuilder.buildZExt(s64, NSign).getReg(0);

Register NSignF = MIRBuilder.buildSITOFP(SrcTy, NSign64).getReg(0);
Register Offset = MIRBuilder.buildFMul(SrcTy, NSignF, SintMax).getReg(0);

Register YAdj = MIRBuilder.buildFSub(SrcTy, Src, Offset).getReg(0);

Register YAdjI = MIRBuilder.buildFPTOSI(s64, YAdj).getReg(0);

Register OffsetI = MIRBuilder.buildFPTOSI(s64, Offset).getReg(0);

Register Result = MIRBuilder.buildAdd(s64, YAdjI, OffsetI).getReg(0);

MIRBuilder.buildCopy(Dst, Result);
MI.eraseFromParent();
return true;
}

MachineMemOperand *StoreMMO = MF.getMachineMemOperand(
PtrInfo, MachineMemOperand::MOStore, MemSize, Align(MemSize));

MIRBuilder.buildInstr(X86::G_FIST)
.addUse(Src)
.addUse(SlotPointer.getReg(0))
.addMemOperand(StoreMMO);

MIRBuilder.buildLoad(Dst, SlotPointer, PtrInfo, Align(MemSize));
MI.eraseFromParent();

return true;
}

bool X86LegalizerInfo::legalizeUITOFP(MachineInstr &MI,
Expand Down
111 changes: 49 additions & 62 deletions llvm/test/CodeGen/X86/isel-fp-to-int.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -18,18 +18,22 @@ define i64 @test_double_to_ui64(double %x) {
;
; GISEL-X64-LABEL: test_double_to_ui64:
; GISEL-X64: # %bb.0: # %entry
; GISEL-X64-NEXT: cvttsd2si %xmm0, %rcx
; GISEL-X64-NEXT: movsd {{.*#+}} xmm1 = [9.2233720368547758E+18,0.0E+0]
; GISEL-X64-NEXT: movapd %xmm0, %xmm2
; GISEL-X64-NEXT: subsd %xmm1, %xmm2
; GISEL-X64-NEXT: cvttsd2si %xmm2, %rdx
; GISEL-X64-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
; GISEL-X64-NEXT: xorq %rdx, %rax
; GISEL-X64-NEXT: xorl %edx, %edx
; GISEL-X64-NEXT: ucomisd %xmm1, %xmm0
; GISEL-X64-NEXT: setb %dl
; GISEL-X64-NEXT: andl $1, %edx
; GISEL-X64-NEXT: cmovneq %rcx, %rax
; GISEL-X64-NEXT: movsd {{.*#+}} xmm3 = [0.0E+0,0.0E+0]
; GISEL-X64-NEXT: ucomisd %xmm2, %xmm3
; GISEL-X64-NEXT: seta %al
; GISEL-X64-NEXT: xorb $1, %al
; GISEL-X64-NEXT: movzbl %al, %eax
; GISEL-X64-NEXT: andq $1, %rax
; GISEL-X64-NEXT: xorps %xmm2, %xmm2
; GISEL-X64-NEXT: cvtsi2sd %rax, %xmm2
; GISEL-X64-NEXT: mulsd %xmm1, %xmm2
; GISEL-X64-NEXT: subsd %xmm2, %xmm0
; GISEL-X64-NEXT: cvttsd2si %xmm0, %rcx
; GISEL-X64-NEXT: cvttsd2si %xmm2, %rax
; GISEL-X64-NEXT: addq %rcx, %rax
; GISEL-X64-NEXT: retq
;
; AVX512-LABEL: test_double_to_ui64:
Expand Down Expand Up @@ -64,17 +68,11 @@ define zeroext i16 @test_double_to_ui16(double %x) {
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq
;
; SDAG-AVX512-LABEL: test_double_to_ui16:
; SDAG-AVX512: # %bb.0: # %entry
; SDAG-AVX512-NEXT: vcvttsd2si %xmm0, %eax
; SDAG-AVX512-NEXT: # kill: def $ax killed $ax killed $eax
; SDAG-AVX512-NEXT: retq
;
; GISEL-AVX512-LABEL: test_double_to_ui16:
; GISEL-AVX512: # %bb.0: # %entry
; GISEL-AVX512-NEXT: vcvttsd2usi %xmm0, %eax
; GISEL-AVX512-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-AVX512-NEXT: retq
; AVX512-LABEL: test_double_to_ui16:
; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vcvttsd2si %xmm0, %eax
; AVX512-NEXT: # kill: def $ax killed $ax killed $eax
; AVX512-NEXT: retq
entry:
%conv = fptoui double %x to i16
ret i16 %conv
Expand All @@ -87,17 +85,11 @@ define zeroext i8 @test_double_to_ui8(double %x) {
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
; SDAG-AVX512-LABEL: test_double_to_ui8:
; SDAG-AVX512: # %bb.0: # %entry
; SDAG-AVX512-NEXT: vcvttsd2si %xmm0, %eax
; SDAG-AVX512-NEXT: # kill: def $al killed $al killed $eax
; SDAG-AVX512-NEXT: retq
;
; GISEL-AVX512-LABEL: test_double_to_ui8:
; GISEL-AVX512: # %bb.0: # %entry
; GISEL-AVX512-NEXT: vcvttsd2usi %xmm0, %eax
; GISEL-AVX512-NEXT: # kill: def $al killed $al killed $eax
; GISEL-AVX512-NEXT: retq
; AVX512-LABEL: test_double_to_ui8:
; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vcvttsd2si %xmm0, %eax
; AVX512-NEXT: # kill: def $al killed $al killed $eax
; AVX512-NEXT: retq
entry:
%conv = fptoui double %x to i8
ret i8 %conv
Expand All @@ -117,18 +109,22 @@ define i64 @test_float_to_ui64(float %x) {
;
; GISEL-X64-LABEL: test_float_to_ui64:
; GISEL-X64: # %bb.0: # %entry
; GISEL-X64-NEXT: cvttss2si %xmm0, %rcx
; GISEL-X64-NEXT: movss {{.*#+}} xmm1 = [9.22337203E+18,0.0E+0,0.0E+0,0.0E+0]
; GISEL-X64-NEXT: movaps %xmm0, %xmm2
; GISEL-X64-NEXT: subss %xmm1, %xmm2
; GISEL-X64-NEXT: cvttss2si %xmm2, %rdx
; GISEL-X64-NEXT: movabsq $-9223372036854775808, %rax # imm = 0x8000000000000000
; GISEL-X64-NEXT: xorq %rdx, %rax
; GISEL-X64-NEXT: xorl %edx, %edx
; GISEL-X64-NEXT: ucomiss %xmm1, %xmm0
; GISEL-X64-NEXT: setb %dl
; GISEL-X64-NEXT: andl $1, %edx
; GISEL-X64-NEXT: cmovneq %rcx, %rax
; GISEL-X64-NEXT: movss {{.*#+}} xmm3 = [0.0E+0,0.0E+0,0.0E+0,0.0E+0]
; GISEL-X64-NEXT: ucomiss %xmm2, %xmm3
; GISEL-X64-NEXT: seta %al
; GISEL-X64-NEXT: xorb $1, %al
; GISEL-X64-NEXT: movzbl %al, %eax
; GISEL-X64-NEXT: andq $1, %rax
; GISEL-X64-NEXT: xorps %xmm2, %xmm2
; GISEL-X64-NEXT: cvtsi2ss %rax, %xmm2
; GISEL-X64-NEXT: mulss %xmm1, %xmm2
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@pawan-nirpal-031 pawan-nirpal-031 Aug 27, 2025

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Legalizer rules need fixing.

; GISEL-X64-NEXT: subss %xmm2, %xmm0
; GISEL-X64-NEXT: cvttss2si %xmm0, %rcx
; GISEL-X64-NEXT: cvttss2si %xmm2, %rax
; GISEL-X64-NEXT: addq %rcx, %rax
; GISEL-X64-NEXT: retq
;
; AVX512-LABEL: test_float_to_ui64:
Expand Down Expand Up @@ -163,17 +159,11 @@ define zeroext i16 @test_float_to_ui16(float %x) {
; X64-NEXT: # kill: def $ax killed $ax killed $eax
; X64-NEXT: retq
;
; SDAG-AVX512-LABEL: test_float_to_ui16:
; SDAG-AVX512: # %bb.0: # %entry
; SDAG-AVX512-NEXT: vcvttss2si %xmm0, %eax
; SDAG-AVX512-NEXT: # kill: def $ax killed $ax killed $eax
; SDAG-AVX512-NEXT: retq
;
; GISEL-AVX512-LABEL: test_float_to_ui16:
; GISEL-AVX512: # %bb.0: # %entry
; GISEL-AVX512-NEXT: vcvttss2usi %xmm0, %eax
; GISEL-AVX512-NEXT: # kill: def $ax killed $ax killed $eax
; GISEL-AVX512-NEXT: retq
; AVX512-LABEL: test_float_to_ui16:
; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vcvttss2si %xmm0, %eax
; AVX512-NEXT: # kill: def $ax killed $ax killed $eax
; AVX512-NEXT: retq
entry:
%conv = fptoui float %x to i16
ret i16 %conv
Expand All @@ -186,17 +176,11 @@ define zeroext i8 @test_float_to_ui8(float %x) {
; X64-NEXT: # kill: def $al killed $al killed $eax
; X64-NEXT: retq
;
; SDAG-AVX512-LABEL: test_float_to_ui8:
; SDAG-AVX512: # %bb.0: # %entry
; SDAG-AVX512-NEXT: vcvttss2si %xmm0, %eax
; SDAG-AVX512-NEXT: # kill: def $al killed $al killed $eax
; SDAG-AVX512-NEXT: retq
;
; GISEL-AVX512-LABEL: test_float_to_ui8:
; GISEL-AVX512: # %bb.0: # %entry
; GISEL-AVX512-NEXT: vcvttss2usi %xmm0, %eax
; GISEL-AVX512-NEXT: # kill: def $al killed $al killed $eax
; GISEL-AVX512-NEXT: retq
; AVX512-LABEL: test_float_to_ui8:
; AVX512: # %bb.0: # %entry
; AVX512-NEXT: vcvttss2si %xmm0, %eax
; AVX512-NEXT: # kill: def $al killed $al killed $eax
; AVX512-NEXT: retq
entry:
%conv = fptoui float %x to i8
ret i8 %conv
Expand Down Expand Up @@ -389,3 +373,6 @@ entry:
%conv = fptosi float %x to i33
ret i33 %conv
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GISEL-AVX512: {{.*}}
; SDAG-AVX512: {{.*}}
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