From 1711bb368e75d0e764cec3bc9a979f153f5e1800 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 27 Aug 2025 12:33:59 +0100 Subject: [PATCH] [X86] canCreateUndefOrPoisonForTargetNode - add SSE bit logic + VPTERNLOG handling Basic bitlogic operations don't create undef/poison. Its proving really annoying to create proper test coverage for these specific opcodes as they tend to appear in later stages - their presence does help in some upcoming patches (e.g. #152107) and I'd prefer to get them committed early. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9a3e79569df50..ab21cf534b304 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -45150,6 +45150,14 @@ bool X86TargetLowering::canCreateUndefOrPoisonForTargetNode( bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const { switch (Op.getOpcode()) { + // SSE bit logic. + case X86ISD::FAND: + case X86ISD::FOR: + case X86ISD::FXOR: + case X86ISD::FANDN: + case X86ISD::ANDNP: + case X86ISD::VPTERNLOG: + return false; // SSE vector insert/extracts use modulo indices. case X86ISD::PINSRB: case X86ISD::PINSRW: