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[ARM][AArch64] Custom Lower abds and abd on ARM and AArch64 #155884

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55ceda5
Pre-commit tests (NFC)
AZero13 Aug 28, 2025
13f2a7b
[ARM][AArch64] Custom Lower ABDS and ABDU
AZero13 Aug 28, 2025
9edf3c2
Fixes
AZero13 Aug 30, 2025
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42 changes: 40 additions & 2 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Expand Up @@ -698,6 +698,11 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ABS, MVT::i64, Custom);
}

setOperationAction(ISD::ABDS, MVT::i32, Custom);
setOperationAction(ISD::ABDS, MVT::i64, Custom);
setOperationAction(ISD::ABDU, MVT::i32, Custom);
setOperationAction(ISD::ABDU, MVT::i64, Custom);

setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
Expand Down Expand Up @@ -7200,6 +7205,40 @@ SDValue AArch64TargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {
getCondCode(DAG, AArch64CC::PL), Cmp.getValue(1));
}

// Generate SUBS and CNEG for absolute difference.
SDValue AArch64TargetLowering::LowerABD(SDValue Op, SelectionDAG &DAG) const {
MVT VT = Op.getSimpleValueType();

if (VT.isVector()) {
if (Op.getOpcode() == ISD::ABDS)
return LowerToPredicatedOp(Op, DAG, AArch64ISD::ABDS_PRED);
else
return LowerToPredicatedOp(Op, DAG, AArch64ISD::ABDU_PRED);
}

SDLoc DL(Op);
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);

// Generate SUBS and CSEL for absolute difference (like LowerABS)
// Compute a - b with flags
SDValue Cmp =
DAG.getNode(AArch64ISD::SUBS, DL, DAG.getVTList(VT, FlagsVT), LHS, RHS);

// Compute b - a (negative of a - b)
SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
Cmp.getValue(0));

// For unsigned: use HS (a >= b) to select a-b, otherwise b-a
// For signed: use GE (a >= b) to select a-b, otherwise b-a
AArch64CC::CondCode CC =
(Op.getOpcode() == ISD::ABDS) ? AArch64CC::PL : AArch64CC::HS;

// CSEL: if a > b, select a-b, otherwise b-a
return DAG.getNode(AArch64ISD::CSEL, DL, VT, Cmp.getValue(0), Neg,
getCondCode(DAG, CC), Cmp.getValue(1));
}

static SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
SDValue Chain = Op.getOperand(0);
SDValue Cond = Op.getOperand(1);
Expand Down Expand Up @@ -7649,9 +7688,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
case ISD::ABS:
return LowerABS(Op, DAG);
case ISD::ABDS:
return LowerToPredicatedOp(Op, DAG, AArch64ISD::ABDS_PRED);
case ISD::ABDU:
return LowerToPredicatedOp(Op, DAG, AArch64ISD::ABDU_PRED);
return LowerABD(Op, DAG);
case ISD::AVGFLOORS:
return LowerAVG(Op, DAG, AArch64ISD::HADDS_PRED);
case ISD::AVGFLOORU:
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.h
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Expand Up @@ -598,6 +598,7 @@ class AArch64TargetLowering : public TargetLowering {
SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerABD(SDValue Op, SelectionDAG &DAG) const;

SDValue LowerMGATHER(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerMSCATTER(SDValue Op, SelectionDAG &DAG) const;
Expand Down
81 changes: 81 additions & 0 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Expand Up @@ -647,6 +647,10 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM_,
if (!Subtarget->hasV8_1MMainlineOps())
setOperationAction(ISD::UCMP, MVT::i32, Custom);

setOperationAction(ISD::ABS, MVT::i32, Custom);
setOperationAction(ISD::ABDS, MVT::i32, Custom);
setOperationAction(ISD::ABDU, MVT::i32, Custom);

setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
setOperationAction(ISD::ConstantFP, MVT::f64, Custom);

Expand Down Expand Up @@ -5621,6 +5625,78 @@ ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
return SDValue();
}

// Generate SUBS and CSEL for integer abs.
SDValue ARMTargetLowering::LowerABS(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
// Thumb1-only sequence:
// asrs r1, r0, #31; eors r0, r1; subs r0, r0, r1
if (Subtarget->isThumb1Only()) {
SDValue X = Op.getOperand(0);
SDValue ShiftAmt = DAG.getConstant(31, DL, MVT::i32);
SDValue S = DAG.getNode(ISD::SRA, DL, MVT::i32, X, ShiftAmt);
SDValue T = DAG.getNode(ISD::XOR, DL, MVT::i32, X, S);
return DAG.getNode(ISD::SUB, DL, MVT::i32, T, S);
}
SDValue Neg = DAG.getNode(ISD::SUB, DL, MVT::i32,
DAG.getConstant(0, DL, MVT::i32), Op.getOperand(0));
// Generate SUBS & CSEL.
SDValue Cmp = DAG.getNode(ARMISD::CMP, DL, FlagsVT, Op.getOperand(0),
DAG.getConstant(0, DL, MVT::i32));
return DAG.getNode(ARMISD::CMOV, DL, MVT::i32, Op.getOperand(0), Neg,
DAG.getConstant(ARMCC::MI, DL, MVT::i32), Cmp);
}

// Generate SUBS and CNEG for absolute difference.
SDValue ARMTargetLowering::LowerABD(SDValue Op, SelectionDAG &DAG) const {
SDLoc DL(Op);
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);

// Thumb1-only custom sequences for i32
if (Subtarget->isThumb1Only()) {
if (Op.getOpcode() == ISD::ABDS) {
// subs r0, r0, r1; asrs r1, r0, #31; eors r0, r1; subs r0, r0, r1
SDValue D = DAG.getNode(ISD::SUB, DL, MVT::i32, LHS, RHS);
SDValue ShiftAmt = DAG.getConstant(31, DL, MVT::i32);
SDValue S = DAG.getNode(ISD::SRA, DL, MVT::i32, D, ShiftAmt);
SDValue T = DAG.getNode(ISD::XOR, DL, MVT::i32, D, S);
return DAG.getNode(ISD::SUB, DL, MVT::i32, T, S);
} else {
// abdu: subs; sbcs r1,r1,r1(mask from borrow); eors; subs
// First subtraction: LHS - RHS
SDValue Sub1WithFlags = DAG.getNode(
ARMISD::SUBC, DL, DAG.getVTList(MVT::i32, FlagsVT), LHS, RHS);
SDValue Sub1Result = Sub1WithFlags.getValue(0);
SDValue Flags1 = Sub1WithFlags.getValue(1);

SDValue Sbc1 = DAG.getNode(
ARMISD::SUBE, DL, DAG.getVTList(MVT::i32, FlagsVT), RHS, RHS, Flags1);

SDValue Xor =
DAG.getNode(ISD::XOR, DL, MVT::i32, Sub1Result, Sbc1.getValue(0));

return DAG.getNode(ISD::SUB, DL, MVT::i32, Xor, Sbc1.getValue(0));
}
}

// Generate SUBS and CSEL for absolute difference (like LowerABS)
// Compute a - b with flags
SDValue Cmp =
DAG.getNode(ARMISD::SUBC, DL, DAG.getVTList(MVT::i32, FlagsVT), LHS, RHS);

// Compute b - a (negative of a - b)
SDValue Neg = DAG.getNode(ISD::SUB, DL, MVT::i32,
DAG.getConstant(0, DL, MVT::i32), Cmp.getValue(0));

// For unsigned: use HS (a >= b) to select a-b, otherwise b-a
// For signed: use GE (a >= b) to select a-b, otherwise b-a
ARMCC::CondCodes CC = (Op.getOpcode() == ISD::ABDS) ? ARMCC::MI : ARMCC::LO;

// CSEL: if a > b, select a-b, otherwise b-a
return DAG.getNode(ARMISD::CMOV, DL, MVT::i32, Cmp.getValue(0), Neg,
DAG.getConstant(CC, DL, MVT::i32), Cmp.getValue(1));
}

SDValue ARMTargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
SDValue Chain = Op.getOperand(0);
SDValue Cond = Op.getOperand(1);
Expand Down Expand Up @@ -10670,6 +10746,11 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
return LowerSTORE(Op, DAG, Subtarget);
case ISD::MLOAD:
return LowerMLOAD(Op, DAG);
case ISD::ABS:
return LowerABS(Op, DAG);
case ISD::ABDS:
case ISD::ABDU:
return LowerABD(Op, DAG);
case ISD::VECREDUCE_MUL:
case ISD::VECREDUCE_AND:
case ISD::VECREDUCE_OR:
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/ARM/ARMISelLowering.h
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Expand Up @@ -888,6 +888,9 @@ class VectorType;
SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;

SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerABD(SDValue Op, SelectionDAG &DAG) const;
void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
SmallVectorImpl<SDValue> &Results) const;
SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG,
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/Analysis/CostModel/ARM/mve-abs.ll
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Expand Up @@ -31,22 +31,22 @@ declare <64 x i8> @llvm.abs.v64i8(<64 x i8>, i1)

define i32 @abs(i32 %arg) {
; MVE-LABEL: 'abs'
; MVE-NEXT: Cost Model: Found costs of RThru:5 CodeSize:6 Lat:5 SizeLat:5 for: %I64 = call i64 @llvm.abs.i64(i64 undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of 4 for: %I64 = call i64 @llvm.abs.i64(i64 undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:74 CodeSize:55 Lat:74 SizeLat:74 for: %V2I64 = call <2 x i64> @llvm.abs.v2i64(<2 x i64> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:148 CodeSize:110 Lat:148 SizeLat:148 for: %V4I64 = call <4 x i64> @llvm.abs.v4i64(<4 x i64> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:296 CodeSize:220 Lat:296 SizeLat:296 for: %V8I64 = call <8 x i64> @llvm.abs.v8i64(<8 x i64> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I32 = call i32 @llvm.abs.i32(i32 undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I32 = call i32 @llvm.abs.i32(i32 undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:29 Lat:40 SizeLat:40 for: %V2I32 = call <2 x i32> @llvm.abs.v2i32(<2 x i32> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I32 = call <4 x i32> @llvm.abs.v4i32(<4 x i32> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V8I32 = call <8 x i32> @llvm.abs.v8i32(<8 x i32> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %V16I32 = call <16 x i32> @llvm.abs.v16i32(<16 x i32> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I16 = call i16 @llvm.abs.i16(i16 undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I16 = call i16 @llvm.abs.i16(i16 undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:29 Lat:40 SizeLat:40 for: %V2I16 = call <2 x i16> @llvm.abs.v2i16(<2 x i16> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I16 = call <4 x i16> @llvm.abs.v4i16(<4 x i16> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V8I16 = call <8 x i16> @llvm.abs.v8i16(<8 x i16> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:4 CodeSize:2 Lat:4 SizeLat:4 for: %V16I16 = call <16 x i16> @llvm.abs.v16i16(<16 x i16> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:8 CodeSize:4 Lat:8 SizeLat:8 for: %V32I16 = call <32 x i16> @llvm.abs.v32i16(<32 x i16> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:3 CodeSize:4 Lat:3 SizeLat:3 for: %I8 = call i8 @llvm.abs.i8(i8 undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of 2 for: %I8 = call i8 @llvm.abs.i8(i8 undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:40 CodeSize:29 Lat:40 SizeLat:40 for: %V2I8 = call <2 x i8> @llvm.abs.v2i8(<2 x i8> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V4I8 = call <4 x i8> @llvm.abs.v4i8(<4 x i8> undef, i1 false)
; MVE-NEXT: Cost Model: Found costs of RThru:2 CodeSize:1 Lat:2 SizeLat:2 for: %V8I8 = call <8 x i8> @llvm.abs.v8i8(<8 x i8> undef, i1 false)
Expand Down
59 changes: 24 additions & 35 deletions llvm/test/CodeGen/AArch64/abds-neg.ll
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Expand Up @@ -73,8 +73,8 @@ define i16 @abd_ext_i16_i32(i16 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i16_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: subs w8, w1, w8
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: subs w8, w8, w1
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = sext i16 %a to i64
%bext = sext i32 %b to i64
Expand Down Expand Up @@ -104,8 +104,8 @@ define i16 @abd_ext_i16_undef(i16 %a, i16 %b) nounwind {
define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i32 %b to i64
Expand All @@ -119,9 +119,8 @@ define i32 @abd_ext_i32(i32 %a, i32 %b) nounwind {
define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: subs w8, w8, w0
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: subs w8, w0, w1, sxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i16 %b to i64
Expand All @@ -135,8 +134,8 @@ define i32 @abd_ext_i32_i16(i32 %a, i16 %b) nounwind {
define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_ext_i32_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w1, w0
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%aext = sext i32 %a to i64
%bext = sext i32 %b to i64
Expand All @@ -150,8 +149,8 @@ define i32 @abd_ext_i32_undef(i32 %a, i32 %b) nounwind {
define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, ge
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, pl
; CHECK-NEXT: ret
%aext = sext i64 %a to i128
%bext = sext i64 %b to i128
Expand All @@ -165,8 +164,8 @@ define i64 @abd_ext_i64(i64 %a, i64 %b) nounwind {
define i64 @abd_ext_i64_undef(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_ext_i64_undef:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x1, x0
; CHECK-NEXT: cneg x0, x8, ge
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, pl
; CHECK-NEXT: ret
%aext = sext i64 %a to i128
%bext = sext i64 %b to i128
Expand Down Expand Up @@ -226,12 +225,9 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
; CHECK-LABEL: abd_minmax_i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sxtb w8, w1
; CHECK-NEXT: sxtb w9, w0
; CHECK-NEXT: cmp w9, w8
; CHECK-NEXT: csel w10, w9, w8, lt
; CHECK-NEXT: csel w8, w9, w8, gt
; CHECK-NEXT: sub w0, w10, w8
; CHECK-NEXT: sxtb w8, w0
; CHECK-NEXT: subs w8, w8, w1, sxtb
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%min = call i8 @llvm.smin.i8(i8 %a, i8 %b)
%max = call i8 @llvm.smax.i8(i8 %a, i8 %b)
Expand All @@ -242,12 +238,9 @@ define i8 @abd_minmax_i8(i8 %a, i8 %b) nounwind {
define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
; CHECK-LABEL: abd_minmax_i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: sxth w9, w0
; CHECK-NEXT: cmp w9, w8
; CHECK-NEXT: csel w10, w9, w8, lt
; CHECK-NEXT: csel w8, w9, w8, gt
; CHECK-NEXT: sub w0, w10, w8
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: subs w8, w8, w1, sxth
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%min = call i16 @llvm.smin.i16(i16 %a, i16 %b)
%max = call i16 @llvm.smax.i16(i16 %a, i16 %b)
Expand All @@ -258,10 +251,8 @@ define i16 @abd_minmax_i16(i16 %a, i16 %b) nounwind {
define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_minmax_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: csel w8, w0, w1, lt
; CHECK-NEXT: csel w9, w0, w1, gt
; CHECK-NEXT: sub w0, w8, w9
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%min = call i32 @llvm.smin.i32(i32 %a, i32 %b)
%max = call i32 @llvm.smax.i32(i32 %a, i32 %b)
Expand All @@ -272,10 +263,8 @@ define i32 @abd_minmax_i32(i32 %a, i32 %b) nounwind {
define i64 @abd_minmax_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_minmax_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: cmp x0, x1
; CHECK-NEXT: csel x8, x0, x1, lt
; CHECK-NEXT: csel x9, x0, x1, gt
; CHECK-NEXT: sub x0, x8, x9
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, pl
; CHECK-NEXT: ret
%min = call i64 @llvm.smin.i64(i64 %a, i64 %b)
%max = call i64 @llvm.smax.i64(i64 %a, i64 %b)
Expand Down Expand Up @@ -343,7 +332,7 @@ define i32 @abd_cmp_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: abd_cmp_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: subs w8, w0, w1
; CHECK-NEXT: cneg w0, w8, ge
; CHECK-NEXT: cneg w0, w8, pl
; CHECK-NEXT: ret
%cmp = icmp sge i32 %a, %b
%ab = sub i32 %a, %b
Expand All @@ -356,7 +345,7 @@ define i64 @abd_cmp_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: abd_cmp_i64:
; CHECK: // %bb.0:
; CHECK-NEXT: subs x8, x0, x1
; CHECK-NEXT: cneg x0, x8, ge
; CHECK-NEXT: cneg x0, x8, pl
; CHECK-NEXT: ret
%cmp = icmp slt i64 %a, %b
%ab = sub i64 %a, %b
Expand Down
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