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[Headers][X86] Add constexpr support for some AVX[512] intrinsics. #156567
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[Headers][X86] Add constexpr support for some AVX[512] intrinsics. #156567
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You can test this locally with the following command:git-clang-format --diff origin/main HEAD --extensions h,c -- clang/lib/Headers/avx512dqintrin.h clang/lib/Headers/avx512vlintrin.h clang/test/CodeGen/X86/avx512dq-builtins.c clang/test/CodeGen/X86/avx512vl-builtins.c
View the diff from clang-format here.diff --git a/clang/lib/Headers/avx512dqintrin.h b/clang/lib/Headers/avx512dqintrin.h
index ee211d3ea..a8435d1cb 100644
--- a/clang/lib/Headers/avx512dqintrin.h
+++ b/clang/lib/Headers/avx512dqintrin.h
@@ -483,8 +483,8 @@ _mm512_maskz_cvtps_epu64 (__mmask8 __U, __m256 __A) {
(__v8di)_mm512_setzero_si512(), \
(__mmask8)(U), (int)(R)))
-static __inline__ __m512d __DEFAULT_FN_ATTRS512_CONSTEXPR
-_mm512_cvtepi64_pd(__m512i __A) {
+static __inline__ __m512d
+ __DEFAULT_FN_ATTRS512_CONSTEXPR _mm512_cvtepi64_pd(__m512i __A) {
return (__m512d)__builtin_convertvector((__v8di)__A, __v8df);
}
@@ -713,8 +713,8 @@ _mm512_maskz_cvttps_epu64 (__mmask8 __U, __m256 __A) {
(__v8di)_mm512_setzero_si512(), \
(__mmask8)(U), (int)(R)))
-static __inline__ __m512d __DEFAULT_FN_ATTRS512_CONSTEXPR
-_mm512_cvtepu64_pd(__m512i __A) {
+static __inline__ __m512d
+ __DEFAULT_FN_ATTRS512_CONSTEXPR _mm512_cvtepu64_pd(__m512i __A) {
return (__m512d)__builtin_convertvector((__v8du)__A, __v8df);
}
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@RKSimon |
No I don't think those are necessary changes tbh. |
RKSimon
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LGTM - cheers
…157260) The following AVX[512] intrinsics are now constexpr: - `_mm_cvtepi64_pd` - `_mm_mask_cvtepi64_pd` - `_mm_maskz_cvtepi64_pd` - `_mm_cvtepu64_pd` - `_mm_mask_cvtepu64_pd` - `_mm_maskz_cvtepu64_pd` - `_mm256_cvtepi64_pd` - `_mm256_mask_cvtepi64_pd` - `_mm256_maskz_cvtepi64_pd` - `_mm256_cvtepu64_pd` - `_mm256_mask_cvtepu64_pd` - `_mm256_maskz_cvtepu64_pd` - `_mm256_cvtepi64_ps` - `_mm256_mask_cvtepi64_ps` - `_mm256_maskz_cvtepi64_ps` - `_mm256_cvtepu64_ps` - `_mm256_mask_cvtepu64_ps` - `_mm256_maskz_cvtepu64_ps` - `_mm_cvtepi16_ph` - `_mm_mask_cvtepi16_ph` - `_mm_maskz_cvtepi16_ph` - `_mm_set1_ph` - `_mm_cvtepu16_ph` - `_mm_mask_cvtepu16_ph` - `_mm_maskz_cvtepu16_ph` - `_mm256_cvtepi16_ph` - `_mm256_mask_cvtepi16_ph` - `_mm256_set1_ph` - `_mm256_maskz_cvtepi16_ph` This PR is part 3 [[part 1](#156187) - [part 2](#156567)] of a series of PRs fixing #155798
…rinsics. (#157260) The following AVX[512] intrinsics are now constexpr: - `_mm_cvtepi64_pd` - `_mm_mask_cvtepi64_pd` - `_mm_maskz_cvtepi64_pd` - `_mm_cvtepu64_pd` - `_mm_mask_cvtepu64_pd` - `_mm_maskz_cvtepu64_pd` - `_mm256_cvtepi64_pd` - `_mm256_mask_cvtepi64_pd` - `_mm256_maskz_cvtepi64_pd` - `_mm256_cvtepu64_pd` - `_mm256_mask_cvtepu64_pd` - `_mm256_maskz_cvtepu64_pd` - `_mm256_cvtepi64_ps` - `_mm256_mask_cvtepi64_ps` - `_mm256_maskz_cvtepi64_ps` - `_mm256_cvtepu64_ps` - `_mm256_mask_cvtepu64_ps` - `_mm256_maskz_cvtepu64_ps` - `_mm_cvtepi16_ph` - `_mm_mask_cvtepi16_ph` - `_mm_maskz_cvtepi16_ph` - `_mm_set1_ph` - `_mm_cvtepu16_ph` - `_mm_mask_cvtepu16_ph` - `_mm_maskz_cvtepu16_ph` - `_mm256_cvtepi16_ph` - `_mm256_mask_cvtepi16_ph` - `_mm256_set1_ph` - `_mm256_maskz_cvtepi16_ph` This PR is part 3 [[part 1](llvm/llvm-project#156187) - [part 2](llvm/llvm-project#156567)] of a series of PRs fixing #155798
The following AVX[512] intrinsics are now constexpr:
_mm_mask_cvtepi32_pd_mm_maskz_cvtepi32_pd_mm_mask_cvtepi32_ps_mm_maskz_cvtepi32_ps_mm_cvtepu32_pd_mm_mask_cvtepu32_pd_mm_maskz_cvtepu32_pd_mm_cvtepu32_ps_mm_mask_cvtepu32_ps_mm_maskz_cvtepu32_ps_mm256_mask_cvtepi32_pd_mm256_maskz_cvtepi32_pd_mm256_mask_cvtepi32_ps_mm256_maskz_cvtepi32_ps_mm256_cvtepu32_pd_mm256_mask_cvtepu32_pd_mm256_maskz_cvtepu32_pd_mm256_cvtepu32_ps_mm256_mask_cvtepu32_ps_mm256_maskz_cvtepu32_ps_mm512_cvtepi64_pd_mm512_mask_cvtepi64_pd_mm512_maskz_cvtepi64_pd_mm512_cvtepu64_pd_mm512_mask_cvtepu64_pd_mm512_maskz_cvtepu64_pdThis PR is part 2 [part 1] of a series of PRs fixing #155798