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[ConstantFolding] Fold scalable get_active_lane_masks #156659

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Merged
merged 2 commits into from
Sep 11, 2025
Merged

[ConstantFolding] Fold scalable get_active_lane_masks #156659

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49833a2
[ConstantFolding] Fold scalable get_active_lane_masks
MDevereau Sep 3, 2025
042b029
Remove Op1.isZero() condition
MDevereau Sep 4, 2025
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7 changes: 7 additions & 0 deletions llvm/lib/Analysis/ConstantFolding.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4238,6 +4238,13 @@ static Constant *ConstantFoldScalableVectorCall(

return ConstantInt::getFalse(SVTy);
}
case Intrinsic::get_active_lane_mask: {
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@david-arm david-arm Sep 3, 2025

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I think we probably want to do this for fixed-width as well.

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@MDevereau MDevereau Sep 3, 2025

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As it stands, ConstantFolding can already handle this for fixed-width. Scalable seems to have been left behind: https://godbolt.org/z/snd7M5oer

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@david-arm david-arm Sep 3, 2025

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I see yeah, and as it stands the code in ConstantFoldFixedVectorCall is broken because it should return poison if Op1 is zero. Once the LangRef is fixed we can always revisit this.

auto Op0 = cast<ConstantInt>(Operands[0])->getValue();
auto Op1 = cast<ConstantInt>(Operands[1])->getValue();
Comment on lines +4242 to +4243
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@fhahn fhahn Sep 11, 2025

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This is currently causing crashes when the operands are constant expressions. I added checks to. make sure the operands are actually ConstantInts in 607a813 to avoid a revert.

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@MDevereau MDevereau Sep 12, 2025

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Thanks for that, much appreciated.

if ((Op0.uge(Op1) && (!Op1.isZero())))
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@davemgreen davemgreen Sep 4, 2025

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I don't think this needs a check for Op1.isZero. It is perfectly valid to refine poison to zero.

It would be converting the whilelo -> get_active_lane_mask that would be invalid, if zero produced poison, as it converts from zero->poison.

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@davemgreen davemgreen Sep 4, 2025

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(This also has many more brackets than necessary, you can drop a few).

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@david-arm david-arm Sep 4, 2025

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Doesn't that mean that if add nsw i64 %v1, %v2 or getelementptr inbounds ..., etc. are known to produce poison we can just return any other value that we think makes sense too? At the IR level the choice of a zero value here is completely arbitrary (since the LangRef explicitly says the result is poison, not zero), but what if a completely different IR pass decides it can prove Op1 is zero via other means (via computed bits analysis, etc) and decides to return another completely arbitrary value following the same logic, e.g. 1? Wouldn't we then be in a situation where two calls to get.active.lane.mask with an operand of 0 return different non-poison results?

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@davemgreen davemgreen Sep 4, 2025

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Yep, poison propagates so if it is not frozen it can have different values at different places.
https://llvm.org/docs/LangRef.html#poison-values
Producing all-ones would be valid (if it was poison), but not as useful.

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@MDevereau MDevereau Sep 4, 2025

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Makes sense, I've removed the Op1.isZero check

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@david-arm david-arm Sep 4, 2025

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Fair enough, thanks for explaining @davemgreen!

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@paulwalker-arm paulwalker-arm Sep 4, 2025

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I'm not sure the poison conversation is necessarily correct. Whilst you are allowed to remove sources of poison I think when the IR is statically known to be poison the poison should be propagated.

@nikic / @fhahn : Can either of you confirm one way or the other?

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@paulwalker-arm paulwalker-arm Sep 10, 2025

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@MDevereau: I've just landed #152140, which removes the poison corner case.

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@MDevereau MDevereau Sep 10, 2025

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@paulwalker-arm Thanks. What I gather from that is it's now OK to assume active_lane_mask(0, 0) is an all false predicate just as active_lane_mask(3, 3) is and that no further changes are needed in this PR.

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@paulwalker-arm paulwalker-arm Sep 10, 2025

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Yep

return ConstantVector::getNullValue(SVTy);
break;
}
default:
break;
}
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34 changes: 34 additions & 0 deletions llvm/test/Transforms/InstSimplify/ConstProp/active-lane-mask.ll
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Expand Up @@ -307,6 +307,40 @@ entry:
ret <4 x float> %var33
}

define <vscale x 4 x i1> @nxv4i1_12_12() {
; CHECK-LABEL: @nxv4i1_12_12(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer
;
entry:
%mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 12, i32 12)
ret <vscale x 4 x i1> %mask
}

define <vscale x 4 x i1> @nxv4i1_8_4() {
; CHECK-LABEL: @nxv4i1_8_4(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret <vscale x 4 x i1> zeroinitializer
;
entry:
%mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 8, i32 4)
ret <vscale x 4 x i1> %mask
}

define <vscale x 16 x i1> @nxv16i1_0_0() {
; CHECK-LABEL: @nxv16i1_0_0(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 0)
; CHECK-NEXT: ret <vscale x 16 x i1> [[MASK]]
;
entry:
%mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 0)
ret <vscale x 16 x i1> %mask
}

declare <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32, i32)
declare <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32, i32)
declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)

declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32, i32)
declare <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv4i1.i64(i64, i64)
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