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2 changes: 1 addition & 1 deletion llvm/test/TableGen/def-multiple-operands.td
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ def Reg3Opnd : Operand<OtherVT> {
// CHECK: archInstrTable {{.* = \{}}
// CHECK: {{\{}}
// CHECK: {{\{}} [[ID:[0-9]+]], 4, 3, 13, {{.+\}, \/\/}}
// CHECK-SAME: Inst #[[ID]] = InstA
// CHECK-SAME: InstA
def InstA : Instruction {
let Namespace = "MyNS";
let Size = 13;
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12 changes: 6 additions & 6 deletions llvm/utils/TableGen/InstrInfoEmitter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -760,8 +760,9 @@ void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
OS << " };\n"
<< " static constexpr " << getMinimalTypeForRange(FeatureBitsets.size())
<< " RequiredFeaturesRefs[] = {\n";
unsigned InstIdx = 0;
for (const CodeGenInstruction *Inst : Target.getInstructions()) {
ArrayRef<const CodeGenInstruction *> NumberedInstructions =
Target.getInstructions();
for (const CodeGenInstruction *Inst : NumberedInstructions) {
OS << " CEFBS";
unsigned NumPredicates = 0;
for (const Record *Predicate :
Expand All @@ -774,11 +775,10 @@ void InstrInfoEmitter::emitFeatureVerifier(raw_ostream &OS,
}
if (!NumPredicates)
OS << "_None";
OS << ", // " << Inst->TheDef->getName() << " = " << InstIdx << '\n';
InstIdx++;
OS << ", // " << Inst->TheDef->getName() << '\n';
}
OS << " };\n\n"
<< " assert(Opcode < " << InstIdx << ");\n"
<< " assert(Opcode < " << NumberedInstructions.size() << ");\n"
<< " return FeatureBitsets[RequiredFeaturesRefs[Opcode]];\n"
<< "}\n\n";

Expand Down Expand Up @@ -1284,7 +1284,7 @@ void InstrInfoEmitter::emitRecord(
OS.write_hex(Value);
OS << "ULL";

OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << '\n';
OS << " }, // " << Inst.TheDef->getName() << '\n';
}

// emitEnums - Print out enum values for all of the instructions.
Expand Down