From 92afeb73ca2163463d1210471b2b1e14865f8c87 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Fri, 5 Sep 2025 20:16:04 -0700 Subject: [PATCH 1/8] [RISCV] Add lit test for testing machine outliner with LPAD --- .../CodeGen/RISCV/machine-outliner-lpad.ll | 51 +++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll new file mode 100644 index 0000000000000..8138464444a72 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll @@ -0,0 +1,51 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV64 + +define i32 @test1() #0 { +; CHECK-LABEL: test1: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +entry: + ret i32 0 +} + +define i32 @test2() #0 { +; CHECK-LABEL: test2: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +entry: + ret i32 0 +} + +define i32 @test3() #0 { +; CHECK-LABEL: test3: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +entry: + ret i32 0 +} + +define i32 @test4() #0 { +; CHECK-LABEL: test4: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +entry: + ret i32 0 +} + +define i32 @main() #0 { +; CHECK-LABEL: main: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +entry: + ret i32 0 +} + +attributes #0 = { minsize } + +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 8, !"cf-protection-branch", i32 1} +!1 = !{i32 1, !"cf-branch-label-scheme", !"unlabeled"} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; RV64: {{.*}} From 8b75b85786831c881b6ef35ec33085d9a3946f37 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Thu, 4 Sep 2025 09:02:51 -0700 Subject: [PATCH 2/8] [RISCV] Exclude LPAD in machine outliner --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index ee6d6cdb00096..0d15ca27edb00 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3511,6 +3511,11 @@ RISCVInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI, return outliner::InstrType::Illegal; } + // LPADs should not be outlined too + if (MI.getOpcode() == RISCV::AUIPC && + MI.getOperand(0).getReg() == RISCV::X0) + return outliner::InstrType::Illegal; + return outliner::InstrType::Legal; } From 936bcca484c4eb9f63d9464466e14945b876b0cd Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Fri, 5 Sep 2025 20:30:16 -0700 Subject: [PATCH 3/8] Regen test --- .../CodeGen/RISCV/machine-outliner-lpad.ll | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll index 8138464444a72..9d5187c8c5f7c 100644 --- a/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll +++ b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll @@ -4,7 +4,9 @@ define i32 @test1() #0 { ; CHECK-LABEL: test1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +; CHECK-NEXT: lpad 0 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ret entry: ret i32 0 } @@ -12,7 +14,9 @@ entry: define i32 @test2() #0 { ; CHECK-LABEL: test2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +; CHECK-NEXT: lpad 0 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ret entry: ret i32 0 } @@ -20,7 +24,9 @@ entry: define i32 @test3() #0 { ; CHECK-LABEL: test3: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +; CHECK-NEXT: lpad 0 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ret entry: ret i32 0 } @@ -28,7 +34,9 @@ entry: define i32 @test4() #0 { ; CHECK-LABEL: test4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +; CHECK-NEXT: lpad 0 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ret entry: ret i32 0 } @@ -36,7 +44,9 @@ entry: define i32 @main() #0 { ; CHECK-LABEL: main: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: tail OUTLINED_FUNCTION_0 +; CHECK-NEXT: lpad 0 +; CHECK-NEXT: li a0, 0 +; CHECK-NEXT: ret entry: ret i32 0 } From 96f1bc04edf9fca5e3dd8dd418b40bd024f8443b Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Fri, 5 Sep 2025 20:57:47 -0700 Subject: [PATCH 4/8] fixup! clang-format --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 0d15ca27edb00..b2b25978a3fc3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3512,8 +3512,7 @@ RISCVInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI, } // LPADs should not be outlined too - if (MI.getOpcode() == RISCV::AUIPC && - MI.getOperand(0).getReg() == RISCV::X0) + if (MI.getOpcode() == RISCV::AUIPC && MI.getOperand(0).getReg() == RISCV::X0) return outliner::InstrType::Illegal; return outliner::InstrType::Legal; From a2ce04919d49886f8086f45cf2be429b18da2b7e Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 7 Sep 2025 23:29:25 -0700 Subject: [PATCH 5/8] Update test --- .../CodeGen/RISCV/machine-outliner-lpad.ll | 47 +++++++++++-------- 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll index 9d5187c8c5f7c..e65943ceae579 100644 --- a/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll +++ b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll @@ -1,54 +1,60 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV64 +; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV32 -define i32 @test1() #0 { +define i16 @test1(i16 %x) #0 { ; CHECK-LABEL: test1: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lpad 0 -; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: ret +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 entry: - ret i32 0 + %y = add i16 5, %x + %z = mul i16 4, %y + ret i16 %z } -define i32 @test2() #0 { +define i16 @test2(i16 %x) #0 { ; CHECK-LABEL: test2: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lpad 0 -; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: ret +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 entry: - ret i32 0 + %y = add i16 5, %x + %z = mul i16 4, %y + ret i16 %z } -define i32 @test3() #0 { +define i16 @test3(i16 %x) #0 { ; CHECK-LABEL: test3: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lpad 0 -; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: ret +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 entry: - ret i32 0 + %y = add i16 5, %x + %z = mul i16 4, %y + ret i16 %z } -define i32 @test4() #0 { +define i16 @test4(i16 %x) #0 { ; CHECK-LABEL: test4: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lpad 0 -; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: ret +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 entry: - ret i32 0 + %y = add i16 5, %x + %z = mul i16 4, %y + ret i16 %z } -define i32 @main() #0 { +define i16 @main(i16 %x) #0 { ; CHECK-LABEL: main: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lpad 0 -; CHECK-NEXT: li a0, 0 -; CHECK-NEXT: ret +; CHECK-NEXT: tail OUTLINED_FUNCTION_0 entry: - ret i32 0 + %y = add i16 5, %x + %z = mul i16 4, %y + ret i16 %z } attributes #0 = { minsize } @@ -58,4 +64,5 @@ attributes #0 = { minsize } !0 = !{i32 8, !"cf-protection-branch", i32 1} !1 = !{i32 1, !"cf-branch-label-scheme", !"unlabeled"} ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; RV32: {{.*}} ; RV64: {{.*}} From ab76d0f4001dd0bfc0adb840b05924e53678428a Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Sun, 7 Sep 2025 23:37:53 -0700 Subject: [PATCH 6/8] Make the checking of LPAD a predicate in RISCVInstrPredicate.td --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrPredicates.td | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index b2b25978a3fc3..6fd47c0839d54 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3512,7 +3512,7 @@ RISCVInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI, } // LPADs should not be outlined too - if (MI.getOpcode() == RISCV::AUIPC && MI.getOperand(0).getReg() == RISCV::X0) + if (isLPAD(MI)) return outliner::InstrType::Illegal; return outliner::InstrType::Legal; diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td index 4abe62f4e874c..64db61af307ac 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td +++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td @@ -148,6 +148,15 @@ def isNonZeroLoadImmediate CheckNot> ]>>>; +// Returns true if this is LPAD (auipc with rd = x0) +def isLPAD + : TIIPredicate<"isLPAD", + MCReturnStatement, + CheckIsRegOperand<0>, + CheckRegOperand<0, X0>, + ]>>>; + def ignoresVXRM : TIIPredicate<"ignoresVXRM", MCOpcodeSwitchStatement< From 158061789946309453f35498cba1402d23c989b1 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Mon, 8 Sep 2025 05:26:06 -0700 Subject: [PATCH 7/8] fix test --- llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll index e65943ceae579..bfeb8509766b9 100644 --- a/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll +++ b/llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV64 -; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK,RV32 +; RUN: llc -mtriple riscv64 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK +; RUN: llc -mtriple riscv32 -mattr=+experimental-zicfilp < %s | FileCheck %s --check-prefixes=CHECK define i16 @test1(i16 %x) #0 { ; CHECK-LABEL: test1: @@ -63,6 +63,3 @@ attributes #0 = { minsize } !0 = !{i32 8, !"cf-protection-branch", i32 1} !1 = !{i32 1, !"cf-branch-label-scheme", !"unlabeled"} -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; RV32: {{.*}} -; RV64: {{.*}} From 1e8eb67677ca4e62e066b1f957c580cd96fb4b12 Mon Sep 17 00:00:00 2001 From: Jesse Huang Date: Mon, 8 Sep 2025 21:21:29 -0700 Subject: [PATCH 8/8] Address comments --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 1 - llvm/lib/Target/RISCV/RISCVInstrPredicates.td | 1 - llvm/test/CodeGen/RISCV/machine-outliner-lpad.ll | 4 ++-- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 6fd47c0839d54..d48a5121b2c83 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3511,7 +3511,6 @@ RISCVInstrInfo::getOutliningTypeImpl(const MachineModuleInfo &MMI, return outliner::InstrType::Illegal; } - // LPADs should not be outlined too if (isLPAD(MI)) return outliner::InstrType::Illegal; diff --git a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td index 64db61af307ac..06309262f1b08 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrPredicates.td +++ b/llvm/lib/Target/RISCV/RISCVInstrPredicates.td @@ -148,7 +148,6 @@ def isNonZeroLoadImmediate CheckNot> ]>>>; -// Returns true if this is LPAD (auipc with rd = x0) def isLPAD : TIIPredicate<"isLPAD", MCReturnStatement