From de0420a468594d414c1d0b2a153500a8d5b84ec3 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Fri, 5 Sep 2025 20:36:53 +0000 Subject: [PATCH 1/5] [PowerPC] Implement AES Acceleration Instructions Implement AES Acceleration Instructions: * xxaesencp * xxaesdecp * xxaesgenlkp * xxgfmul128 --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 114 ++++++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index a12dfae2a0d7f..aec53a0b74000 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -120,6 +120,73 @@ class VXForm_VRTAB5 xo, dag OOL, dag IOL, string asmstr, let Inst{21...31} = xo; } +class XX3Form_XTBp5_M2 xo, dag OOL, dag IOL, string asmstr, + list pattern> + : I<60, OOL, IOL, asmstr, NoItinerary> { + + bits<5> XTp; + bits<5> XBp; + bits<2> M; + + let Pattern = pattern; + + let Inst{6...10} = XTp; + let Inst{15} = M{0}; + let Inst{16...19} = XBp{3...0}; + let Inst{20} = M{1}; + let Inst{21...29} = xo; + let Inst{30} = XBp{4}; +} + +class XX3Form_XTABp5_M2 xo, dag OOL, dag IOL, string asmstr, + list pattern> + : I<60, OOL, IOL, asmstr, NoItinerary> { + + bits<5> XTp; + bits<5> XAp; + bits<5> XBp; + bits<2> M; + + let Pattern = pattern; + + let Inst{6...9} = XTp{3...0}; + let Inst{10} = XTp{4}; + let Inst{11...14} = XAp{3...0}; + let Inst{15} = M{0}; + let Inst{16...19} = XBp{3...0}; + let Inst{20} = M{1}; + let Inst{21...28} = xo; + let Inst{29} = XAp{4}; + let Inst{30} = XBp{4}; +} + +class XX3Form_XTAB6_P1 xo, dag OOL, dag IOL, string asmstr, + list pattern> + : I<60, OOL, IOL, asmstr, NoItinerary> { + + bits<6> XT; + bits<6> XA; + bits<6> XB; + bits<1> P; + + let Pattern = pattern; + + let Inst{6...10} = XT{4...0}; + let Inst{11...15} = XA{4...0}; + let Inst{16...20} = XB{4...0}; + let Inst{21...22} = 3; + let Inst{23} = P; + let Inst{24...28} = xo; + let Inst{29} = XA{5}; + let Inst{30} = XB{5}; + let Inst{31} = XT{5}; +} + +//-------------------------- Instruction definitions -------------------------// +// Predicate combinations available: +// [IsISAFuture] +// [HasVSX, IsISAFuture] + let Predicates = [IsISAFuture] in { defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus", @@ -191,4 +258,51 @@ let Predicates = [HasVSX, IsISAFuture] in { def VUCMPRLH : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB), "vucmprlh $VRT, $VRA, $VRB", []>; + + // AES Acceleration Instructions + def XXAESENCP : XX3Form_XTABp5_M2<194, (outs vsrprc:$XTp), + (ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M), + "xxaesencp $XTp, $XAp, $XBp, $M", []>; + def XXAESDECP : XX3Form_XTABp5_M2<202, (outs vsrprc:$XTp), + (ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M), + "xxaesdecp $XTp, $XAp, $XBp, $M", []>; + def XXAESGENLKP : XX3Form_XTBp5_M2<420, (outs vsrprc:$XTp), + (ins vsrprc:$XBp, u2imm:$M), + "xxaesgenlkp $XTp, $XBp, $M", []>; + def XXGFMUL128 : XX3Form_XTAB6_P1<26, (outs vsrc:$XT), + (ins vsrc:$XA, vsrc:$XB, u1imm:$P), + "xxgfmul128 $XT, $XA, $XB, $P", []>; +} + +//---------------------------- Anonymous Patterns ----------------------------// +// Predicate combinations available: + + +//---------------------------- Instruction aliases ---------------------------// +// Predicate combinations available: +// [HasVSX, IsISAFuture] + +let Predicates = [HasVSX, IsISAFuture] in { + def : InstAlias<"xxaes128encp $XTp, $XAp, $XBp", + (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>; + def : InstAlias<"xxaes192encp $XTp, $XAp, $XBp", + (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>; + def : InstAlias<"xxaes265encp $XTp, $XAp, $XBp", + (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>; + def : InstAlias<"xxaes128decp $XTp, $XAp, $XBp", + (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>; + def : InstAlias<"xxaes192decp $XTp, $XAp, $XBp", + (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>; + def : InstAlias<"xxaes265decp $XTp, $XAp, $XBp", + (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>; + def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp, + vsrprc:$XBp, 0)>; + def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp, + vsrprc:$XBp, 1)>; + def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp, + vsrprc:$XBp, 2)>; + def : InstAlias<"xxgfmul128gcm $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA, + vsrc:$XB, 0)>; + def : InstAlias<"xxgfmul128gcm $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA, + vsrc:$XB, 1)>; } From dc5e4beabd23823dd8a3e2248c1989343c71841c Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 9 Sep 2025 15:25:06 +0000 Subject: [PATCH 2/5] fix extended mnemonic def --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index aec53a0b74000..c68e2f67a3567 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -297,12 +297,12 @@ let Predicates = [HasVSX, IsISAFuture] in { (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>; def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp, vsrprc:$XBp, 0)>; - def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp, + def : InstAlias<"xxaes192genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp, vsrprc:$XBp, 1)>; - def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp, + def : InstAlias<"xxaes256genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp, vsrprc:$XBp, 2)>; def : InstAlias<"xxgfmul128gcm $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA, vsrc:$XB, 0)>; - def : InstAlias<"xxgfmul128gcm $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA, + def : InstAlias<"xxgfmul128xts $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA, vsrc:$XB, 1)>; } From b1b55d6ae39efeeafca1c635f51cda035014a26c Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 9 Sep 2025 15:46:51 +0000 Subject: [PATCH 3/5] fix err in extended mnemonic naming --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index c68e2f67a3567..3f52f72a61c8d 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -287,13 +287,13 @@ let Predicates = [HasVSX, IsISAFuture] in { (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>; def : InstAlias<"xxaes192encp $XTp, $XAp, $XBp", (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>; - def : InstAlias<"xxaes265encp $XTp, $XAp, $XBp", + def : InstAlias<"xxaes256encp $XTp, $XAp, $XBp", (XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>; def : InstAlias<"xxaes128decp $XTp, $XAp, $XBp", (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>; def : InstAlias<"xxaes192decp $XTp, $XAp, $XBp", (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>; - def : InstAlias<"xxaes265decp $XTp, $XAp, $XBp", + def : InstAlias<"xxaes256decp $XTp, $XAp, $XBp", (XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>; def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp, vsrprc:$XBp, 0)>; From becd2d21d290f733565d0e847849979fbb77f3b2 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 9 Sep 2025 17:30:00 +0000 Subject: [PATCH 4/5] fix err in xxaesgenlkp def --- llvm/lib/Target/PowerPC/PPCInstrFuture.td | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td index 3f52f72a61c8d..25ec35925c24c 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFuture.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td @@ -130,7 +130,8 @@ class XX3Form_XTBp5_M2 xo, dag OOL, dag IOL, string asmstr, let Pattern = pattern; - let Inst{6...10} = XTp; + let Inst{6...9} = XTp{3...0}; + let Inst {10} = XTp{4}; let Inst{15} = M{0}; let Inst{16...19} = XBp{3...0}; let Inst{20} = M{1}; From ccc7be721327ca1062cca3319df6356a36c10223 Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 9 Sep 2025 17:43:48 +0000 Subject: [PATCH 5/5] add encoding tests --- .../PowerPC/ppc-encoding-ISAFuture.txt | 12 ++++++++++++ .../PowerPC/ppc64le-encoding-ISAFuture.txt | 12 ++++++++++++ llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 16 ++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index da3601b00b199..a203c706fb44a 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -231,3 +231,15 @@ #CHECK: vucmprhh 1, 3, 6 0x10,0x23,0x31,0x03 + +#CHECK: xxaes192encp 8, 10, 14 +0xf1,0x0b,0x76,0x10 + +#CHECK: xxaes256decp 14, 10, 6 +0xf1,0xca,0x3e,0x50 + +#CHECK: xxaes128genlkp 4, 8 +0xf0,0x80,0x46,0x90 + +#CHECK: xxgfmul128gcm 7, 5, 4 +0xf0,0xe5,0x26,0xd0 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index 66d05043301b6..713015df90b91 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -225,3 +225,15 @@ #CHECK: vucmprhh 1, 3, 6 0x03,0x31,0x23,0x10 + +#CHECK: xxaes192encp 8, 10, 14 +0x10,0x76,0x0b,0xf1 + +#CHECK: xxaes256decp 14, 10, 6 +0x50,0x3e,0xca,0xf1 + +#CHECK: xxaes128genlkp 4, 8 +0x90,0x46,0x80,0xf0 + +#CHECK: xxgfmul128gcm 7, 5, 4 +0xd0,0x26,0xe5,0xf0 diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index 6ae7bd785773d..824716877d57f 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -330,3 +330,19 @@ vucmprhh 1, 3, 6 #CHECK-BE: vucmprhh 1, 3, 6 # encoding: [0x10,0x23,0x31,0x03] #CHECK-LE: vucmprhh 1, 3, 6 # encoding: [0x03,0x31,0x23,0x10] + + xxaes192encp 8, 10, 14 +#CHECK-BE: xxaes192encp 8, 10, 14 # encoding: [0xf1,0x0b,0x76,0x10] +#CHECK-LE: xxaes192encp 8, 10, 14 # encoding: [0x10,0x76,0x0b,0xf1] + + xxaes256decp 14, 10, 6 +#CHECK-BE: xxaes256decp 14, 10, 6 # encoding: [0xf1,0xca,0x3e,0x50] +#CHECK-LE: xxaes256decp 14, 10, 6 # encoding: [0x50,0x3e,0xca,0xf1] + + xxaes128genlkp 4, 8 +#CHECK-BE: xxaes128genlkp 4, 8 # encoding: [0xf0,0x80,0x46,0x90] +#CHECK-LE: xxaes128genlkp 4, 8 # encoding: [0x90,0x46,0x80,0xf0] + + xxgfmul128gcm 7, 5, 4 +#CHECK-BE: xxgfmul128gcm 7, 5, 4 # encoding: [0xf0,0xe5,0x26,0xd0] +#CHECK-LE: xxgfmul128gcm 7, 5, 4 # encoding: [0xd0,0x26,0xe5,0xf0]