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Merged
lei137 merged 5 commits into from
Sep 23, 2025
Merged

[PowerPC] Implement AES Acceleration Instructions #157725

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de0420a
[PowerPC] Implement AES Acceleration Instructions
lei137 Sep 5, 2025
dc5e4be
fix extended mnemonic def
lei137 Sep 9, 2025
b1b55d6
fix err in extended mnemonic naming
lei137 Sep 9, 2025
becd2d2
fix err in xxaesgenlkp def
lei137 Sep 9, 2025
ccc7be7
add encoding tests
lei137 Sep 9, 2025
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115 changes: 115 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrFuture.td
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Original file line number Diff line number Diff line change
Expand Up @@ -120,6 +120,74 @@ class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
let Inst{21...31} = xo;
}

class XX3Form_XTBp5_M2<bits<9> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<60, OOL, IOL, asmstr, NoItinerary> {

bits<5> XTp;
bits<5> XBp;
bits<2> M;

let Pattern = pattern;

let Inst{6...9} = XTp{3...0};
let Inst {10} = XTp{4};
let Inst{15} = M{0};
let Inst{16...19} = XBp{3...0};
let Inst{20} = M{1};
let Inst{21...29} = xo;
let Inst{30} = XBp{4};
}

class XX3Form_XTABp5_M2<bits<8> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<60, OOL, IOL, asmstr, NoItinerary> {

bits<5> XTp;
bits<5> XAp;
bits<5> XBp;
bits<2> M;

let Pattern = pattern;

let Inst{6...9} = XTp{3...0};
let Inst{10} = XTp{4};
let Inst{11...14} = XAp{3...0};
let Inst{15} = M{0};
let Inst{16...19} = XBp{3...0};
let Inst{20} = M{1};
let Inst{21...28} = xo;
let Inst{29} = XAp{4};
let Inst{30} = XBp{4};
}

class XX3Form_XTAB6_P1<bits<5> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<60, OOL, IOL, asmstr, NoItinerary> {

bits<6> XT;
bits<6> XA;
bits<6> XB;
bits<1> P;

let Pattern = pattern;

let Inst{6...10} = XT{4...0};
let Inst{11...15} = XA{4...0};
let Inst{16...20} = XB{4...0};
let Inst{21...22} = 3;
let Inst{23} = P;
let Inst{24...28} = xo;
let Inst{29} = XA{5};
let Inst{30} = XB{5};
let Inst{31} = XT{5};
}

//-------------------------- Instruction definitions -------------------------//
// Predicate combinations available:
// [IsISAFuture]
// [HasVSX, IsISAFuture]
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@maryammo maryammo Sep 19, 2025

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These AES instructions use VSX registers, so do we need HasVSX predicate?

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@lei137 lei137 Sep 22, 2025

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I am not sure I understand the questions... They do use them therefore I think it is needed.
The instructions are currently defined under the predicate combinations: [HasVSX, IsISAFuture] as are the aliases.


let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
Expand Down Expand Up @@ -191,4 +259,51 @@ let Predicates = [HasVSX, IsISAFuture] in {
def VUCMPRLH
: VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
"vucmprlh $VRT, $VRA, $VRB", []>;

// AES Acceleration Instructions
def XXAESENCP : XX3Form_XTABp5_M2<194, (outs vsrprc:$XTp),
(ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M),
"xxaesencp $XTp, $XAp, $XBp, $M", []>;
def XXAESDECP : XX3Form_XTABp5_M2<202, (outs vsrprc:$XTp),
(ins vsrprc:$XAp, vsrprc:$XBp, u2imm:$M),
"xxaesdecp $XTp, $XAp, $XBp, $M", []>;
def XXAESGENLKP : XX3Form_XTBp5_M2<420, (outs vsrprc:$XTp),
(ins vsrprc:$XBp, u2imm:$M),
"xxaesgenlkp $XTp, $XBp, $M", []>;
def XXGFMUL128 : XX3Form_XTAB6_P1<26, (outs vsrc:$XT),
(ins vsrc:$XA, vsrc:$XB, u1imm:$P),
"xxgfmul128 $XT, $XA, $XB, $P", []>;
}

//---------------------------- Anonymous Patterns ----------------------------//
// Predicate combinations available:


//---------------------------- Instruction aliases ---------------------------//
// Predicate combinations available:
// [HasVSX, IsISAFuture]

let Predicates = [HasVSX, IsISAFuture] in {
def : InstAlias<"xxaes128encp $XTp, $XAp, $XBp",
(XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>;
def : InstAlias<"xxaes192encp $XTp, $XAp, $XBp",
(XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>;
def : InstAlias<"xxaes256encp $XTp, $XAp, $XBp",
(XXAESENCP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>;
def : InstAlias<"xxaes128decp $XTp, $XAp, $XBp",
(XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 0)>;
def : InstAlias<"xxaes192decp $XTp, $XAp, $XBp",
(XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 1)>;
def : InstAlias<"xxaes256decp $XTp, $XAp, $XBp",
(XXAESDECP vsrprc:$XTp, vsrprc:$XAp, vsrprc:$XBp, 2)>;
def : InstAlias<"xxaes128genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,
vsrprc:$XBp, 0)>;
def : InstAlias<"xxaes192genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,
vsrprc:$XBp, 1)>;
def : InstAlias<"xxaes256genlkp $XTp, $XBp", (XXAESGENLKP vsrprc:$XTp,
vsrprc:$XBp, 2)>;
def : InstAlias<"xxgfmul128gcm $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA,
vsrc:$XB, 0)>;
def : InstAlias<"xxgfmul128xts $XT, $XA, $XB", (XXGFMUL128 vsrc:$XT, vsrc:$XA,
vsrc:$XB, 1)>;
}
12 changes: 12 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
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Expand Up @@ -231,3 +231,15 @@

#CHECK: vucmprhh 1, 3, 6
0x10,0x23,0x31,0x03

#CHECK: xxaes192encp 8, 10, 14
0xf1,0x0b,0x76,0x10

#CHECK: xxaes256decp 14, 10, 6
0xf1,0xca,0x3e,0x50

#CHECK: xxaes128genlkp 4, 8
0xf0,0x80,0x46,0x90

#CHECK: xxgfmul128gcm 7, 5, 4
0xf0,0xe5,0x26,0xd0
12 changes: 12 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -225,3 +225,15 @@

#CHECK: vucmprhh 1, 3, 6
0x03,0x31,0x23,0x10

#CHECK: xxaes192encp 8, 10, 14
0x10,0x76,0x0b,0xf1

#CHECK: xxaes256decp 14, 10, 6
0x50,0x3e,0xca,0xf1

#CHECK: xxaes128genlkp 4, 8
0x90,0x46,0x80,0xf0

#CHECK: xxgfmul128gcm 7, 5, 4
0xd0,0x26,0xe5,0xf0
16 changes: 16 additions & 0 deletions llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
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Expand Up @@ -330,3 +330,19 @@
vucmprhh 1, 3, 6
#CHECK-BE: vucmprhh 1, 3, 6 # encoding: [0x10,0x23,0x31,0x03]
#CHECK-LE: vucmprhh 1, 3, 6 # encoding: [0x03,0x31,0x23,0x10]

xxaes192encp 8, 10, 14
#CHECK-BE: xxaes192encp 8, 10, 14 # encoding: [0xf1,0x0b,0x76,0x10]
#CHECK-LE: xxaes192encp 8, 10, 14 # encoding: [0x10,0x76,0x0b,0xf1]

xxaes256decp 14, 10, 6
#CHECK-BE: xxaes256decp 14, 10, 6 # encoding: [0xf1,0xca,0x3e,0x50]
#CHECK-LE: xxaes256decp 14, 10, 6 # encoding: [0x50,0x3e,0xca,0xf1]

xxaes128genlkp 4, 8
#CHECK-BE: xxaes128genlkp 4, 8 # encoding: [0xf0,0x80,0x46,0x90]
#CHECK-LE: xxaes128genlkp 4, 8 # encoding: [0x90,0x46,0x80,0xf0]

xxgfmul128gcm 7, 5, 4
#CHECK-BE: xxgfmul128gcm 7, 5, 4 # encoding: [0xf0,0xe5,0x26,0xd0]
#CHECK-LE: xxgfmul128gcm 7, 5, 4 # encoding: [0xd0,0x26,0xe5,0xf0]