Skip to content

[RISCV] Extend zvqdot matching to handle disjoint or #157901

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
Sep 10, 2025
Merged

[RISCV] Extend zvqdot matching to handle disjoint or #157901

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
faabcc5
Precommit tests
XChy Sep 10, 2025
1ca1d7a
[RISCV] Extend zvqdot matching to handle disjoint or
XChy Sep 10, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 6 additions & 9 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19121,18 +19121,18 @@ static SDValue foldReduceOperandViaVQDOT(SDValue InVec, const SDLoc &DL,
SelectionDAG &DAG,
const RISCVSubtarget &Subtarget,
const RISCVTargetLowering &TLI) {
using namespace SDPatternMatch;
// Note: We intentionally do not check the legality of the reduction type.
// We want to handle the m4/m8 *src* types, and thus need to let illegal
// intermediate types flow through here.
if (InVec.getValueType().getVectorElementType() != MVT::i32 ||
!InVec.getValueType().getVectorElementCount().isKnownMultipleOf(4))
return SDValue();

// Recurse through adds (since generic dag canonicalizes to that
// form). TODO: Handle disjoint or here.
if (InVec->getOpcode() == ISD::ADD) {
SDValue A = InVec.getOperand(0);
SDValue B = InVec.getOperand(1);
// Recurse through adds/disjoint ors (since generic dag canonicalizes to that
// form).
SDValue A, B;
if (sd_match(InVec, m_AddLike(m_Value(A), m_Value(B)))) {
SDValue AOpt = foldReduceOperandViaVQDOT(A, DL, DAG, Subtarget, TLI);
SDValue BOpt = foldReduceOperandViaVQDOT(B, DL, DAG, Subtarget, TLI);
if (AOpt || BOpt) {
Expand Down Expand Up @@ -19169,12 +19169,9 @@ static SDValue foldReduceOperandViaVQDOT(SDValue InVec, const SDLoc &DL,
// mul (zext a, zext b) -> partial_reduce_umla 0, a, b
// mul (sext a, zext b) -> partial_reduce_ssmla 0, a, b
// mul (zext a, sext b) -> partial_reduce_smla 0, b, a (swapped)
if (InVec.getOpcode() != ISD::MUL)
if (!sd_match(InVec, m_Mul(m_Value(A), m_Value(B))))
return SDValue();

SDValue A = InVec.getOperand(0);
SDValue B = InVec.getOperand(1);

if (!ISD::isExtOpcode(A.getOpcode()))
return SDValue();

Expand Down
127 changes: 127 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvqdotq.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1552,6 +1552,133 @@ entry:
%res = call <4 x i32> @llvm.experimental.vector.partial.reduce.add(<4 x i32> zeroinitializer, <16 x i32> %a.ext)
ret <4 x i32> %res
}

define i32 @vqdot_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-LABEL: vqdot_vv_accum_disjoint_or:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
; NODOT-NEXT: vsext.vf2 v18, v9
; NODOT-NEXT: vwmul.vv v8, v16, v18
; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; NODOT-NEXT: vor.vv v8, v8, v12
; NODOT-NEXT: vmv.s.x v12, zero
; NODOT-NEXT: vredsum.vs v8, v8, v12
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
; DOT-LABEL: vqdot_vv_accum_disjoint_or:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
; DOT-NEXT: vqdot.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
; DOT-NEXT: ret
entry:
%a.sext = sext <16 x i8> %a to <16 x i32>
%b.sext = sext <16 x i8> %b to <16 x i32>
%mul = mul <16 x i32> %a.sext, %b.sext
%add = or disjoint <16 x i32> %mul, %x
%sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)
ret i32 %sum
}

define i32 @vqdot_vv_accum_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; CHECK-LABEL: vqdot_vv_accum_or:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vsext.vf2 v16, v8
; CHECK-NEXT: vsext.vf2 v18, v9
; CHECK-NEXT: vwmul.vv v8, v16, v18
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vor.vv v8, v8, v12
; CHECK-NEXT: vmv.s.x v12, zero
; CHECK-NEXT: vredsum.vs v8, v8, v12
; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret
entry:
%a.sext = sext <16 x i8> %a to <16 x i32>
%b.sext = sext <16 x i8> %b to <16 x i32>
%mul = mul <16 x i32> %a.sext, %b.sext
%add = or <16 x i32> %mul, %x
%sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)
ret i32 %sum
}

define i32 @vqdotu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-LABEL: vqdotu_vv_accum_disjoint_or:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; NODOT-NEXT: vwmulu.vv v10, v8, v9
; NODOT-NEXT: vsetvli zero, zero, e16, m2, ta, ma
; NODOT-NEXT: vwaddu.wv v12, v12, v10
; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; NODOT-NEXT: vmv.s.x v8, zero
; NODOT-NEXT: vredsum.vs v8, v12, v8
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
; DOT-LABEL: vqdotu_vv_accum_disjoint_or:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
; DOT-NEXT: vqdotu.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
; DOT-NEXT: ret
entry:
%a.zext = zext <16 x i8> %a to <16 x i32>
%b.zext = zext <16 x i8> %b to <16 x i32>
%mul = mul <16 x i32> %a.zext, %b.zext
%add = or disjoint <16 x i32> %mul, %x
%sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)
ret i32 %sum
}

define i32 @vqdotsu_vv_accum_disjoint_or(<16 x i8> %a, <16 x i8> %b, <16 x i32> %x) {
; NODOT-LABEL: vqdotsu_vv_accum_disjoint_or:
; NODOT: # %bb.0: # %entry
; NODOT-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; NODOT-NEXT: vsext.vf2 v16, v8
; NODOT-NEXT: vzext.vf2 v18, v9
; NODOT-NEXT: vwmulsu.vv v8, v16, v18
; NODOT-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; NODOT-NEXT: vor.vv v8, v8, v12
; NODOT-NEXT: vmv.s.x v12, zero
; NODOT-NEXT: vredsum.vs v8, v8, v12
; NODOT-NEXT: vmv.x.s a0, v8
; NODOT-NEXT: ret
;
; DOT-LABEL: vqdotsu_vv_accum_disjoint_or:
; DOT: # %bb.0: # %entry
; DOT-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; DOT-NEXT: vmv1r.v v16, v12
; DOT-NEXT: vqdotsu.vv v16, v8, v9
; DOT-NEXT: vsetivli zero, 4, e32, m4, tu, ma
; DOT-NEXT: vmv.v.v v12, v16
; DOT-NEXT: vmv.s.x v8, zero
; DOT-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; DOT-NEXT: vredsum.vs v8, v12, v8
; DOT-NEXT: vmv.x.s a0, v8
; DOT-NEXT: ret
entry:
%a.sext = sext <16 x i8> %a to <16 x i32>
%b.zext = zext <16 x i8> %b to <16 x i32>
%mul = mul <16 x i32> %a.sext, %b.zext
%add = or disjoint <16 x i32> %mul, %x
%sum = tail call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> %add)
ret i32 %sum
}

;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; DOT32: {{.*}}
; DOT64: {{.*}}