From a477a44f29b02f29158c1591e673a275e9dee1a8 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 5 Sep 2025 18:03:59 +0900 Subject: [PATCH 1/4] PPC: Replace PointerLikeRegClass with RegClassByHwMode --- .../PowerPC/Disassembler/PPCDisassembler.cpp | 3 -- llvm/lib/Target/PowerPC/PPC.td | 6 ++++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 28 ++++++------------- llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 10 +++++-- 4 files changed, 23 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index 47586c417cfe3..70e619cc22b19 100644 --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -185,9 +185,6 @@ DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, return decodeRegisterClass(Inst, RegNo, XRegsNoX0); } -#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass -#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass - static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index 386d0f65d1ed1..d491e88b66ad8 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -394,6 +394,12 @@ def NotAIX : Predicate<"!Subtarget->isAIXABI()">; def IsISAFuture : Predicate<"Subtarget->isISAFuture()">; def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">; +//===----------------------------------------------------------------------===// +// HwModes +//===----------------------------------------------------------------------===// + +defvar PPC32 = DefaultMode; +def PPC64 : HwMode<[In64BitMode]>; // Since new processors generally contain a superset of features of those that // came before them, the idea is to make implementations of new processors diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index db066bc4b7bdd..55e38bcf4afc9 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2142,33 +2142,23 @@ bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, assert(UseIdx < UseMI.getNumOperands() && "Cannot find Reg in UseMI"); assert(UseIdx < UseMCID.getNumOperands() && "No operand description for Reg"); - const MCOperandInfo *UseInfo = &UseMCID.operands()[UseIdx]; - // We can fold the zero if this register requires a GPRC_NOR0/G8RC_NOX0 // register (which might also be specified as a pointer class kind). - if (UseInfo->isLookupPtrRegClass()) { - if (UseInfo->RegClass /* Kind */ != 1) - return false; - } else { - if (UseInfo->RegClass != PPC::GPRC_NOR0RegClassID && - UseInfo->RegClass != PPC::G8RC_NOX0RegClassID) - return false; - } + + const MCOperandInfo &UseInfo = UseMCID.operands()[UseIdx]; + int16_t RegClass = getOpRegClassID(UseInfo); + if (UseInfo.RegClass != PPC::GPRC_NOR0RegClassID && + UseInfo.RegClass != PPC::G8RC_NOX0RegClassID) + return false; // Make sure this is not tied to an output register (or otherwise // constrained). This is true for ST?UX registers, for example, which // are tied to their output registers. - if (UseInfo->Constraints != 0) + if (UseInfo.Constraints != 0) return false; - MCRegister ZeroReg; - if (UseInfo->isLookupPtrRegClass()) { - bool isPPC64 = Subtarget.isPPC64(); - ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; - } else { - ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? - PPC::ZERO8 : PPC::ZERO; - } + MCRegister ZeroReg = + RegClass == PPC::G8RC_NOX0RegClassID ? PPC::ZERO8 : PPC::ZERO; LLVM_DEBUG(dbgs() << "Folded immediate zero for: "); LLVM_DEBUG(UseMI.dump()); diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 8b690b7b833b3..adda91786d19c 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -868,7 +868,11 @@ def crbitm: Operand { def PPCRegGxRCNoR0Operand : AsmOperandClass { let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; } -def ptr_rc_nor0 : Operand, PointerLikeRegClass<1> { + +def ptr_rc_nor0 : Operand, + RegClassByHwMode< + [PPC32, PPC64], + [GPRC_NOR0, G8RC_NOX0]> { let ParserMatchClass = PPCRegGxRCNoR0Operand; } @@ -902,7 +906,9 @@ def memri34_pcrel : Operand { // memri, imm is a 34-bit value. def PPCRegGxRCOperand : AsmOperandClass { let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; } -def ptr_rc_idx : Operand, PointerLikeRegClass<0> { +def ptr_rc_idx : Operand, + RegClassByHwMode<[PPC32, PPC64], + [GPRC, G8RC]> { let ParserMatchClass = PPCRegGxRCOperand; } From 6f955a844ba0a9fde27d19a5e98b843e8f15d69e Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 16 Sep 2025 17:02:30 +0900 Subject: [PATCH 2/4] Use RegisterOperand instead of multiple inheritance from Operand and RegClassByHwMode --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 110 ++++++++++----------- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 44 ++++----- llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 30 +++--- 3 files changed, 93 insertions(+), 91 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 269d30318bca8..580286f00a425 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -693,66 +693,66 @@ def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc_nox0:$RA, tlsreg: "add $RT, $RA, $RB", IIC_IntSimple, [(set i64:$RT, (add i64:$RA, tglobaltlsaddr:$RB))]>; let mayLoad = 1 in { -def LBZXTLS : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LBZXTLS : XForm_1<31, 87, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHAXTLS : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LHAXTLS : XForm_1<31, 343, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWZXTLS : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LWZXTLS : XForm_1<31, 23, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWAXTLS : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LWAXTLS : XForm_1<31, 341, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LDXTLS : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LDXTLS : XForm_1<31, 21, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; -def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHAXTLS_32 : XForm_1<31, 343, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LHAXTLS_32 : XForm_1<31, 343, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWAXTLS_32 : XForm_1<31, 341, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LWAXTLS_32 : XForm_1<31, 341, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; } let mayLoad = 1, Predicates = [HasFPU] in { -def LFSXTLS : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LFSXTLS : XForm_25<31, 535, (outs f4rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>; -def LFDXTLS : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LFDXTLS : XForm_25<31, 599, (outs f8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>; } let mayStore = 1 in { -def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stbx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "sthx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stwx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, PPC970_DGroup_Cracked; -def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stbx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "sthx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stwx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; } let mayStore = 1, Predicates = [HasFPU] in { -def STFSXTLS : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STFSXTLS : XForm_8<31, 663, (outs), (ins f4rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>, PPC970_DGroup_Cracked; -def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>, PPC970_DGroup_Cracked; } @@ -825,47 +825,47 @@ def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc:$RA, tlsreg:$RB), "add $RT, $RA, $RB", IIC_IntSimple, []>; let mayLoad = 1 in { -def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHAXTLS_ : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LHAXTLS_ : XForm_1<31, 343, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWAXTLS_ : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LWAXTLS_ : XForm_1<31, 341, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; } let mayLoad = 1, Predicates = [HasFPU] in { -def LFSXTLS_ : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LFSXTLS_ : XForm_25<31, 535, (outs f4rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>; -def LFDXTLS_ : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), +def LFDXTLS_ : XForm_25<31, 599, (outs f8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>; } let mayStore = 1 in { -def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stbx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "sthx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stwx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, PPC970_DGroup_Cracked; } let mayStore = 1, Predicates = [HasFPU] in { -def STFSXTLS_ : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STFSXTLS_ : XForm_8<31, 663, (outs), (ins f4rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>, PPC970_DGroup_Cracked; -def STFDXTLS_ : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), +def STFDXTLS_ : XForm_8<31, 727, (outs), (ins f8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>, PPC970_DGroup_Cracked; } @@ -1309,18 +1309,18 @@ def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$RST), (ins (memrr $RA, $RB):$ad // Update forms. let mayLoad = 1, hasSideEffects = 0 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in -def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LHAU8 : DForm_1<43, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lhau $RST, $addr", IIC_LdStLHAU, []>, RegConstraint<"$addr.reg = $ea_result">; // NO LWAU! let Interpretation64Bit = 1, isCodeGenOnly = 1 in -def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lhaux $RST, $addr", IIC_LdStLHAUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lwaux $RST, $addr", IIC_LdStLHAUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, isPPC64; @@ -1359,28 +1359,28 @@ def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr // Update forms. let mayLoad = 1, hasSideEffects = 0 in { -def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LBZU8 : DForm_1<35, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lbzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; -def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LHZU8 : DForm_1<41, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lhzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; -def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LWZU8 : DForm_1<33, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lwzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; -def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lbzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lhzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lwzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; @@ -1432,12 +1432,12 @@ def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$RST), (ins (memrr $RA, $RB):$ad } let mayLoad = 1, hasSideEffects = 0 in { -def LDU : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LDU : DSForm_1<58, 1, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memrix $D, $RA):$addr), "ldu $RST, $addr", IIC_LdStLDU, []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64; -def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), +def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "ldux $RST, $addr", IIC_LdStLDUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, isPPC64; @@ -1704,40 +1704,40 @@ def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst), // Stores with Update (pre-inc). let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in { -def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), +def STBU8 : DForm_1<39, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), "stbu $RST, $addr", IIC_LdStSTU, []>, RegConstraint<"$addr.reg = $ea_res">; -def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), +def STHU8 : DForm_1<45, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), "sthu $RST, $addr", IIC_LdStSTU, []>, RegConstraint<"$addr.reg = $ea_res">; -def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), +def STWU8 : DForm_1<37, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), "stwu $RST, $addr", IIC_LdStSTU, []>, RegConstraint<"$addr.reg = $ea_res">; -def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), +def STBUX8: XForm_8_memOp<31, 247, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memrr $RA, $RB):$addr), "stbux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), +def STHUX8: XForm_8_memOp<31, 439, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memrr $RA, $RB):$addr), "sthux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), +def STWUX8: XForm_8_memOp<31, 183, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memrr $RA, $RB):$addr), "stwux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; } // Interpretation64Bit -def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), +def STDU : DSForm_1<62, 1, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memrix $D, $RA):$addr), "stdu $RST, $addr", IIC_LdStSTU, []>, RegConstraint<"$addr.reg = $ea_res">, isPPC64; -def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), +def STDUX : XForm_8_memOp<31, 181, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memrr $RA, $RB):$addr), "stdux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 1c45050cdf9ca..c4ddbb8831147 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1950,61 +1950,61 @@ def LFD : DForm_1<50, (outs f8rc:$RST), (ins (memri $D, $RA):$addr), // Unindexed (r+i) Loads with Update (preinc). let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { -def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), +def LBZU : DForm_1<35, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lbzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$RA = $ea_result">; -def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), +def LHAU : DForm_1<43, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lhau $RST, $addr", IIC_LdStLHAU, []>, RegConstraint<"$addr.reg = $ea_result">; -def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), +def LHZU : DForm_1<41, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lhzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; -def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), +def LWZU : DForm_1<33, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lwzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; let Predicates = [HasFPU] in { -def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), +def LFSU : DForm_1<49, (outs f4rc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lfsu $RST, $addr", IIC_LdStLFDU, []>, RegConstraint<"$addr.reg = $ea_result">; -def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), +def LFDU : DForm_1<51, (outs f8rc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), "lfdu $RST, $addr", IIC_LdStLFDU, []>, RegConstraint<"$addr.reg = $ea_result">; } // Indexed (r+r) Loads with Update (preinc). -def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result), +def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lbzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result), +def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lhaux $RST, $addr", IIC_LdStLHAUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result), +def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lhzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result), +def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lwzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; let Predicates = [HasFPU] in { -def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), +def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lfsux $RST, $addr", IIC_LdStLFDUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), +def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, PtrOpNoR0:$ea_result), (ins (memrr $RA, $RB):$addr), "lfdux $RST, $addr", IIC_LdStLFDUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; @@ -2086,20 +2086,20 @@ def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst), // Unindexed (r+i) Stores with Update (preinc). let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { -def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), +def STBU : DForm_1<39, (outs PtrOpNoR0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), "stbu $RST, $dst", IIC_LdStSTU, []>, RegConstraint<"$dst.reg = $ea_res">; -def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), +def STHU : DForm_1<45, (outs PtrOpNoR0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), "sthu $RST, $dst", IIC_LdStSTU, []>, RegConstraint<"$dst.reg = $ea_res">; -def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), +def STWU : DForm_1<37, (outs PtrOpNoR0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), "stwu $RST, $dst", IIC_LdStSTU, []>, RegConstraint<"$dst.reg = $ea_res">; let Predicates = [HasFPU] in { -def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst), +def STFSU : DForm_1<53, (outs PtrOpNoR0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst), "stfsu $RST, $dst", IIC_LdStSTFDU, []>, RegConstraint<"$dst.reg = $ea_res">; -def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst), +def STFDU : DForm_1<55, (outs PtrOpNoR0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst), "stfdu $RST, $dst", IIC_LdStSTFDU, []>, RegConstraint<"$dst.reg = $ea_res">; } @@ -2159,28 +2159,28 @@ def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$ad // Indexed (r+r) Stores with Update (preinc). let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { -def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), +def STBUX : XForm_8_memOp<31, 247, (outs PtrOpNoR0:$ea_res), (ins gprc:$RST, (memrr $RA, $RB):$addr), "stbux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), +def STHUX : XForm_8_memOp<31, 439, (outs PtrOpNoR0:$ea_res), (ins gprc:$RST, (memrr $RA, $RB):$addr), "sthux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), +def STWUX : XForm_8_memOp<31, 183, (outs PtrOpNoR0:$ea_res), (ins gprc:$RST, (memrr $RA, $RB):$addr), "stwux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; let Predicates = [HasFPU] in { -def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), +def STFSUX: XForm_8_memOp<31, 695, (outs PtrOpNoR0:$ea_res), (ins f4rc:$RST, (memrr $RA, $RB):$addr), "stfsux $RST, $addr", IIC_LdStSTFDU, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), +def STFDUX: XForm_8_memOp<31, 759, (outs PtrOpNoR0:$ea_res), (ins f8rc:$RST, (memrr $RA, $RB):$addr), "stfdux $RST, $addr", IIC_LdStSTFDU, []>, RegConstraint<"$addr.ptrreg = $ea_res">, diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index adda91786d19c..e2aa100262724 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -869,13 +869,15 @@ def PPCRegGxRCNoR0Operand : AsmOperandClass { let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; } -def ptr_rc_nor0 : Operand, - RegClassByHwMode< - [PPC32, PPC64], - [GPRC_NOR0, G8RC_NOX0]> { +def ptr_rc_nor0 : RegClassByHwMode< + [PPC32, PPC64], + [GPRC_NOR0, G8RC_NOX0]>; + +def PtrOpNoR0 : RegisterOperand { let ParserMatchClass = PPCRegGxRCNoR0Operand; } + // New addressing modes with 34 bit immediates. def PPCDispRI34Operand : AsmOperandClass { let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; @@ -893,7 +895,7 @@ def dispRI34_pcrel : Operand { } def memri34 : Operand { // memri, imm is a 34-bit value. let PrintMethod = "printMemRegImm34"; - let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); + let MIOperandInfo = (ops dispRI34:$imm, PtrOpNoR0:$reg); } // memri, imm is a 34-bit value for pc-relative instructions where // base register is set to zero. @@ -978,43 +980,43 @@ def dispSPE2 : Operand { def memri : Operand { let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); + let MIOperandInfo = (ops dispRI:$imm, PtrOpNoR0:$reg); let OperandType = "OPERAND_MEMORY"; } def memrr : Operand { let PrintMethod = "printMemRegReg"; - let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); + let MIOperandInfo = (ops PtrOpNoR0:$ptrreg, ptr_rc_idx:$offreg); let OperandType = "OPERAND_MEMORY"; } def memrix : Operand { // memri where the imm is 4-aligned. let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); + let MIOperandInfo = (ops dispRIX:$imm, PtrOpNoR0:$reg); let OperandType = "OPERAND_MEMORY"; } def memrihash : Operand { // memrihash 8-aligned for ROP Protection Instructions. let PrintMethod = "printMemRegImmHash"; - let MIOperandInfo = (ops dispRIHash:$imm, ptr_rc_nor0:$reg); + let MIOperandInfo = (ops dispRIHash:$imm, PtrOpNoR0:$reg); let OperandType = "OPERAND_MEMORY"; } def memrix16 : Operand { // memri, imm is 16-aligned, 12-bit, Inst{16:27} let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); + let MIOperandInfo = (ops dispRIX16:$imm, PtrOpNoR0:$reg); let OperandType = "OPERAND_MEMORY"; } def spe8dis : Operand { // SPE displacement where the imm is 8-aligned. let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); + let MIOperandInfo = (ops dispSPE8:$imm, PtrOpNoR0:$reg); let OperandType = "OPERAND_MEMORY"; } def spe4dis : Operand { // SPE displacement where the imm is 4-aligned. let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); + let MIOperandInfo = (ops dispSPE4:$imm, PtrOpNoR0:$reg); let OperandType = "OPERAND_MEMORY"; } def spe2dis : Operand { // SPE displacement where the imm is 2-aligned. let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); + let MIOperandInfo = (ops dispSPE2:$imm, PtrOpNoR0:$reg); let OperandType = "OPERAND_MEMORY"; } @@ -1022,7 +1024,7 @@ def spe2dis : Operand { // SPE displacement where the imm is 2-aligned. // pseudo-instructions which translates to LD/LWZ. These instructions requires // G8RC_NOX0 registers. def memr : Operand { - let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); + let MIOperandInfo = (ops PtrOpNoR0:$ptrreg); let OperandType = "OPERAND_MEMORY"; } def PPCTLSRegOperand : AsmOperandClass { From ad52c0819de381476d9c616a4e19408f92dd5921 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 18 Sep 2025 00:20:16 +0900 Subject: [PATCH 3/4] Avoid more multple inheritance --- llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index e2aa100262724..9fa965afa10aa 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -908,9 +908,10 @@ def memri34_pcrel : Operand { // memri, imm is a 34-bit value. def PPCRegGxRCOperand : AsmOperandClass { let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; } -def ptr_rc_idx : Operand, - RegClassByHwMode<[PPC32, PPC64], - [GPRC, G8RC]> { +def ptr_rc_idx : RegClassByHwMode<[PPC32, PPC64], + [GPRC, G8RC]>; + +def PtrRCIdxOp : RegisterOperand { let ParserMatchClass = PPCRegGxRCOperand; } @@ -985,7 +986,7 @@ def memri : Operand { } def memrr : Operand { let PrintMethod = "printMemRegReg"; - let MIOperandInfo = (ops PtrOpNoR0:$ptrreg, ptr_rc_idx:$offreg); + let MIOperandInfo = (ops PtrOpNoR0:$ptrreg, PtrRCIdxOp:$offreg); let OperandType = "OPERAND_MEMORY"; } def memrix : Operand { // memri where the imm is 4-aligned. From ae21c515a32864531d77ca5b22a066ca01e091ad Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 19 Sep 2025 23:03:14 +0900 Subject: [PATCH 4/4] rename --- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 110 ++++++++++----------- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 44 ++++----- llvm/lib/Target/PowerPC/PPCRegisterInfo.td | 32 +++--- 3 files changed, 93 insertions(+), 93 deletions(-) diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 580286f00a425..269d30318bca8 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -693,66 +693,66 @@ def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc_nox0:$RA, tlsreg: "add $RT, $RA, $RB", IIC_IntSimple, [(set i64:$RT, (add i64:$RA, tglobaltlsaddr:$RB))]>; let mayLoad = 1 in { -def LBZXTLS : XForm_1<31, 87, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LBZXTLS : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LHZXTLS : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHAXTLS : XForm_1<31, 343, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LHAXTLS : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWZXTLS : XForm_1<31, 23, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LWZXTLS : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWAXTLS : XForm_1<31, 341, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LWAXTLS : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LDXTLS : XForm_1<31, 21, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LDXTLS : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; -def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LBZXTLS_32 : XForm_1<31, 87, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LHZXTLS_32 : XForm_1<31, 279, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHAXTLS_32 : XForm_1<31, 343, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LHAXTLS_32 : XForm_1<31, 343, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LWZXTLS_32 : XForm_1<31, 23, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWAXTLS_32 : XForm_1<31, 341, (outs gprc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LWAXTLS_32 : XForm_1<31, 341, (outs gprc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; } let mayLoad = 1, Predicates = [HasFPU] in { -def LFSXTLS : XForm_25<31, 535, (outs f4rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LFSXTLS : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>; -def LFDXTLS : XForm_25<31, 599, (outs f8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LFDXTLS : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>; } let mayStore = 1 in { -def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STBXTLS : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stbx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STHXTLS : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "sthx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STWXTLS : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stwx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STDXTLS : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, PPC970_DGroup_Cracked; -def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STBXTLS_32 : XForm_8<31, 215, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stbx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STHXTLS_32 : XForm_8<31, 407, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "sthx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STWXTLS_32 : XForm_8<31, 151, (outs), (ins gprc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stwx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; } let mayStore = 1, Predicates = [HasFPU] in { -def STFSXTLS : XForm_8<31, 663, (outs), (ins f4rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STFSXTLS : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>, PPC970_DGroup_Cracked; -def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>, PPC970_DGroup_Cracked; } @@ -825,47 +825,47 @@ def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$RT), (ins g8rc:$RA, tlsreg:$RB), "add $RT, $RA, $RB", IIC_IntSimple, []>; let mayLoad = 1 in { -def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LBZXTLS_ : XForm_1<31, 87, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lbzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LHZXTLS_ : XForm_1<31, 279, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lhzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LHAXTLS_ : XForm_1<31, 343, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LHAXTLS_ : XForm_1<31, 343, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lhax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LWZXTLS_ : XForm_1<31, 23, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lwzx $RST, $RA, $RB", IIC_LdStLoad, []>; -def LWAXTLS_ : XForm_1<31, 341, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LWAXTLS_ : XForm_1<31, 341, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lwax $RST, $RA, $RB", IIC_LdStLoad, []>; -def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LDXTLS_ : XForm_1<31, 21, (outs g8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "ldx $RST, $RA, $RB", IIC_LdStLD, []>, isPPC64; } let mayLoad = 1, Predicates = [HasFPU] in { -def LFSXTLS_ : XForm_25<31, 535, (outs f4rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LFSXTLS_ : XForm_25<31, 535, (outs f4rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lfsx $RST, $RA, $RB", IIC_LdStLFD, []>; -def LFDXTLS_ : XForm_25<31, 599, (outs f8rc:$RST), (ins PtrOpNoR0:$RA, tlsreg:$RB), +def LFDXTLS_ : XForm_25<31, 599, (outs f8rc:$RST), (ins ptr_rc_nor0:$RA, tlsreg:$RB), "lfdx $RST, $RA, $RB", IIC_LdStLFD, []>; } let mayStore = 1 in { -def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STBXTLS_ : XForm_8<31, 215, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stbx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STHXTLS_ : XForm_8<31, 407, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "sthx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STWXTLS_ : XForm_8<31, 151, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stwx $RST, $RA, $RB", IIC_LdStStore, []>, PPC970_DGroup_Cracked; -def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STDXTLS_ : XForm_8<31, 149, (outs), (ins g8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stdx $RST, $RA, $RB", IIC_LdStSTD, []>, isPPC64, PPC970_DGroup_Cracked; } let mayStore = 1, Predicates = [HasFPU] in { -def STFSXTLS_ : XForm_8<31, 663, (outs), (ins f4rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STFSXTLS_ : XForm_8<31, 663, (outs), (ins f4rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stfsx $RST, $RA, $RB", IIC_LdStSTFD, []>, PPC970_DGroup_Cracked; -def STFDXTLS_ : XForm_8<31, 727, (outs), (ins f8rc:$RST, PtrOpNoR0:$RA, tlsreg:$RB), +def STFDXTLS_ : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:$RB), "stfdx $RST, $RA, $RB", IIC_LdStSTFD, []>, PPC970_DGroup_Cracked; } @@ -1309,18 +1309,18 @@ def LWAX_32 : XForm_1_memOp<31, 341, (outs gprc:$RST), (ins (memrr $RA, $RB):$ad // Update forms. let mayLoad = 1, hasSideEffects = 0 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in -def LHAU8 : DForm_1<43, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LHAU8 : DForm_1<43, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lhau $RST, $addr", IIC_LdStLHAU, []>, RegConstraint<"$addr.reg = $ea_result">; // NO LWAU! let Interpretation64Bit = 1, isCodeGenOnly = 1 in -def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LHAUX8 : XForm_1_memOp<31, 375, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lhaux $RST, $addr", IIC_LdStLHAUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LWAUX : XForm_1_memOp<31, 373, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lwaux $RST, $addr", IIC_LdStLHAUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, isPPC64; @@ -1359,28 +1359,28 @@ def LWZX8 : XForm_1_memOp<31, 23, (outs g8rc:$RST), (ins (memrr $RA, $RB):$addr // Update forms. let mayLoad = 1, hasSideEffects = 0 in { -def LBZU8 : DForm_1<35, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LBZU8 : DForm_1<35, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lbzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; -def LHZU8 : DForm_1<41, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LHZU8 : DForm_1<41, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lhzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; -def LWZU8 : DForm_1<33, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LWZU8 : DForm_1<33, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lwzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; -def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LBZUX8 : XForm_1_memOp<31, 119, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lbzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LHZUX8 : XForm_1_memOp<31, 311, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lhzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LWZUX8 : XForm_1_memOp<31, 55, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lwzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; @@ -1432,12 +1432,12 @@ def LWBRX8 : XForm_1_memOp<31, 534, (outs g8rc:$RST), (ins (memrr $RA, $RB):$ad } let mayLoad = 1, hasSideEffects = 0 in { -def LDU : DSForm_1<58, 1, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LDU : DSForm_1<58, 1, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memrix $D, $RA):$addr), "ldu $RST, $addr", IIC_LdStLDU, []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64; -def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, PtrOpNoR0:$ea_result), +def LDUX : XForm_1_memOp<31, 53, (outs g8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "ldux $RST, $addr", IIC_LdStLDUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">, isPPC64; @@ -1704,40 +1704,40 @@ def : Pat<(int_ppc_atomic_store_i128 i64:$lo, i64:$hi, ForceXForm:$dst), // Stores with Update (pre-inc). let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in { -def STBU8 : DForm_1<39, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), +def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), "stbu $RST, $addr", IIC_LdStSTU, []>, RegConstraint<"$addr.reg = $ea_res">; -def STHU8 : DForm_1<45, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), +def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), "sthu $RST, $addr", IIC_LdStSTU, []>, RegConstraint<"$addr.reg = $ea_res">; -def STWU8 : DForm_1<37, (outs PtrOpNoR0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), +def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memri $D, $RA):$addr), "stwu $RST, $addr", IIC_LdStSTU, []>, RegConstraint<"$addr.reg = $ea_res">; -def STBUX8: XForm_8_memOp<31, 247, (outs PtrOpNoR0:$ea_res), +def STBUX8: XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memrr $RA, $RB):$addr), "stbux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STHUX8: XForm_8_memOp<31, 439, (outs PtrOpNoR0:$ea_res), +def STHUX8: XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memrr $RA, $RB):$addr), "sthux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STWUX8: XForm_8_memOp<31, 183, (outs PtrOpNoR0:$ea_res), +def STWUX8: XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memrr $RA, $RB):$addr), "stwux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; } // Interpretation64Bit -def STDU : DSForm_1<62, 1, (outs PtrOpNoR0:$ea_res), +def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memrix $D, $RA):$addr), "stdu $RST, $addr", IIC_LdStSTU, []>, RegConstraint<"$addr.reg = $ea_res">, isPPC64; -def STDUX : XForm_8_memOp<31, 181, (outs PtrOpNoR0:$ea_res), +def STDUX : XForm_8_memOp<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$RST, (memrr $RA, $RB):$addr), "stdux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index c4ddbb8831147..1c45050cdf9ca 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1950,61 +1950,61 @@ def LFD : DForm_1<50, (outs f8rc:$RST), (ins (memri $D, $RA):$addr), // Unindexed (r+i) Loads with Update (preinc). let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in { -def LBZU : DForm_1<35, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), +def LBZU : DForm_1<35, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lbzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$RA = $ea_result">; -def LHAU : DForm_1<43, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), +def LHAU : DForm_1<43, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lhau $RST, $addr", IIC_LdStLHAU, []>, RegConstraint<"$addr.reg = $ea_result">; -def LHZU : DForm_1<41, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), +def LHZU : DForm_1<41, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lhzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; -def LWZU : DForm_1<33, (outs gprc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), +def LWZU : DForm_1<33, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lwzu $RST, $addr", IIC_LdStLoadUpd, []>, RegConstraint<"$addr.reg = $ea_result">; let Predicates = [HasFPU] in { -def LFSU : DForm_1<49, (outs f4rc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), +def LFSU : DForm_1<49, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lfsu $RST, $addr", IIC_LdStLFDU, []>, RegConstraint<"$addr.reg = $ea_result">; -def LFDU : DForm_1<51, (outs f8rc:$RST, PtrOpNoR0:$ea_result), (ins (memri $D, $RA):$addr), +def LFDU : DForm_1<51, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memri $D, $RA):$addr), "lfdu $RST, $addr", IIC_LdStLFDU, []>, RegConstraint<"$addr.reg = $ea_result">; } // Indexed (r+r) Loads with Update (preinc). -def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, PtrOpNoR0:$ea_result), +def LBZUX : XForm_1_memOp<31, 119, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lbzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, PtrOpNoR0:$ea_result), +def LHAUX : XForm_1_memOp<31, 375, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lhaux $RST, $addr", IIC_LdStLHAUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, PtrOpNoR0:$ea_result), +def LHZUX : XForm_1_memOp<31, 311, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lhzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, PtrOpNoR0:$ea_result), +def LWZUX : XForm_1_memOp<31, 55, (outs gprc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lwzux $RST, $addr", IIC_LdStLoadUpdX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; let Predicates = [HasFPU] in { -def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, PtrOpNoR0:$ea_result), +def LFSUX : XForm_1_memOp<31, 567, (outs f4rc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lfsux $RST, $addr", IIC_LdStLFDUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; -def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, PtrOpNoR0:$ea_result), +def LFDUX : XForm_1_memOp<31, 631, (outs f8rc:$RST, ptr_rc_nor0:$ea_result), (ins (memrr $RA, $RB):$addr), "lfdux $RST, $addr", IIC_LdStLFDUX, []>, RegConstraint<"$addr.ptrreg = $ea_result">; @@ -2086,20 +2086,20 @@ def STFD : DForm_1<54, (outs), (ins f8rc:$RST, (memri $D, $RA):$dst), // Unindexed (r+i) Stores with Update (preinc). let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { -def STBU : DForm_1<39, (outs PtrOpNoR0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), +def STBU : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), "stbu $RST, $dst", IIC_LdStSTU, []>, RegConstraint<"$dst.reg = $ea_res">; -def STHU : DForm_1<45, (outs PtrOpNoR0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), +def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), "sthu $RST, $dst", IIC_LdStSTU, []>, RegConstraint<"$dst.reg = $ea_res">; -def STWU : DForm_1<37, (outs PtrOpNoR0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), +def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memri $D, $RA):$dst), "stwu $RST, $dst", IIC_LdStSTU, []>, RegConstraint<"$dst.reg = $ea_res">; let Predicates = [HasFPU] in { -def STFSU : DForm_1<53, (outs PtrOpNoR0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst), +def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memri $D, $RA):$dst), "stfsu $RST, $dst", IIC_LdStSTFDU, []>, RegConstraint<"$dst.reg = $ea_res">; -def STFDU : DForm_1<55, (outs PtrOpNoR0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst), +def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memri $D, $RA):$dst), "stfdu $RST, $dst", IIC_LdStSTFDU, []>, RegConstraint<"$dst.reg = $ea_res">; } @@ -2159,28 +2159,28 @@ def STFDX : XForm_28_memOp<31, 727, (outs), (ins f8rc:$RST, (memrr $RA, $RB):$ad // Indexed (r+r) Stores with Update (preinc). let PPC970_Unit = 2, mayStore = 1, mayLoad = 0 in { -def STBUX : XForm_8_memOp<31, 247, (outs PtrOpNoR0:$ea_res), +def STBUX : XForm_8_memOp<31, 247, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memrr $RA, $RB):$addr), "stbux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STHUX : XForm_8_memOp<31, 439, (outs PtrOpNoR0:$ea_res), +def STHUX : XForm_8_memOp<31, 439, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memrr $RA, $RB):$addr), "sthux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STWUX : XForm_8_memOp<31, 183, (outs PtrOpNoR0:$ea_res), +def STWUX : XForm_8_memOp<31, 183, (outs ptr_rc_nor0:$ea_res), (ins gprc:$RST, (memrr $RA, $RB):$addr), "stwux $RST, $addr", IIC_LdStSTUX, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; let Predicates = [HasFPU] in { -def STFSUX: XForm_8_memOp<31, 695, (outs PtrOpNoR0:$ea_res), +def STFSUX: XForm_8_memOp<31, 695, (outs ptr_rc_nor0:$ea_res), (ins f4rc:$RST, (memrr $RA, $RB):$addr), "stfsux $RST, $addr", IIC_LdStSTFDU, []>, RegConstraint<"$addr.ptrreg = $ea_res">, PPC970_DGroup_Cracked; -def STFDUX: XForm_8_memOp<31, 759, (outs PtrOpNoR0:$ea_res), +def STFDUX: XForm_8_memOp<31, 759, (outs ptr_rc_nor0:$ea_res), (ins f8rc:$RST, (memrr $RA, $RB):$addr), "stfdux $RST, $addr", IIC_LdStSTFDU, []>, RegConstraint<"$addr.ptrreg = $ea_res">, diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index 9fa965afa10aa..6d8c1223adf78 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -869,15 +869,14 @@ def PPCRegGxRCNoR0Operand : AsmOperandClass { let Name = "RegGxRCNoR0"; let PredicateMethod = "isRegNumber"; } -def ptr_rc_nor0 : RegClassByHwMode< +def ptr_rc_nor0_by_hwmode : RegClassByHwMode< [PPC32, PPC64], [GPRC_NOR0, G8RC_NOX0]>; -def PtrOpNoR0 : RegisterOperand { +def ptr_rc_nor0 : RegisterOperand { let ParserMatchClass = PPCRegGxRCNoR0Operand; } - // New addressing modes with 34 bit immediates. def PPCDispRI34Operand : AsmOperandClass { let Name = "DispRI34"; let PredicateMethod = "isS34Imm"; @@ -895,7 +894,7 @@ def dispRI34_pcrel : Operand { } def memri34 : Operand { // memri, imm is a 34-bit value. let PrintMethod = "printMemRegImm34"; - let MIOperandInfo = (ops dispRI34:$imm, PtrOpNoR0:$reg); + let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); } // memri, imm is a 34-bit value for pc-relative instructions where // base register is set to zero. @@ -908,10 +907,11 @@ def memri34_pcrel : Operand { // memri, imm is a 34-bit value. def PPCRegGxRCOperand : AsmOperandClass { let Name = "RegGxRC"; let PredicateMethod = "isRegNumber"; } -def ptr_rc_idx : RegClassByHwMode<[PPC32, PPC64], - [GPRC, G8RC]>; -def PtrRCIdxOp : RegisterOperand { +def ptr_rc_idx_by_hwmode : RegClassByHwMode<[PPC32, PPC64], + [GPRC, G8RC]>; + +def ptr_rc_idx : RegisterOperand { let ParserMatchClass = PPCRegGxRCOperand; } @@ -981,43 +981,43 @@ def dispSPE2 : Operand { def memri : Operand { let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispRI:$imm, PtrOpNoR0:$reg); + let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); let OperandType = "OPERAND_MEMORY"; } def memrr : Operand { let PrintMethod = "printMemRegReg"; - let MIOperandInfo = (ops PtrOpNoR0:$ptrreg, PtrRCIdxOp:$offreg); + let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg, ptr_rc_idx:$offreg); let OperandType = "OPERAND_MEMORY"; } def memrix : Operand { // memri where the imm is 4-aligned. let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispRIX:$imm, PtrOpNoR0:$reg); + let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); let OperandType = "OPERAND_MEMORY"; } def memrihash : Operand { // memrihash 8-aligned for ROP Protection Instructions. let PrintMethod = "printMemRegImmHash"; - let MIOperandInfo = (ops dispRIHash:$imm, PtrOpNoR0:$reg); + let MIOperandInfo = (ops dispRIHash:$imm, ptr_rc_nor0:$reg); let OperandType = "OPERAND_MEMORY"; } def memrix16 : Operand { // memri, imm is 16-aligned, 12-bit, Inst{16:27} let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispRIX16:$imm, PtrOpNoR0:$reg); + let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); let OperandType = "OPERAND_MEMORY"; } def spe8dis : Operand { // SPE displacement where the imm is 8-aligned. let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispSPE8:$imm, PtrOpNoR0:$reg); + let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); let OperandType = "OPERAND_MEMORY"; } def spe4dis : Operand { // SPE displacement where the imm is 4-aligned. let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispSPE4:$imm, PtrOpNoR0:$reg); + let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); let OperandType = "OPERAND_MEMORY"; } def spe2dis : Operand { // SPE displacement where the imm is 2-aligned. let PrintMethod = "printMemRegImm"; - let MIOperandInfo = (ops dispSPE2:$imm, PtrOpNoR0:$reg); + let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); let OperandType = "OPERAND_MEMORY"; } @@ -1025,7 +1025,7 @@ def spe2dis : Operand { // SPE displacement where the imm is 2-aligned. // pseudo-instructions which translates to LD/LWZ. These instructions requires // G8RC_NOX0 registers. def memr : Operand { - let MIOperandInfo = (ops PtrOpNoR0:$ptrreg); + let MIOperandInfo = (ops ptr_rc_nor0:$ptrreg); let OperandType = "OPERAND_MEMORY"; } def PPCTLSRegOperand : AsmOperandClass {