From 1d9cd9ac32dba3fbf02bf85de7c62ebb3358ec05 Mon Sep 17 00:00:00 2001 From: John Lu Date: Fri, 19 Sep 2025 11:48:39 -0500 Subject: [PATCH 1/9] Calc IsVALU correctly during UADDO/USUBO selection Signed-off-by: John Lu --- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 15 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 9 +- .../AMDGPU/amdgpu-codegenprepare-idiv.ll | 3170 ++++++++-------- .../test/CodeGen/AMDGPU/carryout-selection.ll | 1815 +++++---- .../expand-scalar-carry-out-select-user.ll | 61 +- llvm/test/CodeGen/AMDGPU/sdiv64.ll | 492 +-- llvm/test/CodeGen/AMDGPU/srem.ll | 3329 +++++++++-------- llvm/test/CodeGen/AMDGPU/srem64.ll | 745 ++-- llvm/test/CodeGen/AMDGPU/udiv64.ll | 209 +- llvm/test/CodeGen/AMDGPU/urem64.ll | 469 ++- llvm/test/CodeGen/AMDGPU/wave32.ll | 514 ++- 11 files changed, 5699 insertions(+), 5129 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp index ae5284a18de27..2192a72bb27b7 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp @@ -1089,10 +1089,17 @@ void AMDGPUDAGToDAGISel::SelectUADDO_USUBO(SDNode *N) { for (SDNode::user_iterator UI = N->user_begin(), E = N->user_end(); UI != E; ++UI) if (UI.getUse().getResNo() == 1) { - if ((IsAdd && (UI->getOpcode() != ISD::UADDO_CARRY)) || - (!IsAdd && (UI->getOpcode() != ISD::USUBO_CARRY))) { - IsVALU = true; - break; + if (UI->isMachineOpcode()) { + if (UI->getMachineOpcode() != + (IsAdd ? AMDGPU::S_ADD_CO_PSEUDO : AMDGPU::S_SUB_CO_PSEUDO)) { + IsVALU = true; + break; + } + } else { + if (UI->getOpcode() != (IsAdd ? ISD::UADDO_CARRY : ISD::USUBO_CARRY)) { + IsVALU = true; + break; + } } } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index afefd01ffb3ba..b1368329284c3 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5970,9 +5970,12 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, .add(Src1); // clang-format on - BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_CSELECT_B64), Dest1.getReg()) - .addImm(1) - .addImm(0); + const TargetRegisterClass *Dest1RC = MRI.getRegClass(Dest1.getReg()); + unsigned Dest1Size = TRI->getRegSizeInBits(*Dest1RC); + assert(Dest1Size == 64 || Dest1Size == 32); + unsigned SelOpc = + (Dest1Size == 64) ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32; + BuildMI(*BB, MI, DL, TII->get(SelOpc), Dest1.getReg()).addImm(1).addImm(0); MI.eraseFromParent(); return BB; diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index b2dcd77274989..e68353e5223fb 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -7792,8 +7792,9 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-LABEL: sdiv_i64_pow2_shl_denom: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd -; GFX6-NEXT: s_mov_b32 s7, 0xf000 -; GFX6-NEXT: s_mov_b32 s6, -1 +; GFX6-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 +; GFX6-NEXT: s_mov_b32 s3, 0xf000 +; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s0 ; GFX6-NEXT: s_ashr_i32 s8, s1, 31 @@ -7803,143 +7804,175 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9] ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s11 -; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 -; GFX6-NEXT: s_sub_u32 s4, 0, s10 -; GFX6-NEXT: s_subb_u32 s5, 0, s11 +; GFX6-NEXT: s_sub_u32 s12, 0, s10 +; GFX6-NEXT: s_subb_u32 s13, 0, s11 ; GFX6-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0 -; GFX6-NEXT: s_waitcnt lgkmcnt(0) -; GFX6-NEXT: s_ashr_i32 s12, s3, 31 -; GFX6-NEXT: s_add_u32 s2, s2, s12 -; GFX6-NEXT: s_mov_b32 s13, s12 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: s_addc_u32 s3, s3, s12 -; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13] -; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0 -; GFX6-NEXT: v_mul_lo_u32 v5, s5, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s4, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4 -; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v0, v2 -; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 -; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 -; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s5, v0 -; GFX6-NEXT: s_mov_b32 s5, s1 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, s4, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v8, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 -; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0 -; GFX6-NEXT: v_mul_hi_u32 v4, s2, v1 -; GFX6-NEXT: v_mul_hi_u32 v5, s3, v1 -; GFX6-NEXT: v_mul_lo_u32 v1, s3, v1 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0 -; GFX6-NEXT: v_mul_hi_u32 v0, s3, v0 -; GFX6-NEXT: s_mov_b32 s4, s0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, s10, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s10, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s11, v0 -; GFX6-NEXT: v_mov_b32_e32 v5, s11 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, s10, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 -; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s3, v2 -; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s2, v3 -; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc -; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s10, v3 -; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v5 -; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] -; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 1, v0 -; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0 -; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] -; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1] -; GFX6-NEXT: v_mov_b32_e32 v6, s3 -; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v2 -; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 -; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s11, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX6-NEXT: s_xor_b64 s[0:1], s[12:13], s[8:9] -; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0 -; GFX6-NEXT: v_xor_b32_e32 v1, s1, v1 +; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX6-NEXT: v_mul_hi_u32 v2, s12, v0 +; GFX6-NEXT: v_readfirstlane_b32 s14, v1 +; GFX6-NEXT: v_readfirstlane_b32 s0, v0 +; GFX6-NEXT: s_mul_i32 s1, s12, s14 +; GFX6-NEXT: v_readfirstlane_b32 s17, v2 +; GFX6-NEXT: s_mul_i32 s15, s13, s0 +; GFX6-NEXT: s_mul_i32 s16, s12, s0 +; GFX6-NEXT: s_add_i32 s1, s17, s1 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s16 +; GFX6-NEXT: s_add_i32 s1, s1, s15 +; GFX6-NEXT: v_mul_hi_u32 v0, v0, s1 +; GFX6-NEXT: v_mul_hi_u32 v4, v1, s16 +; GFX6-NEXT: v_readfirstlane_b32 s15, v3 +; GFX6-NEXT: s_mul_i32 s17, s0, s1 +; GFX6-NEXT: v_mul_hi_u32 v1, v1, s1 +; GFX6-NEXT: s_add_u32 s15, s15, s17 +; GFX6-NEXT: v_readfirstlane_b32 s17, v0 +; GFX6-NEXT: s_addc_u32 s17, 0, s17 +; GFX6-NEXT: s_mul_i32 s16, s14, s16 +; GFX6-NEXT: v_readfirstlane_b32 s18, v4 +; GFX6-NEXT: s_add_u32 s15, s15, s16 +; GFX6-NEXT: s_addc_u32 s15, s17, s18 +; GFX6-NEXT: v_readfirstlane_b32 s16, v1 +; GFX6-NEXT: s_addc_u32 s16, s16, 0 +; GFX6-NEXT: s_mul_i32 s1, s14, s1 +; GFX6-NEXT: s_add_u32 s1, s15, s1 +; GFX6-NEXT: s_addc_u32 s15, 0, s16 +; GFX6-NEXT: s_add_i32 s16, s0, s1 +; GFX6-NEXT: v_mov_b32_e32 v0, s16 +; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GFX6-NEXT: v_mul_hi_u32 v0, s12, v0 +; GFX6-NEXT: s_or_b32 s0, s0, s1 +; GFX6-NEXT: s_cmp_lg_u32 s0, 0 +; GFX6-NEXT: s_addc_u32 s14, s14, s15 +; GFX6-NEXT: s_mul_i32 s0, s12, s14 +; GFX6-NEXT: v_readfirstlane_b32 s1, v0 +; GFX6-NEXT: s_add_i32 s0, s1, s0 +; GFX6-NEXT: s_mul_i32 s13, s13, s16 +; GFX6-NEXT: s_mul_i32 s1, s12, s16 +; GFX6-NEXT: s_add_i32 s0, s0, s13 ; GFX6-NEXT: v_mov_b32_e32 v2, s1 -; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 -; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc -; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX6-NEXT: v_mov_b32_e32 v0, s0 +; GFX6-NEXT: v_mul_hi_u32 v3, s14, v2 +; GFX6-NEXT: v_mul_hi_u32 v2, s16, v2 +; GFX6-NEXT: v_mul_hi_u32 v1, s14, v0 +; GFX6-NEXT: v_mul_hi_u32 v0, s16, v0 +; GFX6-NEXT: s_mul_i32 s13, s16, s0 +; GFX6-NEXT: v_readfirstlane_b32 s17, v2 +; GFX6-NEXT: s_add_u32 s13, s17, s13 +; GFX6-NEXT: v_readfirstlane_b32 s15, v0 +; GFX6-NEXT: s_mul_i32 s1, s14, s1 +; GFX6-NEXT: s_addc_u32 s15, 0, s15 +; GFX6-NEXT: v_readfirstlane_b32 s12, v3 +; GFX6-NEXT: s_add_u32 s1, s13, s1 +; GFX6-NEXT: s_addc_u32 s1, s15, s12 +; GFX6-NEXT: v_readfirstlane_b32 s12, v1 +; GFX6-NEXT: s_addc_u32 s12, s12, 0 +; GFX6-NEXT: s_mul_i32 s0, s14, s0 +; GFX6-NEXT: s_add_u32 s0, s1, s0 +; GFX6-NEXT: s_addc_u32 s12, 0, s12 +; GFX6-NEXT: s_add_i32 s15, s16, s0 +; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GFX6-NEXT: s_or_b32 s0, s0, s1 +; GFX6-NEXT: s_cmp_lg_u32 s0, 0 +; GFX6-NEXT: s_addc_u32 s14, s14, s12 +; GFX6-NEXT: s_ashr_i32 s12, s7, 31 +; GFX6-NEXT: s_add_u32 s0, s6, s12 +; GFX6-NEXT: s_mov_b32 s13, s12 +; GFX6-NEXT: s_addc_u32 s1, s7, s12 +; GFX6-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13] +; GFX6-NEXT: v_mov_b32_e32 v0, s14 +; GFX6-NEXT: v_mul_hi_u32 v1, s6, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, s15 +; GFX6-NEXT: v_mul_hi_u32 v3, s6, v2 +; GFX6-NEXT: s_mov_b32 s0, s4 +; GFX6-NEXT: v_readfirstlane_b32 s4, v1 +; GFX6-NEXT: v_mul_hi_u32 v1, s7, v2 +; GFX6-NEXT: s_mul_i32 s1, s6, s14 +; GFX6-NEXT: v_readfirstlane_b32 s16, v3 +; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0 +; GFX6-NEXT: s_add_u32 s1, s16, s1 +; GFX6-NEXT: s_addc_u32 s4, 0, s4 +; GFX6-NEXT: s_mul_i32 s15, s7, s15 +; GFX6-NEXT: v_readfirstlane_b32 s16, v1 +; GFX6-NEXT: s_add_u32 s1, s1, s15 +; GFX6-NEXT: s_addc_u32 s1, s4, s16 +; GFX6-NEXT: v_readfirstlane_b32 s4, v0 +; GFX6-NEXT: s_addc_u32 s4, s4, 0 +; GFX6-NEXT: s_mul_i32 s14, s7, s14 +; GFX6-NEXT: s_add_u32 s14, s1, s14 +; GFX6-NEXT: v_mov_b32_e32 v0, s14 +; GFX6-NEXT: v_mul_hi_u32 v0, s10, v0 +; GFX6-NEXT: s_addc_u32 s15, 0, s4 +; GFX6-NEXT: s_mov_b32 s1, s5 +; GFX6-NEXT: s_mul_i32 s4, s10, s15 +; GFX6-NEXT: v_readfirstlane_b32 s5, v0 +; GFX6-NEXT: s_add_i32 s4, s5, s4 +; GFX6-NEXT: s_mul_i32 s5, s11, s14 +; GFX6-NEXT: s_add_i32 s16, s4, s5 +; GFX6-NEXT: s_sub_i32 s17, s7, s16 +; GFX6-NEXT: s_mul_i32 s4, s10, s14 +; GFX6-NEXT: s_sub_i32 s6, s6, s4 +; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_or_b32 s18, s4, s5 +; GFX6-NEXT: s_cmp_lg_u32 s18, 0 +; GFX6-NEXT: s_subb_u32 s17, s17, s11 +; GFX6-NEXT: s_sub_i32 s19, s6, s10 +; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_or_b32 s4, s4, s5 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-NEXT: s_subb_u32 s4, s17, 0 +; GFX6-NEXT: s_cmp_ge_u32 s4, s11 +; GFX6-NEXT: s_cselect_b32 s5, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s19, s10 +; GFX6-NEXT: s_cselect_b32 s17, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s4, s11 +; GFX6-NEXT: s_cselect_b32 s4, s17, s5 +; GFX6-NEXT: s_add_u32 s5, s14, 1 +; GFX6-NEXT: s_addc_u32 s17, s15, 0 +; GFX6-NEXT: s_add_u32 s19, s14, 2 +; GFX6-NEXT: s_addc_u32 s20, s15, 0 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-NEXT: s_cselect_b32 s4, s19, s5 +; GFX6-NEXT: s_cselect_b32 s5, s20, s17 +; GFX6-NEXT: s_cmp_lg_u32 s18, 0 +; GFX6-NEXT: s_subb_u32 s7, s7, s16 +; GFX6-NEXT: s_cmp_ge_u32 s7, s11 +; GFX6-NEXT: s_cselect_b32 s16, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s6, s10 +; GFX6-NEXT: s_cselect_b32 s6, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s7, s11 +; GFX6-NEXT: s_cselect_b32 s6, s6, s16 +; GFX6-NEXT: s_cmp_lg_u32 s6, 0 +; GFX6-NEXT: s_cselect_b32 s5, s5, s15 +; GFX6-NEXT: s_cselect_b32 s4, s4, s14 +; GFX6-NEXT: s_xor_b64 s[6:7], s[12:13], s[8:9] +; GFX6-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] +; GFX6-NEXT: s_sub_u32 s4, s4, s6 +; GFX6-NEXT: s_subb_u32 s5, s5, s7 +; GFX6-NEXT: v_mov_b32_e32 v0, s4 +; GFX6-NEXT: v_mov_b32_e32 v1, s5 +; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX6-NEXT: s_endpgm ; ; GFX9-LABEL: sdiv_i64_pow2_shl_denom: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34 -; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s0 -; GFX9-NEXT: s_ashr_i32 s2, s1, 31 -; GFX9-NEXT: s_add_u32 s0, s0, s2 -; GFX9-NEXT: s_mov_b32 s3, s2 -; GFX9-NEXT: s_addc_u32 s1, s1, s2 -; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[2:3] -; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 -; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7 -; GFX9-NEXT: s_sub_u32 s0, 0, s6 -; GFX9-NEXT: s_subb_u32 s1, 0, s7 +; GFX9-NEXT: s_ashr_i32 s6, s1, 31 +; GFX9-NEXT: s_add_u32 s0, s0, s6 +; GFX9-NEXT: s_mov_b32 s7, s6 +; GFX9-NEXT: s_addc_u32 s1, s1, s6 +; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[6:7] +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s9 +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: s_sub_u32 s10, 0, s8 +; GFX9-NEXT: s_subb_u32 s11, 0, s9 ; GFX9-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GFX9-NEXT: v_rcp_f32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 @@ -7949,130 +7982,122 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: v_madmk_f32 v1, v2, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX9-NEXT: v_readfirstlane_b32 s4, v2 -; GFX9-NEXT: v_readfirstlane_b32 s5, v1 -; GFX9-NEXT: s_mul_i32 s12, s0, s4 -; GFX9-NEXT: s_mul_hi_u32 s14, s0, s5 -; GFX9-NEXT: s_mul_i32 s13, s1, s5 -; GFX9-NEXT: s_add_i32 s12, s14, s12 -; GFX9-NEXT: s_mul_i32 s15, s0, s5 -; GFX9-NEXT: s_add_i32 s12, s12, s13 -; GFX9-NEXT: s_mul_hi_u32 s14, s5, s15 -; GFX9-NEXT: s_mul_hi_u32 s13, s5, s12 -; GFX9-NEXT: s_mul_i32 s5, s5, s12 -; GFX9-NEXT: s_add_u32 s5, s14, s5 +; GFX9-NEXT: v_readfirstlane_b32 s12, v2 +; GFX9-NEXT: v_readfirstlane_b32 s4, v1 +; GFX9-NEXT: s_mul_i32 s5, s10, s12 +; GFX9-NEXT: s_mul_hi_u32 s14, s10, s4 +; GFX9-NEXT: s_mul_i32 s13, s11, s4 +; GFX9-NEXT: s_add_i32 s5, s14, s5 +; GFX9-NEXT: s_mul_i32 s15, s10, s4 +; GFX9-NEXT: s_add_i32 s5, s5, s13 +; GFX9-NEXT: s_mul_hi_u32 s14, s4, s15 +; GFX9-NEXT: s_mul_i32 s16, s4, s5 +; GFX9-NEXT: s_mul_hi_u32 s13, s4, s5 +; GFX9-NEXT: s_add_u32 s14, s14, s16 ; GFX9-NEXT: s_addc_u32 s13, 0, s13 -; GFX9-NEXT: s_mul_hi_u32 s16, s4, s15 -; GFX9-NEXT: s_mul_i32 s15, s4, s15 -; GFX9-NEXT: s_add_u32 s5, s5, s15 -; GFX9-NEXT: s_mul_hi_u32 s14, s4, s12 -; GFX9-NEXT: s_addc_u32 s5, s13, s16 -; GFX9-NEXT: s_addc_u32 s13, s14, 0 -; GFX9-NEXT: s_mul_i32 s12, s4, s12 -; GFX9-NEXT: s_add_u32 s5, s5, s12 -; GFX9-NEXT: s_addc_u32 s12, 0, s13 -; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s5, v1 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s4, s4, s12 -; GFX9-NEXT: v_readfirstlane_b32 s12, v1 -; GFX9-NEXT: s_mul_i32 s5, s0, s4 -; GFX9-NEXT: s_mul_hi_u32 s13, s0, s12 -; GFX9-NEXT: s_add_i32 s5, s13, s5 -; GFX9-NEXT: s_mul_i32 s1, s1, s12 -; GFX9-NEXT: s_add_i32 s5, s5, s1 -; GFX9-NEXT: s_mul_i32 s0, s0, s12 -; GFX9-NEXT: s_mul_hi_u32 s13, s4, s0 -; GFX9-NEXT: s_mul_i32 s14, s4, s0 -; GFX9-NEXT: s_mul_i32 s16, s12, s5 -; GFX9-NEXT: s_mul_hi_u32 s0, s12, s0 -; GFX9-NEXT: s_mul_hi_u32 s15, s12, s5 -; GFX9-NEXT: s_add_u32 s0, s0, s16 -; GFX9-NEXT: s_addc_u32 s12, 0, s15 -; GFX9-NEXT: s_add_u32 s0, s0, s14 -; GFX9-NEXT: s_mul_hi_u32 s1, s4, s5 -; GFX9-NEXT: s_addc_u32 s0, s12, s13 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 -; GFX9-NEXT: s_mul_i32 s5, s4, s5 -; GFX9-NEXT: s_add_u32 s0, s0, s5 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s12, s4, s1 -; GFX9-NEXT: s_ashr_i32 s4, s11, 31 -; GFX9-NEXT: s_add_u32 s0, s10, s4 +; GFX9-NEXT: s_mul_hi_u32 s17, s12, s15 +; GFX9-NEXT: s_mul_i32 s15, s12, s15 +; GFX9-NEXT: s_add_u32 s14, s14, s15 +; GFX9-NEXT: s_mul_hi_u32 s16, s12, s5 +; GFX9-NEXT: s_addc_u32 s13, s13, s17 +; GFX9-NEXT: s_addc_u32 s14, s16, 0 +; GFX9-NEXT: s_mul_i32 s5, s12, s5 +; GFX9-NEXT: s_add_u32 s5, s13, s5 +; GFX9-NEXT: s_addc_u32 s13, 0, s14 +; GFX9-NEXT: s_add_i32 s14, s4, s5 +; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-NEXT: s_addc_u32 s12, s12, s13 +; GFX9-NEXT: s_mul_i32 s4, s10, s12 +; GFX9-NEXT: s_mul_hi_u32 s5, s10, s14 +; GFX9-NEXT: s_add_i32 s4, s5, s4 +; GFX9-NEXT: s_mul_i32 s11, s11, s14 +; GFX9-NEXT: s_add_i32 s4, s4, s11 +; GFX9-NEXT: s_mul_i32 s10, s10, s14 +; GFX9-NEXT: s_mul_hi_u32 s11, s12, s10 +; GFX9-NEXT: s_mul_i32 s13, s12, s10 +; GFX9-NEXT: s_mul_i32 s16, s14, s4 +; GFX9-NEXT: s_mul_hi_u32 s10, s14, s10 +; GFX9-NEXT: s_mul_hi_u32 s15, s14, s4 +; GFX9-NEXT: s_add_u32 s10, s10, s16 +; GFX9-NEXT: s_addc_u32 s15, 0, s15 +; GFX9-NEXT: s_add_u32 s10, s10, s13 +; GFX9-NEXT: s_mul_hi_u32 s5, s12, s4 +; GFX9-NEXT: s_addc_u32 s10, s15, s11 +; GFX9-NEXT: s_addc_u32 s5, s5, 0 +; GFX9-NEXT: s_mul_i32 s4, s12, s4 +; GFX9-NEXT: s_add_u32 s4, s10, s4 +; GFX9-NEXT: s_addc_u32 s10, 0, s5 +; GFX9-NEXT: s_add_i32 s14, s14, s4 +; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-NEXT: s_addc_u32 s10, s12, s10 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_ashr_i32 s4, s3, 31 +; GFX9-NEXT: s_add_u32 s2, s2, s4 ; GFX9-NEXT: s_mov_b32 s5, s4 -; GFX9-NEXT: s_addc_u32 s1, s11, s4 -; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[4:5] -; GFX9-NEXT: v_readfirstlane_b32 s13, v1 -; GFX9-NEXT: s_mul_i32 s1, s10, s12 -; GFX9-NEXT: s_mul_hi_u32 s14, s10, s13 -; GFX9-NEXT: s_mul_hi_u32 s0, s10, s12 -; GFX9-NEXT: s_add_u32 s1, s14, s1 -; GFX9-NEXT: s_addc_u32 s0, 0, s0 -; GFX9-NEXT: s_mul_hi_u32 s15, s11, s13 -; GFX9-NEXT: s_mul_i32 s13, s11, s13 -; GFX9-NEXT: s_add_u32 s1, s1, s13 -; GFX9-NEXT: s_mul_hi_u32 s14, s11, s12 -; GFX9-NEXT: s_addc_u32 s0, s0, s15 -; GFX9-NEXT: s_addc_u32 s1, s14, 0 -; GFX9-NEXT: s_mul_i32 s12, s11, s12 -; GFX9-NEXT: s_add_u32 s12, s0, s12 -; GFX9-NEXT: s_addc_u32 s13, 0, s1 -; GFX9-NEXT: s_mul_i32 s0, s6, s13 -; GFX9-NEXT: s_mul_hi_u32 s1, s6, s12 -; GFX9-NEXT: s_add_i32 s0, s1, s0 -; GFX9-NEXT: s_mul_i32 s1, s7, s12 -; GFX9-NEXT: s_add_i32 s14, s0, s1 -; GFX9-NEXT: s_mul_i32 s1, s6, s12 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: s_sub_i32 s0, s11, s14 -; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, s10, v1 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_subb_u32 s10, s0, s7 -; GFX9-NEXT: v_subrev_co_u32_e64 v2, s[0:1], s6, v1 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s10, s10, 0 -; GFX9-NEXT: s_cmp_ge_u32 s10, s7 -; GFX9-NEXT: s_cselect_b32 s15, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v2 -; GFX9-NEXT: s_cmp_eq_u32 s10, s7 -; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v3, s15 -; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[0:1] -; GFX9-NEXT: s_add_u32 s0, s12, 1 -; GFX9-NEXT: s_addc_u32 s10, s13, 0 -; GFX9-NEXT: s_add_u32 s1, s12, 2 -; GFX9-NEXT: s_addc_u32 s15, s13, 0 -; GFX9-NEXT: v_mov_b32_e32 v3, s0 -; GFX9-NEXT: v_mov_b32_e32 v4, s1 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v3, s10 -; GFX9-NEXT: v_mov_b32_e32 v4, s15 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1] -; GFX9-NEXT: s_subb_u32 s0, s11, s14 -; GFX9-NEXT: s_cmp_ge_u32 s0, s7 -; GFX9-NEXT: s_cselect_b32 s1, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v1 -; GFX9-NEXT: s_cmp_eq_u32 s0, s7 -; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc -; GFX9-NEXT: v_mov_b32_e32 v4, s1 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; GFX9-NEXT: v_mov_b32_e32 v4, s13 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc -; GFX9-NEXT: v_mov_b32_e32 v3, s12 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc -; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[2:3] -; GFX9-NEXT: v_xor_b32_e32 v2, s0, v2 -; GFX9-NEXT: v_xor_b32_e32 v3, s1, v1 -; GFX9-NEXT: v_mov_b32_e32 v4, s1 -; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s0, v2 -; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v3, v4, vcc -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[8:9] +; GFX9-NEXT: s_addc_u32 s3, s3, s4 +; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: s_mul_i32 s12, s2, s10 +; GFX9-NEXT: s_mul_hi_u32 s13, s2, s14 +; GFX9-NEXT: s_mul_hi_u32 s11, s2, s10 +; GFX9-NEXT: s_add_u32 s12, s13, s12 +; GFX9-NEXT: s_addc_u32 s11, 0, s11 +; GFX9-NEXT: s_mul_hi_u32 s15, s3, s14 +; GFX9-NEXT: s_mul_i32 s14, s3, s14 +; GFX9-NEXT: s_add_u32 s12, s12, s14 +; GFX9-NEXT: s_mul_hi_u32 s13, s3, s10 +; GFX9-NEXT: s_addc_u32 s11, s11, s15 +; GFX9-NEXT: s_addc_u32 s12, s13, 0 +; GFX9-NEXT: s_mul_i32 s10, s3, s10 +; GFX9-NEXT: s_add_u32 s14, s11, s10 +; GFX9-NEXT: s_addc_u32 s15, 0, s12 +; GFX9-NEXT: s_mul_i32 s10, s8, s15 +; GFX9-NEXT: s_mul_hi_u32 s11, s8, s14 +; GFX9-NEXT: s_add_i32 s10, s11, s10 +; GFX9-NEXT: s_mul_i32 s11, s9, s14 +; GFX9-NEXT: s_add_i32 s16, s10, s11 +; GFX9-NEXT: s_sub_i32 s12, s3, s16 +; GFX9-NEXT: s_mul_i32 s10, s8, s14 +; GFX9-NEXT: s_sub_i32 s2, s2, s10 +; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s17, s12, s9 +; GFX9-NEXT: s_sub_i32 s18, s2, s8 +; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GFX9-NEXT: s_subb_u32 s12, s17, 0 +; GFX9-NEXT: s_cmp_ge_u32 s12, s9 +; GFX9-NEXT: s_cselect_b32 s13, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s18, s8 +; GFX9-NEXT: s_cselect_b32 s17, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s12, s9 +; GFX9-NEXT: s_cselect_b32 s12, s17, s13 +; GFX9-NEXT: s_add_u32 s13, s14, 1 +; GFX9-NEXT: s_addc_u32 s17, s15, 0 +; GFX9-NEXT: s_add_u32 s18, s14, 2 +; GFX9-NEXT: s_addc_u32 s19, s15, 0 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b32 s12, s18, s13 +; GFX9-NEXT: s_cselect_b32 s13, s19, s17 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s3, s3, s16 +; GFX9-NEXT: s_cmp_ge_u32 s3, s9 +; GFX9-NEXT: s_cselect_b32 s10, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s2, s8 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s3, s9 +; GFX9-NEXT: s_cselect_b32 s2, s2, s10 +; GFX9-NEXT: s_cmp_lg_u32 s2, 0 +; GFX9-NEXT: s_cselect_b32 s3, s13, s15 +; GFX9-NEXT: s_cselect_b32 s2, s12, s14 +; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] +; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: s_sub_u32 s2, s2, s4 +; GFX9-NEXT: s_subb_u32 s3, s3, s5 +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: v_mov_b32_e32 v2, s3 +; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] ; GFX9-NEXT: s_endpgm %shl.y = shl i64 4096, %y %r = sdiv i64 %x, %shl.y @@ -8276,276 +8301,343 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-LABEL: sdiv_v2i64_pow2_shl_denom: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd -; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 -; GFX6-NEXT: s_mov_b32 s7, 0xf000 -; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) -; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s12 -; GFX6-NEXT: s_lshl_b64 s[14:15], 0x1000, s14 -; GFX6-NEXT: s_ashr_i32 s12, s1, 31 -; GFX6-NEXT: s_add_u32 s0, s0, s12 -; GFX6-NEXT: s_mov_b32 s13, s12 -; GFX6-NEXT: s_addc_u32 s1, s1, s12 -; GFX6-NEXT: s_xor_b64 s[2:3], s[0:1], s[12:13] -; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3 -; GFX6-NEXT: s_sub_u32 s0, 0, s2 -; GFX6-NEXT: s_subb_u32 s1, 0, s3 -; GFX6-NEXT: s_ashr_i32 s16, s9, 31 +; GFX6-NEXT: s_lshl_b64 s[6:7], 0x1000, s12 +; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s14 +; GFX6-NEXT: s_ashr_i32 s2, s7, 31 +; GFX6-NEXT: s_add_u32 s6, s6, s2 +; GFX6-NEXT: s_mov_b32 s3, s2 +; GFX6-NEXT: s_addc_u32 s7, s7, s2 +; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3] +; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GFX6-NEXT: s_sub_u32 s14, 0, s6 +; GFX6-NEXT: s_subb_u32 s15, 0, s7 ; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0 -; GFX6-NEXT: s_mov_b32 s17, s16 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 -; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0 -; GFX6-NEXT: v_mul_lo_u32 v5, s1, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s0, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4 -; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v6, v1, v4 -; GFX6-NEXT: v_mul_lo_u32 v4, v1, v4 -; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, s0, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v8, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 -; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: s_add_u32 s0, s8, s16 -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GFX6-NEXT: s_addc_u32 s1, s9, s16 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[16:17] -; GFX6-NEXT: v_mul_lo_u32 v2, s8, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s8, v0 -; GFX6-NEXT: v_mul_hi_u32 v4, s8, v1 -; GFX6-NEXT: v_mul_hi_u32 v5, s9, v1 -; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s9, v0 +; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX6-NEXT: v_mul_hi_u32 v2, s14, v0 +; GFX6-NEXT: v_readfirstlane_b32 s16, v1 +; GFX6-NEXT: v_readfirstlane_b32 s12, v0 +; GFX6-NEXT: s_mul_i32 s13, s14, s16 +; GFX6-NEXT: v_readfirstlane_b32 s19, v2 +; GFX6-NEXT: s_mul_i32 s17, s15, s12 +; GFX6-NEXT: s_mul_i32 s18, s14, s12 +; GFX6-NEXT: s_add_i32 s13, s19, s13 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s18 +; GFX6-NEXT: s_add_i32 s13, s13, s17 +; GFX6-NEXT: v_mul_hi_u32 v0, v0, s13 +; GFX6-NEXT: v_mul_hi_u32 v4, v1, s18 +; GFX6-NEXT: v_readfirstlane_b32 s17, v3 +; GFX6-NEXT: s_mul_i32 s20, s12, s13 +; GFX6-NEXT: v_mul_hi_u32 v1, v1, s13 +; GFX6-NEXT: s_add_u32 s17, s17, s20 +; GFX6-NEXT: v_readfirstlane_b32 s20, v0 +; GFX6-NEXT: s_mul_i32 s18, s16, s18 +; GFX6-NEXT: s_addc_u32 s20, 0, s20 +; GFX6-NEXT: v_readfirstlane_b32 s19, v4 +; GFX6-NEXT: s_add_u32 s17, s17, s18 +; GFX6-NEXT: s_addc_u32 s17, s20, s19 +; GFX6-NEXT: v_readfirstlane_b32 s18, v1 +; GFX6-NEXT: s_addc_u32 s18, s18, 0 +; GFX6-NEXT: s_mul_i32 s13, s16, s13 +; GFX6-NEXT: s_add_u32 s13, s17, s13 +; GFX6-NEXT: s_addc_u32 s17, 0, s18 +; GFX6-NEXT: s_add_i32 s18, s12, s13 +; GFX6-NEXT: v_mov_b32_e32 v0, s18 +; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: v_mul_hi_u32 v0, s14, v0 +; GFX6-NEXT: s_or_b32 s12, s12, s13 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_addc_u32 s16, s16, s17 +; GFX6-NEXT: s_mul_i32 s12, s14, s16 +; GFX6-NEXT: v_readfirstlane_b32 s13, v0 +; GFX6-NEXT: s_add_i32 s12, s13, s12 +; GFX6-NEXT: s_mul_i32 s15, s15, s18 +; GFX6-NEXT: s_mul_i32 s13, s14, s18 +; GFX6-NEXT: s_add_i32 s12, s12, s15 +; GFX6-NEXT: v_mov_b32_e32 v2, s13 +; GFX6-NEXT: v_mov_b32_e32 v0, s12 +; GFX6-NEXT: v_mul_hi_u32 v3, s16, v2 +; GFX6-NEXT: v_mul_hi_u32 v2, s18, v2 +; GFX6-NEXT: v_mul_hi_u32 v1, s16, v0 +; GFX6-NEXT: v_mul_hi_u32 v0, s18, v0 +; GFX6-NEXT: s_mul_i32 s15, s18, s12 +; GFX6-NEXT: v_readfirstlane_b32 s19, v2 +; GFX6-NEXT: s_add_u32 s15, s19, s15 +; GFX6-NEXT: v_readfirstlane_b32 s17, v0 +; GFX6-NEXT: s_mul_i32 s13, s16, s13 +; GFX6-NEXT: s_addc_u32 s17, 0, s17 +; GFX6-NEXT: v_readfirstlane_b32 s14, v3 +; GFX6-NEXT: s_add_u32 s13, s15, s13 +; GFX6-NEXT: s_addc_u32 s13, s17, s14 +; GFX6-NEXT: v_readfirstlane_b32 s14, v1 +; GFX6-NEXT: s_addc_u32 s14, s14, 0 +; GFX6-NEXT: s_mul_i32 s12, s16, s12 +; GFX6-NEXT: s_add_u32 s12, s13, s12 +; GFX6-NEXT: s_addc_u32 s14, 0, s14 +; GFX6-NEXT: s_add_i32 s15, s18, s12 +; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_or_b32 s12, s12, s13 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_addc_u32 s14, s16, s14 +; GFX6-NEXT: s_ashr_i32 s12, s9, 31 +; GFX6-NEXT: s_add_u32 s8, s8, s12 +; GFX6-NEXT: s_mov_b32 s13, s12 +; GFX6-NEXT: s_addc_u32 s9, s9, s12 +; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] +; GFX6-NEXT: v_mov_b32_e32 v0, s14 +; GFX6-NEXT: v_mul_hi_u32 v1, s8, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, s15 +; GFX6-NEXT: v_mul_hi_u32 v3, s8, v2 +; GFX6-NEXT: s_mul_i32 s16, s8, s14 +; GFX6-NEXT: v_readfirstlane_b32 s17, v1 +; GFX6-NEXT: v_mul_hi_u32 v1, s9, v2 +; GFX6-NEXT: v_readfirstlane_b32 s18, v3 ; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, s2, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s2, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s3, v0 -; GFX6-NEXT: v_mov_b32_e32 v5, s3 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, s2, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v4, v2 -; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s9, v2 -; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s8, v3 -; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc -; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3 -; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5 -; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] -; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v5, s[0:1], 1, v0 -; GFX6-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0 -; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] -; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1] -; GFX6-NEXT: s_xor_b64 s[0:1], s[16:17], s[12:13] -; GFX6-NEXT: s_ashr_i32 s8, s15, 31 -; GFX6-NEXT: s_add_u32 s12, s14, s8 -; GFX6-NEXT: v_mov_b32_e32 v6, s9 -; GFX6-NEXT: s_mov_b32 s9, s8 -; GFX6-NEXT: s_addc_u32 s13, s15, s8 -; GFX6-NEXT: s_xor_b64 s[12:13], s[12:13], s[8:9] -; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc -; GFX6-NEXT: v_cvt_f32_u32_e32 v6, s12 -; GFX6-NEXT: v_cvt_f32_u32_e32 v7, s13 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s3, v2 -; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 -; GFX6-NEXT: v_mac_f32_e32 v6, 0x4f800000, v7 -; GFX6-NEXT: v_rcp_f32_e32 v6, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GFX6-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v6 -; GFX6-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 -; GFX6-NEXT: v_trunc_f32_e32 v3, v3 -; GFX6-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 -; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX6-NEXT: s_sub_u32 s2, 0, s12 -; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GFX6-NEXT: v_mul_hi_u32 v4, s2, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, s2, v3 -; GFX6-NEXT: s_subb_u32 s3, 0, s13 -; GFX6-NEXT: v_mul_lo_u32 v6, s3, v2 -; GFX6-NEXT: v_xor_b32_e32 v0, s0, v0 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_mul_lo_u32 v5, s2, v2 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GFX6-NEXT: v_mul_lo_u32 v6, v2, v4 -; GFX6-NEXT: v_mul_hi_u32 v7, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v8, v2, v4 -; GFX6-NEXT: v_mul_hi_u32 v9, v3, v4 -; GFX6-NEXT: v_mul_lo_u32 v4, v3, v4 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GFX6-NEXT: v_mul_lo_u32 v8, v3, v5 -; GFX6-NEXT: v_mul_hi_u32 v5, v3, v5 -; GFX6-NEXT: v_xor_b32_e32 v1, s1, v1 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc -; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s2, v3 -; GFX6-NEXT: v_mul_hi_u32 v5, s2, v2 -; GFX6-NEXT: v_mul_lo_u32 v6, s3, v2 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GFX6-NEXT: v_mul_lo_u32 v5, s2, v2 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GFX6-NEXT: v_mul_lo_u32 v8, v2, v4 -; GFX6-NEXT: v_mul_hi_u32 v9, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v10, v2, v4 -; GFX6-NEXT: v_mul_hi_u32 v7, v3, v5 -; GFX6-NEXT: v_mul_lo_u32 v5, v3, v5 -; GFX6-NEXT: v_mul_hi_u32 v6, v3, v4 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, v3, v4 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: s_ashr_i32 s2, s11, 31 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc -; GFX6-NEXT: s_add_u32 s10, s10, s2 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: s_mov_b32 s3, s2 -; GFX6-NEXT: s_addc_u32 s11, s11, s2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GFX6-NEXT: s_xor_b64 s[10:11], s[10:11], s[2:3] -; GFX6-NEXT: v_mul_lo_u32 v4, s10, v3 -; GFX6-NEXT: v_mul_hi_u32 v5, s10, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, s10, v3 -; GFX6-NEXT: v_mul_hi_u32 v8, s11, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, s11, v3 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GFX6-NEXT: v_mul_lo_u32 v7, s11, v2 -; GFX6-NEXT: v_mul_hi_u32 v2, s11, v2 -; GFX6-NEXT: v_mov_b32_e32 v6, s1 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s12, v3 -; GFX6-NEXT: v_mul_hi_u32 v5, s12, v2 -; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 -; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc -; GFX6-NEXT: v_mul_lo_u32 v6, s13, v2 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GFX6-NEXT: v_mul_lo_u32 v5, s12, v2 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v6, v4 -; GFX6-NEXT: v_sub_i32_e32 v6, vcc, s11, v4 -; GFX6-NEXT: v_mov_b32_e32 v7, s13 -; GFX6-NEXT: v_sub_i32_e32 v5, vcc, s10, v5 -; GFX6-NEXT: v_subb_u32_e64 v6, s[0:1], v6, v7, vcc -; GFX6-NEXT: v_subrev_i32_e64 v7, s[0:1], s12, v5 -; GFX6-NEXT: v_subbrev_u32_e64 v6, s[0:1], 0, v6, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s13, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s12, v7 -; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[0:1] -; GFX6-NEXT: v_cmp_eq_u32_e64 s[0:1], s13, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v6, v8, v7, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v7, s[0:1], 1, v2 -; GFX6-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v3, s[0:1] -; GFX6-NEXT: v_add_i32_e64 v9, s[0:1], 2, v2 -; GFX6-NEXT: v_addc_u32_e64 v10, s[0:1], 0, v3, s[0:1] -; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v6, v7, v9, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v7, v8, v10, s[0:1] -; GFX6-NEXT: v_mov_b32_e32 v8, s11 -; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v8, v4, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s13, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s12, v5 -; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s13, v4 -; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v5, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v6, vcc -; GFX6-NEXT: s_xor_b64 s[0:1], s[2:3], s[8:9] -; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc -; GFX6-NEXT: v_xor_b32_e32 v2, s0, v2 -; GFX6-NEXT: v_xor_b32_e32 v3, s1, v3 -; GFX6-NEXT: v_mov_b32_e32 v4, s1 -; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v2 -; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc -; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GFX6-NEXT: s_add_u32 s16, s18, s16 +; GFX6-NEXT: s_addc_u32 s17, 0, s17 +; GFX6-NEXT: s_mul_i32 s15, s9, s15 +; GFX6-NEXT: v_readfirstlane_b32 s18, v1 +; GFX6-NEXT: s_add_u32 s15, s16, s15 +; GFX6-NEXT: s_addc_u32 s15, s17, s18 +; GFX6-NEXT: v_readfirstlane_b32 s16, v0 +; GFX6-NEXT: s_addc_u32 s16, s16, 0 +; GFX6-NEXT: s_mul_i32 s14, s9, s14 +; GFX6-NEXT: s_add_u32 s17, s15, s14 +; GFX6-NEXT: v_mov_b32_e32 v0, s17 +; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0 +; GFX6-NEXT: s_addc_u32 s16, 0, s16 +; GFX6-NEXT: s_mul_i32 s14, s6, s16 +; GFX6-NEXT: v_readfirstlane_b32 s15, v0 +; GFX6-NEXT: s_add_i32 s14, s15, s14 +; GFX6-NEXT: s_mul_i32 s15, s7, s17 +; GFX6-NEXT: s_add_i32 s18, s14, s15 +; GFX6-NEXT: s_sub_i32 s19, s9, s18 +; GFX6-NEXT: s_mul_i32 s14, s6, s17 +; GFX6-NEXT: s_sub_i32 s8, s8, s14 +; GFX6-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX6-NEXT: s_or_b32 s20, s14, s15 +; GFX6-NEXT: s_cmp_lg_u32 s20, 0 +; GFX6-NEXT: s_subb_u32 s19, s19, s7 +; GFX6-NEXT: s_sub_i32 s21, s8, s6 +; GFX6-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX6-NEXT: s_or_b32 s14, s14, s15 +; GFX6-NEXT: s_cmp_lg_u32 s14, 0 +; GFX6-NEXT: s_subb_u32 s14, s19, 0 +; GFX6-NEXT: s_cmp_ge_u32 s14, s7 +; GFX6-NEXT: s_cselect_b32 s15, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s21, s6 +; GFX6-NEXT: s_cselect_b32 s19, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s14, s7 +; GFX6-NEXT: s_cselect_b32 s14, s19, s15 +; GFX6-NEXT: s_add_u32 s15, s17, 1 +; GFX6-NEXT: s_addc_u32 s19, s16, 0 +; GFX6-NEXT: s_add_u32 s21, s17, 2 +; GFX6-NEXT: s_addc_u32 s22, s16, 0 +; GFX6-NEXT: s_cmp_lg_u32 s14, 0 +; GFX6-NEXT: s_cselect_b32 s14, s21, s15 +; GFX6-NEXT: s_cselect_b32 s15, s22, s19 +; GFX6-NEXT: s_cmp_lg_u32 s20, 0 +; GFX6-NEXT: s_subb_u32 s9, s9, s18 +; GFX6-NEXT: s_cmp_ge_u32 s9, s7 +; GFX6-NEXT: s_cselect_b32 s18, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s8, s6 +; GFX6-NEXT: s_cselect_b32 s6, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s9, s7 +; GFX6-NEXT: s_cselect_b32 s6, s6, s18 +; GFX6-NEXT: s_cmp_lg_u32 s6, 0 +; GFX6-NEXT: s_cselect_b32 s7, s15, s16 +; GFX6-NEXT: s_cselect_b32 s6, s14, s17 +; GFX6-NEXT: s_xor_b64 s[2:3], s[12:13], s[2:3] +; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3] +; GFX6-NEXT: s_sub_u32 s14, s6, s2 +; GFX6-NEXT: s_subb_u32 s15, s7, s3 +; GFX6-NEXT: s_ashr_i32 s6, s1, 31 +; GFX6-NEXT: s_add_u32 s0, s0, s6 +; GFX6-NEXT: s_mov_b32 s7, s6 +; GFX6-NEXT: s_addc_u32 s1, s1, s6 +; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[6:7] +; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9 +; GFX6-NEXT: s_sub_u32 s12, 0, s8 +; GFX6-NEXT: s_subb_u32 s13, 0, s9 +; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GFX6-NEXT: v_rcp_f32_e32 v0, v0 +; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GFX6-NEXT: v_trunc_f32_e32 v1, v1 +; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX6-NEXT: v_mul_hi_u32 v2, s12, v0 +; GFX6-NEXT: v_readfirstlane_b32 s16, v1 +; GFX6-NEXT: v_readfirstlane_b32 s2, v0 +; GFX6-NEXT: s_mul_i32 s1, s12, s16 +; GFX6-NEXT: v_readfirstlane_b32 s3, v2 +; GFX6-NEXT: s_mul_i32 s0, s13, s2 +; GFX6-NEXT: s_add_i32 s1, s3, s1 +; GFX6-NEXT: s_add_i32 s3, s1, s0 +; GFX6-NEXT: s_mul_i32 s17, s12, s2 +; GFX6-NEXT: v_mul_hi_u32 v2, v0, s3 +; GFX6-NEXT: v_mul_hi_u32 v0, v0, s17 +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; GFX6-NEXT: s_mul_i32 s4, s2, s3 +; GFX6-NEXT: v_readfirstlane_b32 s5, v2 +; GFX6-NEXT: v_readfirstlane_b32 s18, v0 +; GFX6-NEXT: v_mul_hi_u32 v0, v1, s17 +; GFX6-NEXT: v_mul_hi_u32 v1, v1, s3 +; GFX6-NEXT: s_add_u32 s4, s18, s4 +; GFX6-NEXT: s_addc_u32 s5, 0, s5 +; GFX6-NEXT: s_mul_i32 s17, s16, s17 +; GFX6-NEXT: v_readfirstlane_b32 s18, v0 +; GFX6-NEXT: s_add_u32 s4, s4, s17 +; GFX6-NEXT: s_addc_u32 s4, s5, s18 +; GFX6-NEXT: v_readfirstlane_b32 s5, v1 +; GFX6-NEXT: s_addc_u32 s5, s5, 0 +; GFX6-NEXT: s_mul_i32 s3, s16, s3 +; GFX6-NEXT: s_add_u32 s3, s4, s3 +; GFX6-NEXT: s_addc_u32 s4, 0, s5 +; GFX6-NEXT: s_add_i32 s5, s2, s3 +; GFX6-NEXT: v_mov_b32_e32 v0, s5 +; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 +; GFX6-NEXT: v_mul_hi_u32 v0, s12, v0 +; GFX6-NEXT: s_or_b32 s2, s2, s3 +; GFX6-NEXT: s_cmp_lg_u32 s2, 0 +; GFX6-NEXT: s_addc_u32 s4, s16, s4 +; GFX6-NEXT: s_mul_i32 s2, s12, s4 +; GFX6-NEXT: v_readfirstlane_b32 s3, v0 +; GFX6-NEXT: s_add_i32 s2, s3, s2 +; GFX6-NEXT: s_mul_i32 s13, s13, s5 +; GFX6-NEXT: s_mul_i32 s3, s12, s5 +; GFX6-NEXT: s_add_i32 s2, s2, s13 +; GFX6-NEXT: v_mov_b32_e32 v2, s3 +; GFX6-NEXT: v_mov_b32_e32 v0, s2 +; GFX6-NEXT: v_mul_hi_u32 v3, s4, v2 +; GFX6-NEXT: v_mul_hi_u32 v2, s5, v2 +; GFX6-NEXT: v_mul_hi_u32 v1, s4, v0 +; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0 +; GFX6-NEXT: s_mul_i32 s13, s5, s2 +; GFX6-NEXT: v_readfirstlane_b32 s17, v2 +; GFX6-NEXT: s_add_u32 s13, s17, s13 +; GFX6-NEXT: v_readfirstlane_b32 s16, v0 +; GFX6-NEXT: s_mul_i32 s3, s4, s3 +; GFX6-NEXT: s_addc_u32 s16, 0, s16 +; GFX6-NEXT: v_readfirstlane_b32 s12, v3 +; GFX6-NEXT: s_add_u32 s3, s13, s3 +; GFX6-NEXT: s_addc_u32 s3, s16, s12 +; GFX6-NEXT: v_readfirstlane_b32 s12, v1 +; GFX6-NEXT: s_addc_u32 s12, s12, 0 +; GFX6-NEXT: s_mul_i32 s2, s4, s2 +; GFX6-NEXT: s_add_u32 s2, s3, s2 +; GFX6-NEXT: s_addc_u32 s12, 0, s12 +; GFX6-NEXT: s_add_i32 s13, s5, s2 +; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 +; GFX6-NEXT: s_or_b32 s2, s2, s3 +; GFX6-NEXT: s_cmp_lg_u32 s2, 0 +; GFX6-NEXT: s_addc_u32 s12, s4, s12 +; GFX6-NEXT: s_ashr_i32 s4, s11, 31 +; GFX6-NEXT: s_add_u32 s2, s10, s4 +; GFX6-NEXT: s_mov_b32 s5, s4 +; GFX6-NEXT: s_addc_u32 s3, s11, s4 +; GFX6-NEXT: s_xor_b64 s[10:11], s[2:3], s[4:5] +; GFX6-NEXT: v_mov_b32_e32 v0, s12 +; GFX6-NEXT: v_mul_hi_u32 v1, s10, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, s13 +; GFX6-NEXT: v_mul_hi_u32 v3, s10, v2 +; GFX6-NEXT: s_mul_i32 s2, s10, s12 +; GFX6-NEXT: v_readfirstlane_b32 s16, v1 +; GFX6-NEXT: v_mul_hi_u32 v1, s11, v2 +; GFX6-NEXT: v_readfirstlane_b32 s17, v3 +; GFX6-NEXT: v_mul_hi_u32 v0, s11, v0 +; GFX6-NEXT: s_add_u32 s2, s17, s2 +; GFX6-NEXT: s_addc_u32 s16, 0, s16 +; GFX6-NEXT: s_mul_i32 s13, s11, s13 +; GFX6-NEXT: v_readfirstlane_b32 s17, v1 +; GFX6-NEXT: s_add_u32 s2, s2, s13 +; GFX6-NEXT: s_addc_u32 s2, s16, s17 +; GFX6-NEXT: v_readfirstlane_b32 s13, v0 +; GFX6-NEXT: s_addc_u32 s13, s13, 0 +; GFX6-NEXT: s_mul_i32 s12, s11, s12 +; GFX6-NEXT: s_add_u32 s16, s2, s12 +; GFX6-NEXT: v_mov_b32_e32 v0, s16 +; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0 +; GFX6-NEXT: s_addc_u32 s17, 0, s13 +; GFX6-NEXT: s_mul_i32 s12, s8, s17 +; GFX6-NEXT: s_mov_b32 s3, 0xf000 +; GFX6-NEXT: v_readfirstlane_b32 s13, v0 +; GFX6-NEXT: s_add_i32 s12, s13, s12 +; GFX6-NEXT: s_mul_i32 s13, s9, s16 +; GFX6-NEXT: s_add_i32 s18, s12, s13 +; GFX6-NEXT: s_sub_i32 s19, s11, s18 +; GFX6-NEXT: s_mul_i32 s12, s8, s16 +; GFX6-NEXT: s_sub_i32 s10, s10, s12 +; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_or_b32 s20, s12, s13 +; GFX6-NEXT: s_cmp_lg_u32 s20, 0 +; GFX6-NEXT: s_subb_u32 s19, s19, s9 +; GFX6-NEXT: s_sub_i32 s21, s10, s8 +; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_or_b32 s12, s12, s13 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_subb_u32 s12, s19, 0 +; GFX6-NEXT: s_cmp_ge_u32 s12, s9 +; GFX6-NEXT: s_cselect_b32 s13, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s21, s8 +; GFX6-NEXT: s_cselect_b32 s19, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s12, s9 +; GFX6-NEXT: s_cselect_b32 s12, s19, s13 +; GFX6-NEXT: s_add_u32 s13, s16, 1 +; GFX6-NEXT: s_addc_u32 s19, s17, 0 +; GFX6-NEXT: s_add_u32 s21, s16, 2 +; GFX6-NEXT: s_addc_u32 s22, s17, 0 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_cselect_b32 s12, s21, s13 +; GFX6-NEXT: s_cselect_b32 s13, s22, s19 +; GFX6-NEXT: s_cmp_lg_u32 s20, 0 +; GFX6-NEXT: s_subb_u32 s11, s11, s18 +; GFX6-NEXT: s_cmp_ge_u32 s11, s9 +; GFX6-NEXT: s_cselect_b32 s18, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s10, s8 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s11, s9 +; GFX6-NEXT: s_cselect_b32 s8, s8, s18 +; GFX6-NEXT: s_cmp_lg_u32 s8, 0 +; GFX6-NEXT: s_cselect_b32 s9, s13, s17 +; GFX6-NEXT: s_cselect_b32 s8, s12, s16 +; GFX6-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] +; GFX6-NEXT: s_xor_b64 s[6:7], s[8:9], s[4:5] +; GFX6-NEXT: s_sub_u32 s4, s6, s4 +; GFX6-NEXT: s_subb_u32 s5, s7, s5 +; GFX6-NEXT: s_mov_b32 s2, -1 +; GFX6-NEXT: v_mov_b32_e32 v0, s14 +; GFX6-NEXT: v_mov_b32_e32 v1, s15 +; GFX6-NEXT: v_mov_b32_e32 v2, s4 +; GFX6-NEXT: v_mov_b32_e32 v3, s5 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX6-NEXT: s_endpgm ; ; GFX9-LABEL: sdiv_v2i64_pow2_shl_denom: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34 -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s12 -; GFX9-NEXT: s_lshl_b64 s[6:7], 0x1000, s14 -; GFX9-NEXT: s_ashr_i32 s12, s1, 31 -; GFX9-NEXT: s_add_u32 s0, s0, s12 -; GFX9-NEXT: s_mov_b32 s13, s12 -; GFX9-NEXT: s_addc_u32 s1, s1, s12 -; GFX9-NEXT: s_xor_b64 s[14:15], s[0:1], s[12:13] -; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s14 -; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s15 -; GFX9-NEXT: s_sub_u32 s0, 0, s14 -; GFX9-NEXT: s_subb_u32 s1, 0, s15 +; GFX9-NEXT: s_lshl_b64 s[6:7], 0x1000, s12 +; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s14 +; GFX9-NEXT: s_ashr_i32 s2, s7, 31 +; GFX9-NEXT: s_add_u32 s6, s6, s2 +; GFX9-NEXT: s_mov_b32 s3, s2 +; GFX9-NEXT: s_addc_u32 s7, s7, s2 +; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3] +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GFX9-NEXT: s_sub_u32 s14, 0, s6 +; GFX9-NEXT: s_subb_u32 s15, 0, s7 ; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -8554,270 +8646,255 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s16, v1 +; GFX9-NEXT: v_readfirstlane_b32 s12, v0 +; GFX9-NEXT: s_mul_i32 s13, s14, s16 +; GFX9-NEXT: s_mul_hi_u32 s18, s14, s12 +; GFX9-NEXT: s_mul_i32 s17, s15, s12 +; GFX9-NEXT: s_add_i32 s13, s18, s13 +; GFX9-NEXT: s_mul_i32 s19, s14, s12 +; GFX9-NEXT: s_add_i32 s13, s13, s17 +; GFX9-NEXT: s_mul_hi_u32 s18, s12, s19 +; GFX9-NEXT: s_mul_i32 s20, s12, s13 +; GFX9-NEXT: s_mul_hi_u32 s17, s12, s13 +; GFX9-NEXT: s_add_u32 s18, s18, s20 +; GFX9-NEXT: s_addc_u32 s17, 0, s17 +; GFX9-NEXT: s_mul_hi_u32 s20, s16, s19 +; GFX9-NEXT: s_mul_i32 s19, s16, s19 +; GFX9-NEXT: s_add_u32 s18, s18, s19 +; GFX9-NEXT: s_mul_hi_u32 s21, s16, s13 +; GFX9-NEXT: s_addc_u32 s17, s17, s20 +; GFX9-NEXT: s_addc_u32 s18, s21, 0 +; GFX9-NEXT: s_mul_i32 s13, s16, s13 +; GFX9-NEXT: s_add_u32 s13, s17, s13 +; GFX9-NEXT: s_addc_u32 s17, 0, s18 +; GFX9-NEXT: s_add_i32 s18, s12, s13 +; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GFX9-NEXT: s_addc_u32 s16, s16, s17 +; GFX9-NEXT: s_mul_i32 s12, s14, s16 +; GFX9-NEXT: s_mul_hi_u32 s13, s14, s18 +; GFX9-NEXT: s_add_i32 s12, s13, s12 +; GFX9-NEXT: s_mul_i32 s15, s15, s18 +; GFX9-NEXT: s_add_i32 s12, s12, s15 +; GFX9-NEXT: s_mul_i32 s14, s14, s18 +; GFX9-NEXT: s_mul_hi_u32 s15, s16, s14 +; GFX9-NEXT: s_mul_i32 s17, s16, s14 +; GFX9-NEXT: s_mul_i32 s20, s18, s12 +; GFX9-NEXT: s_mul_hi_u32 s14, s18, s14 +; GFX9-NEXT: s_mul_hi_u32 s19, s18, s12 +; GFX9-NEXT: s_add_u32 s14, s14, s20 +; GFX9-NEXT: s_addc_u32 s19, 0, s19 +; GFX9-NEXT: s_add_u32 s14, s14, s17 +; GFX9-NEXT: s_mul_hi_u32 s13, s16, s12 +; GFX9-NEXT: s_addc_u32 s14, s19, s15 +; GFX9-NEXT: s_addc_u32 s13, s13, 0 +; GFX9-NEXT: s_mul_i32 s12, s16, s12 +; GFX9-NEXT: s_add_u32 s12, s14, s12 +; GFX9-NEXT: s_addc_u32 s14, 0, s13 +; GFX9-NEXT: s_add_i32 s18, s18, s12 +; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GFX9-NEXT: s_addc_u32 s14, s16, s14 +; GFX9-NEXT: s_ashr_i32 s12, s9, 31 +; GFX9-NEXT: s_add_u32 s8, s8, s12 +; GFX9-NEXT: s_mov_b32 s13, s12 +; GFX9-NEXT: s_addc_u32 s9, s9, s12 +; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] +; GFX9-NEXT: s_mul_i32 s16, s8, s14 +; GFX9-NEXT: s_mul_hi_u32 s17, s8, s18 +; GFX9-NEXT: s_mul_hi_u32 s15, s8, s14 +; GFX9-NEXT: s_add_u32 s16, s17, s16 +; GFX9-NEXT: s_addc_u32 s15, 0, s15 +; GFX9-NEXT: s_mul_hi_u32 s19, s9, s18 +; GFX9-NEXT: s_mul_i32 s18, s9, s18 +; GFX9-NEXT: s_add_u32 s16, s16, s18 +; GFX9-NEXT: s_mul_hi_u32 s17, s9, s14 +; GFX9-NEXT: s_addc_u32 s15, s15, s19 +; GFX9-NEXT: s_addc_u32 s16, s17, 0 +; GFX9-NEXT: s_mul_i32 s14, s9, s14 +; GFX9-NEXT: s_add_u32 s18, s15, s14 +; GFX9-NEXT: s_addc_u32 s19, 0, s16 +; GFX9-NEXT: s_mul_i32 s14, s6, s19 +; GFX9-NEXT: s_mul_hi_u32 s15, s6, s18 +; GFX9-NEXT: s_add_i32 s14, s15, s14 +; GFX9-NEXT: s_mul_i32 s15, s7, s18 +; GFX9-NEXT: s_add_i32 s20, s14, s15 +; GFX9-NEXT: s_sub_i32 s16, s9, s20 +; GFX9-NEXT: s_mul_i32 s14, s6, s18 +; GFX9-NEXT: s_sub_i32 s8, s8, s14 +; GFX9-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 +; GFX9-NEXT: s_subb_u32 s21, s16, s7 +; GFX9-NEXT: s_sub_i32 s22, s8, s6 +; GFX9-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GFX9-NEXT: s_subb_u32 s16, s21, 0 +; GFX9-NEXT: s_cmp_ge_u32 s16, s7 +; GFX9-NEXT: s_cselect_b32 s17, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s22, s6 +; GFX9-NEXT: s_cselect_b32 s21, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s16, s7 +; GFX9-NEXT: s_cselect_b32 s16, s21, s17 +; GFX9-NEXT: s_add_u32 s17, s18, 1 +; GFX9-NEXT: s_addc_u32 s21, s19, 0 +; GFX9-NEXT: s_add_u32 s22, s18, 2 +; GFX9-NEXT: s_addc_u32 s23, s19, 0 +; GFX9-NEXT: s_cmp_lg_u32 s16, 0 +; GFX9-NEXT: s_cselect_b32 s16, s22, s17 +; GFX9-NEXT: s_cselect_b32 s17, s23, s21 +; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 +; GFX9-NEXT: s_subb_u32 s9, s9, s20 +; GFX9-NEXT: s_cmp_ge_u32 s9, s7 +; GFX9-NEXT: s_cselect_b32 s14, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s8, s6 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s9, s7 +; GFX9-NEXT: s_cselect_b32 s6, s6, s14 +; GFX9-NEXT: s_cmp_lg_u32 s6, 0 +; GFX9-NEXT: s_cselect_b32 s7, s17, s19 +; GFX9-NEXT: s_cselect_b32 s6, s16, s18 +; GFX9-NEXT: s_xor_b64 s[2:3], s[12:13], s[2:3] +; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[2:3] +; GFX9-NEXT: s_sub_u32 s14, s6, s2 +; GFX9-NEXT: s_subb_u32 s15, s7, s3 +; GFX9-NEXT: s_ashr_i32 s2, s1, 31 +; GFX9-NEXT: s_add_u32 s0, s0, s2 +; GFX9-NEXT: s_mov_b32 s3, s2 +; GFX9-NEXT: s_addc_u32 s1, s1, s2 +; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[2:3] +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-NEXT: s_sub_u32 s8, 0, s6 +; GFX9-NEXT: s_subb_u32 s9, 0, s7 +; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GFX9-NEXT: v_rcp_f32_e32 v1, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 +; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1 +; GFX9-NEXT: v_trunc_f32_e32 v2, v2 +; GFX9-NEXT: v_mac_f32_e32 v1, 0xcf800000, v2 +; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 -; GFX9-NEXT: v_readfirstlane_b32 s5, v0 -; GFX9-NEXT: s_mul_i32 s16, s0, s4 -; GFX9-NEXT: s_mul_hi_u32 s18, s0, s5 -; GFX9-NEXT: s_mul_i32 s17, s1, s5 -; GFX9-NEXT: s_add_i32 s16, s18, s16 -; GFX9-NEXT: s_mul_i32 s19, s0, s5 -; GFX9-NEXT: s_add_i32 s16, s16, s17 -; GFX9-NEXT: s_mul_hi_u32 s17, s5, s16 -; GFX9-NEXT: s_mul_i32 s18, s5, s16 -; GFX9-NEXT: s_mul_hi_u32 s5, s5, s19 -; GFX9-NEXT: s_add_u32 s5, s5, s18 +; GFX9-NEXT: v_readfirstlane_b32 s13, v2 +; GFX9-NEXT: s_mul_hi_u32 s12, s8, s4 +; GFX9-NEXT: s_mul_i32 s16, s8, s13 +; GFX9-NEXT: s_mul_i32 s5, s9, s4 +; GFX9-NEXT: s_add_i32 s12, s12, s16 +; GFX9-NEXT: s_add_i32 s12, s12, s5 +; GFX9-NEXT: s_mul_i32 s17, s8, s4 +; GFX9-NEXT: s_mul_i32 s16, s4, s12 +; GFX9-NEXT: s_mul_hi_u32 s18, s4, s17 +; GFX9-NEXT: s_mul_hi_u32 s5, s4, s12 +; GFX9-NEXT: s_add_u32 s16, s18, s16 +; GFX9-NEXT: s_addc_u32 s5, 0, s5 +; GFX9-NEXT: s_mul_hi_u32 s19, s13, s17 +; GFX9-NEXT: s_mul_i32 s17, s13, s17 +; GFX9-NEXT: s_add_u32 s16, s16, s17 +; GFX9-NEXT: s_mul_hi_u32 s18, s13, s12 +; GFX9-NEXT: s_addc_u32 s5, s5, s19 +; GFX9-NEXT: s_addc_u32 s16, s18, 0 +; GFX9-NEXT: s_mul_i32 s12, s13, s12 +; GFX9-NEXT: s_add_u32 s5, s5, s12 +; GFX9-NEXT: s_addc_u32 s12, 0, s16 +; GFX9-NEXT: s_add_i32 s16, s4, s5 +; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-NEXT: s_addc_u32 s12, s13, s12 +; GFX9-NEXT: s_mul_i32 s4, s8, s12 +; GFX9-NEXT: s_mul_hi_u32 s5, s8, s16 +; GFX9-NEXT: s_add_i32 s4, s5, s4 +; GFX9-NEXT: s_mul_i32 s9, s9, s16 +; GFX9-NEXT: s_add_i32 s4, s4, s9 +; GFX9-NEXT: s_mul_i32 s8, s8, s16 +; GFX9-NEXT: s_mul_hi_u32 s9, s12, s8 +; GFX9-NEXT: s_mul_i32 s13, s12, s8 +; GFX9-NEXT: s_mul_i32 s18, s16, s4 +; GFX9-NEXT: s_mul_hi_u32 s8, s16, s8 +; GFX9-NEXT: s_mul_hi_u32 s17, s16, s4 +; GFX9-NEXT: s_add_u32 s8, s8, s18 ; GFX9-NEXT: s_addc_u32 s17, 0, s17 -; GFX9-NEXT: s_mul_hi_u32 s20, s4, s19 -; GFX9-NEXT: s_mul_i32 s19, s4, s19 -; GFX9-NEXT: s_add_u32 s5, s5, s19 -; GFX9-NEXT: s_mul_hi_u32 s18, s4, s16 -; GFX9-NEXT: s_addc_u32 s5, s17, s20 -; GFX9-NEXT: s_addc_u32 s17, s18, 0 -; GFX9-NEXT: s_mul_i32 s16, s4, s16 -; GFX9-NEXT: s_add_u32 s5, s5, s16 -; GFX9-NEXT: s_addc_u32 s16, 0, s17 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s5, v0 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s4, s4, s16 -; GFX9-NEXT: v_readfirstlane_b32 s16, v0 -; GFX9-NEXT: s_mul_i32 s5, s0, s4 -; GFX9-NEXT: s_mul_hi_u32 s17, s0, s16 -; GFX9-NEXT: s_add_i32 s5, s17, s5 -; GFX9-NEXT: s_mul_i32 s1, s1, s16 -; GFX9-NEXT: s_add_i32 s5, s5, s1 -; GFX9-NEXT: s_mul_i32 s0, s0, s16 -; GFX9-NEXT: s_mul_hi_u32 s17, s4, s0 -; GFX9-NEXT: s_mul_i32 s18, s4, s0 -; GFX9-NEXT: s_mul_i32 s20, s16, s5 -; GFX9-NEXT: s_mul_hi_u32 s0, s16, s0 -; GFX9-NEXT: s_mul_hi_u32 s19, s16, s5 -; GFX9-NEXT: s_add_u32 s0, s0, s20 -; GFX9-NEXT: s_addc_u32 s16, 0, s19 -; GFX9-NEXT: s_add_u32 s0, s0, s18 -; GFX9-NEXT: s_mul_hi_u32 s1, s4, s5 -; GFX9-NEXT: s_addc_u32 s0, s16, s17 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 -; GFX9-NEXT: s_mul_i32 s5, s4, s5 -; GFX9-NEXT: s_add_u32 s0, s0, s5 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s16, s4, s1 -; GFX9-NEXT: s_ashr_i32 s4, s9, 31 -; GFX9-NEXT: s_add_u32 s0, s8, s4 +; GFX9-NEXT: s_add_u32 s8, s8, s13 +; GFX9-NEXT: s_mul_hi_u32 s5, s12, s4 +; GFX9-NEXT: s_addc_u32 s8, s17, s9 +; GFX9-NEXT: s_addc_u32 s5, s5, 0 +; GFX9-NEXT: s_mul_i32 s4, s12, s4 +; GFX9-NEXT: s_add_u32 s4, s8, s4 +; GFX9-NEXT: s_addc_u32 s8, 0, s5 +; GFX9-NEXT: s_add_i32 s16, s16, s4 +; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-NEXT: s_addc_u32 s12, s12, s8 +; GFX9-NEXT: s_ashr_i32 s4, s11, 31 +; GFX9-NEXT: s_add_u32 s8, s10, s4 ; GFX9-NEXT: s_mov_b32 s5, s4 -; GFX9-NEXT: s_addc_u32 s1, s9, s4 -; GFX9-NEXT: s_xor_b64 s[8:9], s[0:1], s[4:5] -; GFX9-NEXT: v_readfirstlane_b32 s17, v0 -; GFX9-NEXT: s_mul_i32 s1, s8, s16 -; GFX9-NEXT: s_mul_hi_u32 s18, s8, s17 -; GFX9-NEXT: s_mul_hi_u32 s0, s8, s16 -; GFX9-NEXT: s_add_u32 s1, s18, s1 -; GFX9-NEXT: s_addc_u32 s0, 0, s0 -; GFX9-NEXT: s_mul_hi_u32 s19, s9, s17 -; GFX9-NEXT: s_mul_i32 s17, s9, s17 -; GFX9-NEXT: s_add_u32 s1, s1, s17 -; GFX9-NEXT: s_mul_hi_u32 s18, s9, s16 -; GFX9-NEXT: s_addc_u32 s0, s0, s19 -; GFX9-NEXT: s_addc_u32 s1, s18, 0 +; GFX9-NEXT: s_addc_u32 s9, s11, s4 +; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[4:5] +; GFX9-NEXT: s_mul_i32 s11, s8, s12 +; GFX9-NEXT: s_mul_hi_u32 s13, s8, s16 +; GFX9-NEXT: s_mul_hi_u32 s10, s8, s12 +; GFX9-NEXT: s_add_u32 s11, s13, s11 +; GFX9-NEXT: s_addc_u32 s10, 0, s10 +; GFX9-NEXT: s_mul_hi_u32 s17, s9, s16 ; GFX9-NEXT: s_mul_i32 s16, s9, s16 -; GFX9-NEXT: s_add_u32 s16, s0, s16 -; GFX9-NEXT: s_addc_u32 s17, 0, s1 -; GFX9-NEXT: s_mul_i32 s0, s14, s17 -; GFX9-NEXT: s_mul_hi_u32 s1, s14, s16 -; GFX9-NEXT: s_add_i32 s0, s1, s0 -; GFX9-NEXT: s_mul_i32 s1, s15, s16 -; GFX9-NEXT: s_add_i32 s18, s0, s1 -; GFX9-NEXT: s_mul_i32 s1, s14, s16 -; GFX9-NEXT: v_mov_b32_e32 v0, s1 -; GFX9-NEXT: s_sub_i32 s0, s9, s18 -; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s8, v0 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_subb_u32 s8, s0, s15 -; GFX9-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s14, v0 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s8, s8, 0 -; GFX9-NEXT: s_cmp_ge_u32 s8, s15 +; GFX9-NEXT: s_add_u32 s11, s11, s16 +; GFX9-NEXT: s_mul_hi_u32 s13, s9, s12 +; GFX9-NEXT: s_addc_u32 s10, s10, s17 +; GFX9-NEXT: s_addc_u32 s11, s13, 0 +; GFX9-NEXT: s_mul_i32 s12, s9, s12 +; GFX9-NEXT: s_add_u32 s16, s10, s12 +; GFX9-NEXT: s_addc_u32 s17, 0, s11 +; GFX9-NEXT: s_mul_i32 s10, s6, s17 +; GFX9-NEXT: s_mul_hi_u32 s11, s6, s16 +; GFX9-NEXT: s_add_i32 s10, s11, s10 +; GFX9-NEXT: s_mul_i32 s11, s7, s16 +; GFX9-NEXT: s_add_i32 s18, s10, s11 +; GFX9-NEXT: s_sub_i32 s12, s9, s18 +; GFX9-NEXT: s_mul_i32 s10, s6, s16 +; GFX9-NEXT: s_sub_i32 s8, s8, s10 +; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s19, s12, s7 +; GFX9-NEXT: s_sub_i32 s20, s8, s6 +; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GFX9-NEXT: s_subb_u32 s12, s19, 0 +; GFX9-NEXT: s_cmp_ge_u32 s12, s7 +; GFX9-NEXT: s_cselect_b32 s13, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s20, s6 ; GFX9-NEXT: s_cselect_b32 s19, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s14, v1 -; GFX9-NEXT: s_cmp_eq_u32 s8, s15 -; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v2, s19 -; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1] -; GFX9-NEXT: s_add_u32 s0, s16, 1 -; GFX9-NEXT: s_addc_u32 s8, s17, 0 -; GFX9-NEXT: s_add_u32 s1, s16, 2 +; GFX9-NEXT: s_cmp_eq_u32 s12, s7 +; GFX9-NEXT: s_cselect_b32 s12, s19, s13 +; GFX9-NEXT: s_add_u32 s13, s16, 1 ; GFX9-NEXT: s_addc_u32 s19, s17, 0 -; GFX9-NEXT: v_mov_b32_e32 v2, s0 -; GFX9-NEXT: v_mov_b32_e32 v3, s1 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v3, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v2, s8 -; GFX9-NEXT: v_mov_b32_e32 v3, s19 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; GFX9-NEXT: s_subb_u32 s0, s9, s18 -; GFX9-NEXT: s_cmp_ge_u32 s0, s15 -; GFX9-NEXT: s_cselect_b32 s1, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s14, v0 -; GFX9-NEXT: s_cmp_eq_u32 s0, s15 -; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; GFX9-NEXT: v_mov_b32_e32 v3, s1 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9-NEXT: s_xor_b64 s[0:1], s[4:5], s[12:13] -; GFX9-NEXT: s_ashr_i32 s4, s7, 31 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: s_add_u32 s6, s6, s4 -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX9-NEXT: s_mov_b32 s5, s4 -; GFX9-NEXT: s_addc_u32 s7, s7, s4 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc -; GFX9-NEXT: v_mov_b32_e32 v2, s16 -; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5] -; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc -; GFX9-NEXT: v_cvt_f32_u32_e32 v2, s6 -; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s7 -; GFX9-NEXT: v_xor_b32_e32 v1, s0, v1 -; GFX9-NEXT: v_xor_b32_e32 v5, s1, v0 -; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v1 -; GFX9-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 -; GFX9-NEXT: v_rcp_f32_e32 v2, v2 -; GFX9-NEXT: s_sub_u32 s0, 0, s6 -; GFX9-NEXT: v_mov_b32_e32 v6, s1 -; GFX9-NEXT: s_subb_u32 s1, 0, s7 -; GFX9-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 -; GFX9-NEXT: v_trunc_f32_e32 v3, v3 -; GFX9-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 -; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v5, v6, vcc -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: v_readfirstlane_b32 s13, v3 -; GFX9-NEXT: s_mul_hi_u32 s12, s0, s8 -; GFX9-NEXT: s_mul_i32 s14, s0, s13 -; GFX9-NEXT: s_mul_i32 s9, s1, s8 -; GFX9-NEXT: s_add_i32 s12, s12, s14 -; GFX9-NEXT: s_add_i32 s12, s12, s9 -; GFX9-NEXT: s_mul_i32 s15, s0, s8 -; GFX9-NEXT: s_mul_hi_u32 s9, s8, s12 -; GFX9-NEXT: s_mul_i32 s14, s8, s12 -; GFX9-NEXT: s_mul_hi_u32 s8, s8, s15 -; GFX9-NEXT: s_add_u32 s8, s8, s14 -; GFX9-NEXT: s_addc_u32 s9, 0, s9 -; GFX9-NEXT: s_mul_hi_u32 s16, s13, s15 -; GFX9-NEXT: s_mul_i32 s15, s13, s15 -; GFX9-NEXT: s_add_u32 s8, s8, s15 -; GFX9-NEXT: s_mul_hi_u32 s14, s13, s12 -; GFX9-NEXT: s_addc_u32 s8, s9, s16 -; GFX9-NEXT: s_addc_u32 s9, s14, 0 -; GFX9-NEXT: s_mul_i32 s12, s13, s12 -; GFX9-NEXT: s_add_u32 s8, s8, s12 -; GFX9-NEXT: s_addc_u32 s9, 0, s9 -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s8, v2 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s8, s13, s9 -; GFX9-NEXT: v_readfirstlane_b32 s12, v2 -; GFX9-NEXT: s_mul_i32 s9, s0, s8 -; GFX9-NEXT: s_mul_hi_u32 s13, s0, s12 -; GFX9-NEXT: s_add_i32 s9, s13, s9 -; GFX9-NEXT: s_mul_i32 s1, s1, s12 -; GFX9-NEXT: s_add_i32 s9, s9, s1 -; GFX9-NEXT: s_mul_i32 s0, s0, s12 -; GFX9-NEXT: s_mul_hi_u32 s13, s8, s0 -; GFX9-NEXT: s_mul_i32 s14, s8, s0 -; GFX9-NEXT: s_mul_i32 s16, s12, s9 -; GFX9-NEXT: s_mul_hi_u32 s0, s12, s0 -; GFX9-NEXT: s_mul_hi_u32 s15, s12, s9 -; GFX9-NEXT: s_add_u32 s0, s0, s16 -; GFX9-NEXT: s_addc_u32 s12, 0, s15 -; GFX9-NEXT: s_add_u32 s0, s0, s14 -; GFX9-NEXT: s_mul_hi_u32 s1, s8, s9 -; GFX9-NEXT: s_addc_u32 s0, s12, s13 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 -; GFX9-NEXT: s_mul_i32 s9, s8, s9 -; GFX9-NEXT: s_add_u32 s0, s0, s9 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s12, s8, s1 -; GFX9-NEXT: s_ashr_i32 s8, s11, 31 -; GFX9-NEXT: s_add_u32 s0, s10, s8 -; GFX9-NEXT: s_mov_b32 s9, s8 -; GFX9-NEXT: s_addc_u32 s1, s11, s8 -; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9] -; GFX9-NEXT: v_readfirstlane_b32 s13, v2 -; GFX9-NEXT: s_mul_i32 s1, s10, s12 -; GFX9-NEXT: s_mul_hi_u32 s14, s10, s13 -; GFX9-NEXT: s_mul_hi_u32 s0, s10, s12 -; GFX9-NEXT: s_add_u32 s1, s14, s1 -; GFX9-NEXT: s_addc_u32 s0, 0, s0 -; GFX9-NEXT: s_mul_hi_u32 s15, s11, s13 -; GFX9-NEXT: s_mul_i32 s13, s11, s13 -; GFX9-NEXT: s_add_u32 s1, s1, s13 -; GFX9-NEXT: s_mul_hi_u32 s14, s11, s12 -; GFX9-NEXT: s_addc_u32 s0, s0, s15 -; GFX9-NEXT: s_addc_u32 s1, s14, 0 -; GFX9-NEXT: s_mul_i32 s12, s11, s12 -; GFX9-NEXT: s_add_u32 s12, s0, s12 -; GFX9-NEXT: s_addc_u32 s13, 0, s1 -; GFX9-NEXT: s_mul_i32 s0, s6, s13 -; GFX9-NEXT: s_mul_hi_u32 s1, s6, s12 -; GFX9-NEXT: s_add_i32 s0, s1, s0 -; GFX9-NEXT: s_mul_i32 s1, s7, s12 -; GFX9-NEXT: s_add_i32 s14, s0, s1 -; GFX9-NEXT: s_mul_i32 s1, s6, s12 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: s_sub_i32 s0, s11, s14 -; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s10, v2 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_subb_u32 s10, s0, s7 -; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s6, v2 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s10, s10, 0 -; GFX9-NEXT: s_cmp_ge_u32 s10, s7 -; GFX9-NEXT: s_cselect_b32 s15, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v3 -; GFX9-NEXT: s_cmp_eq_u32 s10, s7 -; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v5, s15 -; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v3, s[0:1] -; GFX9-NEXT: s_add_u32 s0, s12, 1 -; GFX9-NEXT: s_addc_u32 s10, s13, 0 -; GFX9-NEXT: s_add_u32 s1, s12, 2 -; GFX9-NEXT: s_addc_u32 s15, s13, 0 -; GFX9-NEXT: v_mov_b32_e32 v5, s0 -; GFX9-NEXT: v_mov_b32_e32 v6, s1 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v5, v6, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v5, s10 -; GFX9-NEXT: v_mov_b32_e32 v6, s15 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1] -; GFX9-NEXT: s_subb_u32 s0, s11, s14 -; GFX9-NEXT: s_cmp_ge_u32 s0, s7 -; GFX9-NEXT: s_cselect_b32 s1, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v2 -; GFX9-NEXT: s_cmp_eq_u32 s0, s7 -; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GFX9-NEXT: v_mov_b32_e32 v6, s1 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc -; GFX9-NEXT: v_mov_b32_e32 v6, s13 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v5, vcc -; GFX9-NEXT: v_mov_b32_e32 v5, s12 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX9-NEXT: s_xor_b64 s[0:1], s[8:9], s[4:5] -; GFX9-NEXT: v_xor_b32_e32 v3, s0, v3 -; GFX9-NEXT: v_xor_b32_e32 v5, s1, v2 -; GFX9-NEXT: v_mov_b32_e32 v6, s1 -; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v3 -; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v5, v6, vcc -; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] +; GFX9-NEXT: s_add_u32 s20, s16, 2 +; GFX9-NEXT: s_addc_u32 s21, s17, 0 +; GFX9-NEXT: s_cmp_lg_u32 s12, 0 +; GFX9-NEXT: s_cselect_b32 s12, s20, s13 +; GFX9-NEXT: s_cselect_b32 s13, s21, s19 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s9, s9, s18 +; GFX9-NEXT: s_cmp_ge_u32 s9, s7 +; GFX9-NEXT: s_cselect_b32 s10, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s8, s6 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s9, s7 +; GFX9-NEXT: s_cselect_b32 s6, s6, s10 +; GFX9-NEXT: s_cmp_lg_u32 s6, 0 +; GFX9-NEXT: s_cselect_b32 s7, s13, s17 +; GFX9-NEXT: s_cselect_b32 s6, s12, s16 +; GFX9-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3] +; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], s[2:3] +; GFX9-NEXT: s_sub_u32 s2, s4, s2 +; GFX9-NEXT: s_subb_u32 s3, s5, s3 +; GFX9-NEXT: v_mov_b32_e32 v1, s14 +; GFX9-NEXT: v_mov_b32_e32 v2, s15 +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: v_mov_b32_e32 v4, s3 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1] ; GFX9-NEXT: s_endpgm %shl.y = shl <2 x i64> , %y %r = sdiv <2 x i64> %x, %shl.y @@ -8983,8 +9060,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-LABEL: srem_i64_pow2_shl_denom: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd -; GFX6-NEXT: s_mov_b32 s7, 0xf000 -; GFX6-NEXT: s_mov_b32 s6, -1 +; GFX6-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) ; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s0 ; GFX6-NEXT: s_ashr_i32 s2, s1, 31 @@ -8994,130 +9070,167 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[2:3] ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9 -; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 -; GFX6-NEXT: s_sub_u32 s4, 0, s8 -; GFX6-NEXT: s_subb_u32 s5, 0, s9 +; GFX6-NEXT: s_sub_u32 s10, 0, s8 +; GFX6-NEXT: s_subb_u32 s11, 0, s9 +; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0 -; GFX6-NEXT: s_waitcnt lgkmcnt(0) -; GFX6-NEXT: s_ashr_i32 s10, s3, 31 -; GFX6-NEXT: s_add_u32 s2, s2, s10 -; GFX6-NEXT: s_mov_b32 s11, s10 +; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: s_addc_u32 s3, s3, s10 -; GFX6-NEXT: s_xor_b64 s[12:13], s[2:3], s[10:11] -; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0 -; GFX6-NEXT: v_mul_lo_u32 v5, s5, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s4, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4 -; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v0, v2 -; GFX6-NEXT: v_mul_lo_u32 v6, v1, v4 -; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4 -; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, s4, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s4, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s5, v0 -; GFX6-NEXT: s_mov_b32 s5, s1 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, s4, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v8, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 -; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, s12, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s12, v0 -; GFX6-NEXT: v_mul_hi_u32 v4, s12, v1 -; GFX6-NEXT: v_mul_hi_u32 v5, s13, v1 -; GFX6-NEXT: v_mul_lo_u32 v1, s13, v1 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s13, v0 -; GFX6-NEXT: v_mul_hi_u32 v0, s13, v0 -; GFX6-NEXT: s_mov_b32 s4, s0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc -; GFX6-NEXT: v_mul_lo_u32 v1, s8, v1 -; GFX6-NEXT: v_mul_hi_u32 v2, s8, v0 -; GFX6-NEXT: v_mul_lo_u32 v3, s9, v0 -; GFX6-NEXT: v_mul_lo_u32 v0, s8, v0 -; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s13, v1 -; GFX6-NEXT: v_mov_b32_e32 v3, s9 -; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s12, v0 -; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc -; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s8, v0 -; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v5 -; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3] -; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v4 -; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] -; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v5 -; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s8, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3] -; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] -; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1] -; GFX6-NEXT: v_mov_b32_e32 v4, s13 -; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 -; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 -; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1 -; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX6-NEXT: v_xor_b32_e32 v0, s10, v0 -; GFX6-NEXT: v_xor_b32_e32 v1, s10, v1 -; GFX6-NEXT: v_mov_b32_e32 v2, s10 -; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0 -; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc -; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX6-NEXT: v_mul_hi_u32 v2, s10, v0 +; GFX6-NEXT: v_readfirstlane_b32 s12, v1 +; GFX6-NEXT: v_readfirstlane_b32 s0, v0 +; GFX6-NEXT: s_mul_i32 s1, s10, s12 +; GFX6-NEXT: v_readfirstlane_b32 s15, v2 +; GFX6-NEXT: s_mul_i32 s13, s11, s0 +; GFX6-NEXT: s_mul_i32 s14, s10, s0 +; GFX6-NEXT: s_add_i32 s1, s15, s1 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s14 +; GFX6-NEXT: s_add_i32 s1, s1, s13 +; GFX6-NEXT: v_mul_hi_u32 v0, v0, s1 +; GFX6-NEXT: v_mul_hi_u32 v4, v1, s14 +; GFX6-NEXT: v_readfirstlane_b32 s13, v3 +; GFX6-NEXT: s_mul_i32 s15, s0, s1 +; GFX6-NEXT: v_mul_hi_u32 v1, v1, s1 +; GFX6-NEXT: s_add_u32 s13, s13, s15 +; GFX6-NEXT: v_readfirstlane_b32 s15, v0 +; GFX6-NEXT: s_addc_u32 s15, 0, s15 +; GFX6-NEXT: s_mul_i32 s14, s12, s14 +; GFX6-NEXT: v_readfirstlane_b32 s16, v4 +; GFX6-NEXT: s_add_u32 s13, s13, s14 +; GFX6-NEXT: s_addc_u32 s13, s15, s16 +; GFX6-NEXT: v_readfirstlane_b32 s14, v1 +; GFX6-NEXT: s_addc_u32 s14, s14, 0 +; GFX6-NEXT: s_mul_i32 s1, s12, s1 +; GFX6-NEXT: s_add_u32 s1, s13, s1 +; GFX6-NEXT: s_addc_u32 s13, 0, s14 +; GFX6-NEXT: s_add_i32 s14, s0, s1 +; GFX6-NEXT: v_mov_b32_e32 v0, s14 +; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GFX6-NEXT: v_mul_hi_u32 v0, s10, v0 +; GFX6-NEXT: s_or_b32 s0, s0, s1 +; GFX6-NEXT: s_cmp_lg_u32 s0, 0 +; GFX6-NEXT: s_addc_u32 s12, s12, s13 +; GFX6-NEXT: s_mul_i32 s0, s10, s12 +; GFX6-NEXT: v_readfirstlane_b32 s1, v0 +; GFX6-NEXT: s_add_i32 s0, s1, s0 +; GFX6-NEXT: s_mul_i32 s11, s11, s14 +; GFX6-NEXT: s_mul_i32 s1, s10, s14 +; GFX6-NEXT: s_add_i32 s0, s0, s11 +; GFX6-NEXT: v_mov_b32_e32 v2, s1 +; GFX6-NEXT: v_mov_b32_e32 v0, s0 +; GFX6-NEXT: v_mul_hi_u32 v3, s12, v2 +; GFX6-NEXT: v_mul_hi_u32 v2, s14, v2 +; GFX6-NEXT: v_mul_hi_u32 v1, s12, v0 +; GFX6-NEXT: v_mul_hi_u32 v0, s14, v0 +; GFX6-NEXT: s_mul_i32 s11, s14, s0 +; GFX6-NEXT: v_readfirstlane_b32 s15, v2 +; GFX6-NEXT: s_add_u32 s11, s15, s11 +; GFX6-NEXT: v_readfirstlane_b32 s13, v0 +; GFX6-NEXT: s_mul_i32 s1, s12, s1 +; GFX6-NEXT: s_addc_u32 s13, 0, s13 +; GFX6-NEXT: v_readfirstlane_b32 s10, v3 +; GFX6-NEXT: s_add_u32 s1, s11, s1 +; GFX6-NEXT: s_addc_u32 s1, s13, s10 +; GFX6-NEXT: v_readfirstlane_b32 s10, v1 +; GFX6-NEXT: s_addc_u32 s10, s10, 0 +; GFX6-NEXT: s_mul_i32 s0, s12, s0 +; GFX6-NEXT: s_add_u32 s0, s1, s0 +; GFX6-NEXT: s_addc_u32 s10, 0, s10 +; GFX6-NEXT: s_add_i32 s13, s14, s0 +; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GFX6-NEXT: s_or_b32 s0, s0, s1 +; GFX6-NEXT: s_cmp_lg_u32 s0, 0 +; GFX6-NEXT: s_addc_u32 s12, s12, s10 +; GFX6-NEXT: s_ashr_i32 s10, s7, 31 +; GFX6-NEXT: s_add_u32 s0, s6, s10 +; GFX6-NEXT: s_mov_b32 s11, s10 +; GFX6-NEXT: s_addc_u32 s1, s7, s10 +; GFX6-NEXT: s_xor_b64 s[6:7], s[0:1], s[10:11] +; GFX6-NEXT: v_mov_b32_e32 v0, s12 +; GFX6-NEXT: v_mul_hi_u32 v1, s6, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, s13 +; GFX6-NEXT: v_mul_hi_u32 v3, s6, v2 +; GFX6-NEXT: s_mov_b32 s0, s4 +; GFX6-NEXT: v_readfirstlane_b32 s4, v1 +; GFX6-NEXT: v_mul_hi_u32 v1, s7, v2 +; GFX6-NEXT: s_mul_i32 s1, s6, s12 +; GFX6-NEXT: v_readfirstlane_b32 s14, v3 +; GFX6-NEXT: v_mul_hi_u32 v0, s7, v0 +; GFX6-NEXT: s_add_u32 s1, s14, s1 +; GFX6-NEXT: s_addc_u32 s4, 0, s4 +; GFX6-NEXT: s_mul_i32 s13, s7, s13 +; GFX6-NEXT: v_readfirstlane_b32 s14, v1 +; GFX6-NEXT: s_add_u32 s1, s1, s13 +; GFX6-NEXT: s_addc_u32 s1, s4, s14 +; GFX6-NEXT: v_readfirstlane_b32 s4, v0 +; GFX6-NEXT: s_addc_u32 s4, s4, 0 +; GFX6-NEXT: s_mul_i32 s12, s7, s12 +; GFX6-NEXT: s_add_u32 s12, s1, s12 +; GFX6-NEXT: v_mov_b32_e32 v0, s12 +; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0 +; GFX6-NEXT: s_addc_u32 s4, 0, s4 +; GFX6-NEXT: s_mov_b32 s1, s5 +; GFX6-NEXT: s_mul_i32 s4, s8, s4 +; GFX6-NEXT: v_readfirstlane_b32 s5, v0 +; GFX6-NEXT: s_add_i32 s4, s5, s4 +; GFX6-NEXT: s_mul_i32 s5, s9, s12 +; GFX6-NEXT: s_add_i32 s13, s4, s5 +; GFX6-NEXT: s_sub_i32 s14, s7, s13 +; GFX6-NEXT: s_mul_i32 s4, s8, s12 +; GFX6-NEXT: s_sub_i32 s6, s6, s4 +; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_or_b32 s12, s4, s5 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_subb_u32 s14, s14, s9 +; GFX6-NEXT: s_sub_i32 s15, s6, s8 +; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_or_b32 s4, s4, s5 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-NEXT: s_subb_u32 s16, s14, 0 +; GFX6-NEXT: s_cmp_ge_u32 s16, s9 +; GFX6-NEXT: s_cselect_b32 s5, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s15, s8 +; GFX6-NEXT: s_cselect_b32 s17, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s16, s9 +; GFX6-NEXT: s_cselect_b32 s17, s17, s5 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-NEXT: s_subb_u32 s14, s14, s9 +; GFX6-NEXT: s_sub_i32 s18, s15, s8 +; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_or_b32 s4, s4, s5 +; GFX6-NEXT: s_cmp_lg_u32 s4, 0 +; GFX6-NEXT: s_subb_u32 s4, s14, 0 +; GFX6-NEXT: s_cmp_lg_u32 s17, 0 +; GFX6-NEXT: s_cselect_b32 s14, s18, s15 +; GFX6-NEXT: s_cselect_b32 s4, s4, s16 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_subb_u32 s5, s7, s13 +; GFX6-NEXT: s_cmp_ge_u32 s5, s9 +; GFX6-NEXT: s_cselect_b32 s7, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s6, s8 +; GFX6-NEXT: s_cselect_b32 s8, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s5, s9 +; GFX6-NEXT: s_cselect_b32 s7, s8, s7 +; GFX6-NEXT: s_cmp_lg_u32 s7, 0 +; GFX6-NEXT: s_cselect_b32 s5, s4, s5 +; GFX6-NEXT: s_cselect_b32 s4, s14, s6 +; GFX6-NEXT: s_xor_b64 s[4:5], s[4:5], s[10:11] +; GFX6-NEXT: s_sub_u32 s4, s4, s10 +; GFX6-NEXT: s_subb_u32 s5, s5, s10 +; GFX6-NEXT: v_mov_b32_e32 v0, s4 +; GFX6-NEXT: v_mov_b32_e32 v1, s5 +; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GFX6-NEXT: s_endpgm ; ; GFX9-LABEL: srem_i64_pow2_shl_denom: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34 -; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s0 ; GFX9-NEXT: s_ashr_i32 s2, s1, 31 @@ -9127,8 +9240,9 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_xor_b64 s[6:7], s[0:1], s[2:3] ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7 -; GFX9-NEXT: s_sub_u32 s0, 0, s6 -; GFX9-NEXT: s_subb_u32 s1, 0, s7 +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: s_sub_u32 s8, 0, s6 +; GFX9-NEXT: s_subb_u32 s9, 0, s7 ; GFX9-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GFX9-NEXT: v_rcp_f32_e32 v1, v0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0 @@ -9138,127 +9252,123 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: v_madmk_f32 v1, v2, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX9-NEXT: v_readfirstlane_b32 s2, v2 -; GFX9-NEXT: v_readfirstlane_b32 s3, v1 -; GFX9-NEXT: s_mul_i32 s4, s0, s2 -; GFX9-NEXT: s_mul_hi_u32 s12, s0, s3 -; GFX9-NEXT: s_mul_i32 s5, s1, s3 -; GFX9-NEXT: s_add_i32 s4, s12, s4 -; GFX9-NEXT: s_mul_i32 s13, s0, s3 -; GFX9-NEXT: s_add_i32 s4, s4, s5 -; GFX9-NEXT: s_mul_hi_u32 s12, s3, s13 -; GFX9-NEXT: s_mul_hi_u32 s5, s3, s4 -; GFX9-NEXT: s_mul_i32 s3, s3, s4 -; GFX9-NEXT: s_add_u32 s3, s12, s3 -; GFX9-NEXT: s_addc_u32 s5, 0, s5 -; GFX9-NEXT: s_mul_hi_u32 s14, s2, s13 -; GFX9-NEXT: s_mul_i32 s13, s2, s13 -; GFX9-NEXT: s_add_u32 s3, s3, s13 -; GFX9-NEXT: s_mul_hi_u32 s12, s2, s4 -; GFX9-NEXT: s_addc_u32 s3, s5, s14 -; GFX9-NEXT: s_addc_u32 s5, s12, 0 -; GFX9-NEXT: s_mul_i32 s4, s2, s4 -; GFX9-NEXT: s_add_u32 s3, s3, s4 -; GFX9-NEXT: s_addc_u32 s4, 0, s5 -; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s3, v1 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s2, s2, s4 +; GFX9-NEXT: v_readfirstlane_b32 s10, v2 ; GFX9-NEXT: v_readfirstlane_b32 s4, v1 -; GFX9-NEXT: s_mul_i32 s3, s0, s2 -; GFX9-NEXT: s_mul_hi_u32 s5, s0, s4 -; GFX9-NEXT: s_add_i32 s3, s5, s3 -; GFX9-NEXT: s_mul_i32 s1, s1, s4 -; GFX9-NEXT: s_add_i32 s3, s3, s1 -; GFX9-NEXT: s_mul_i32 s0, s0, s4 -; GFX9-NEXT: s_mul_hi_u32 s5, s2, s0 -; GFX9-NEXT: s_mul_i32 s12, s2, s0 -; GFX9-NEXT: s_mul_i32 s14, s4, s3 -; GFX9-NEXT: s_mul_hi_u32 s0, s4, s0 -; GFX9-NEXT: s_mul_hi_u32 s13, s4, s3 -; GFX9-NEXT: s_add_u32 s0, s0, s14 -; GFX9-NEXT: s_addc_u32 s4, 0, s13 -; GFX9-NEXT: s_add_u32 s0, s0, s12 -; GFX9-NEXT: s_mul_hi_u32 s1, s2, s3 -; GFX9-NEXT: s_addc_u32 s0, s4, s5 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 -; GFX9-NEXT: s_mul_i32 s3, s2, s3 -; GFX9-NEXT: s_add_u32 s0, s0, s3 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, s0, v1 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s2, s2, s1 -; GFX9-NEXT: s_ashr_i32 s4, s11, 31 -; GFX9-NEXT: s_add_u32 s0, s10, s4 +; GFX9-NEXT: s_mul_i32 s5, s8, s10 +; GFX9-NEXT: s_mul_hi_u32 s12, s8, s4 +; GFX9-NEXT: s_mul_i32 s11, s9, s4 +; GFX9-NEXT: s_add_i32 s5, s12, s5 +; GFX9-NEXT: s_mul_i32 s13, s8, s4 +; GFX9-NEXT: s_add_i32 s5, s5, s11 +; GFX9-NEXT: s_mul_hi_u32 s12, s4, s13 +; GFX9-NEXT: s_mul_i32 s14, s4, s5 +; GFX9-NEXT: s_mul_hi_u32 s11, s4, s5 +; GFX9-NEXT: s_add_u32 s12, s12, s14 +; GFX9-NEXT: s_addc_u32 s11, 0, s11 +; GFX9-NEXT: s_mul_hi_u32 s15, s10, s13 +; GFX9-NEXT: s_mul_i32 s13, s10, s13 +; GFX9-NEXT: s_add_u32 s12, s12, s13 +; GFX9-NEXT: s_mul_hi_u32 s14, s10, s5 +; GFX9-NEXT: s_addc_u32 s11, s11, s15 +; GFX9-NEXT: s_addc_u32 s12, s14, 0 +; GFX9-NEXT: s_mul_i32 s5, s10, s5 +; GFX9-NEXT: s_add_u32 s5, s11, s5 +; GFX9-NEXT: s_addc_u32 s11, 0, s12 +; GFX9-NEXT: s_add_i32 s12, s4, s5 +; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-NEXT: s_addc_u32 s10, s10, s11 +; GFX9-NEXT: s_mul_i32 s4, s8, s10 +; GFX9-NEXT: s_mul_hi_u32 s5, s8, s12 +; GFX9-NEXT: s_add_i32 s4, s5, s4 +; GFX9-NEXT: s_mul_i32 s9, s9, s12 +; GFX9-NEXT: s_add_i32 s4, s4, s9 +; GFX9-NEXT: s_mul_i32 s8, s8, s12 +; GFX9-NEXT: s_mul_hi_u32 s9, s10, s8 +; GFX9-NEXT: s_mul_i32 s11, s10, s8 +; GFX9-NEXT: s_mul_i32 s14, s12, s4 +; GFX9-NEXT: s_mul_hi_u32 s8, s12, s8 +; GFX9-NEXT: s_mul_hi_u32 s13, s12, s4 +; GFX9-NEXT: s_add_u32 s8, s8, s14 +; GFX9-NEXT: s_addc_u32 s13, 0, s13 +; GFX9-NEXT: s_add_u32 s8, s8, s11 +; GFX9-NEXT: s_mul_hi_u32 s5, s10, s4 +; GFX9-NEXT: s_addc_u32 s8, s13, s9 +; GFX9-NEXT: s_addc_u32 s5, s5, 0 +; GFX9-NEXT: s_mul_i32 s4, s10, s4 +; GFX9-NEXT: s_add_u32 s4, s8, s4 +; GFX9-NEXT: s_addc_u32 s8, 0, s5 +; GFX9-NEXT: s_add_i32 s12, s12, s4 +; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-NEXT: s_addc_u32 s8, s10, s8 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_ashr_i32 s4, s3, 31 +; GFX9-NEXT: s_add_u32 s2, s2, s4 ; GFX9-NEXT: s_mov_b32 s5, s4 -; GFX9-NEXT: s_addc_u32 s1, s11, s4 -; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[4:5] -; GFX9-NEXT: v_readfirstlane_b32 s3, v1 -; GFX9-NEXT: s_mul_i32 s1, s10, s2 -; GFX9-NEXT: s_mul_hi_u32 s5, s10, s3 -; GFX9-NEXT: s_mul_hi_u32 s0, s10, s2 -; GFX9-NEXT: s_add_u32 s1, s5, s1 -; GFX9-NEXT: s_addc_u32 s0, 0, s0 -; GFX9-NEXT: s_mul_hi_u32 s12, s11, s3 -; GFX9-NEXT: s_mul_i32 s3, s11, s3 -; GFX9-NEXT: s_add_u32 s1, s1, s3 -; GFX9-NEXT: s_mul_hi_u32 s5, s11, s2 -; GFX9-NEXT: s_addc_u32 s0, s0, s12 -; GFX9-NEXT: s_addc_u32 s1, s5, 0 -; GFX9-NEXT: s_mul_i32 s2, s11, s2 -; GFX9-NEXT: s_add_u32 s0, s0, s2 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: s_mul_i32 s1, s6, s1 -; GFX9-NEXT: s_mul_hi_u32 s2, s6, s0 -; GFX9-NEXT: s_add_i32 s1, s2, s1 -; GFX9-NEXT: s_mul_i32 s2, s7, s0 -; GFX9-NEXT: s_mul_i32 s0, s6, s0 -; GFX9-NEXT: s_add_i32 s5, s1, s2 -; GFX9-NEXT: v_mov_b32_e32 v1, s0 -; GFX9-NEXT: s_sub_i32 s1, s11, s5 -; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, s10, v1 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_subb_u32 s10, s1, s7 -; GFX9-NEXT: v_subrev_co_u32_e64 v2, s[0:1], s6, v1 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s12, s10, 0 -; GFX9-NEXT: s_cmp_ge_u32 s12, s7 -; GFX9-NEXT: s_cselect_b32 s13, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s6, v2 -; GFX9-NEXT: s_cmp_eq_u32 s12, s7 -; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[2:3] -; GFX9-NEXT: v_mov_b32_e32 v4, s13 -; GFX9-NEXT: s_cselect_b64 s[2:3], -1, 0 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[2:3] -; GFX9-NEXT: s_subb_u32 s2, s10, s7 -; GFX9-NEXT: v_subrev_co_u32_e64 v4, s[0:1], s6, v2 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s2, s2, 0 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v3, s12 -; GFX9-NEXT: v_mov_b32_e32 v4, s2 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1] -; GFX9-NEXT: s_subb_u32 s0, s11, s5 -; GFX9-NEXT: s_cmp_ge_u32 s0, s7 -; GFX9-NEXT: s_cselect_b32 s1, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s6, v1 -; GFX9-NEXT: s_cmp_eq_u32 s0, s7 -; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GFX9-NEXT: v_mov_b32_e32 v5, s1 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GFX9-NEXT: v_mov_b32_e32 v5, s0 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX9-NEXT: v_xor_b32_e32 v1, s4, v1 -; GFX9-NEXT: v_xor_b32_e32 v2, s4, v3 -; GFX9-NEXT: v_mov_b32_e32 v3, s4 -; GFX9-NEXT: v_subrev_co_u32_e32 v1, vcc, s4, v1 -; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v3, vcc -; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[8:9] +; GFX9-NEXT: s_addc_u32 s3, s3, s4 +; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: s_mul_i32 s10, s2, s8 +; GFX9-NEXT: s_mul_hi_u32 s11, s2, s12 +; GFX9-NEXT: s_mul_hi_u32 s9, s2, s8 +; GFX9-NEXT: s_add_u32 s10, s11, s10 +; GFX9-NEXT: s_addc_u32 s9, 0, s9 +; GFX9-NEXT: s_mul_hi_u32 s13, s3, s12 +; GFX9-NEXT: s_mul_i32 s12, s3, s12 +; GFX9-NEXT: s_add_u32 s10, s10, s12 +; GFX9-NEXT: s_mul_hi_u32 s11, s3, s8 +; GFX9-NEXT: s_addc_u32 s9, s9, s13 +; GFX9-NEXT: s_addc_u32 s10, s11, 0 +; GFX9-NEXT: s_mul_i32 s8, s3, s8 +; GFX9-NEXT: s_add_u32 s8, s9, s8 +; GFX9-NEXT: s_addc_u32 s9, 0, s10 +; GFX9-NEXT: s_mul_i32 s9, s6, s9 +; GFX9-NEXT: s_mul_hi_u32 s10, s6, s8 +; GFX9-NEXT: s_add_i32 s9, s10, s9 +; GFX9-NEXT: s_mul_i32 s10, s7, s8 +; GFX9-NEXT: s_add_i32 s12, s9, s10 +; GFX9-NEXT: s_sub_i32 s10, s3, s12 +; GFX9-NEXT: s_mul_i32 s8, s6, s8 +; GFX9-NEXT: s_sub_i32 s2, s2, s8 +; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX9-NEXT: s_subb_u32 s13, s10, s7 +; GFX9-NEXT: s_sub_i32 s14, s2, s6 +; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s15, s13, 0 +; GFX9-NEXT: s_cmp_ge_u32 s15, s7 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s14, s6 +; GFX9-NEXT: s_cselect_b32 s17, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s15, s7 +; GFX9-NEXT: s_cselect_b32 s16, s17, s16 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s13, s13, s7 +; GFX9-NEXT: s_sub_i32 s17, s14, s6 +; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s10, s13, 0 +; GFX9-NEXT: s_cmp_lg_u32 s16, 0 +; GFX9-NEXT: s_cselect_b32 s11, s17, s14 +; GFX9-NEXT: s_cselect_b32 s10, s10, s15 +; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX9-NEXT: s_subb_u32 s3, s3, s12 +; GFX9-NEXT: s_cmp_ge_u32 s3, s7 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s2, s6 +; GFX9-NEXT: s_cselect_b32 s6, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s3, s7 +; GFX9-NEXT: s_cselect_b32 s6, s6, s8 +; GFX9-NEXT: s_cmp_lg_u32 s6, 0 +; GFX9-NEXT: s_cselect_b32 s3, s10, s3 +; GFX9-NEXT: s_cselect_b32 s2, s11, s2 +; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: s_sub_u32 s2, s2, s4 +; GFX9-NEXT: s_subb_u32 s3, s3, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s2 +; GFX9-NEXT: v_mov_b32_e32 v2, s3 +; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1] ; GFX9-NEXT: s_endpgm %shl.y = shl i64 4096, %y %r = srem i64 %x, %shl.y @@ -9353,272 +9463,347 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-LABEL: srem_v2i64_pow2_shl_denom: ; GFX6: ; %bb.0: ; GFX6-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd -; GFX6-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9 -; GFX6-NEXT: s_mov_b32 s7, 0xf000 -; GFX6-NEXT: s_mov_b32 s6, -1 ; GFX6-NEXT: s_waitcnt lgkmcnt(0) -; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s12 -; GFX6-NEXT: s_lshl_b64 s[16:17], 0x1000, s14 +; GFX6-NEXT: s_lshl_b64 s[2:3], 0x1000, s12 +; GFX6-NEXT: s_lshl_b64 s[0:1], 0x1000, s14 +; GFX6-NEXT: s_ashr_i32 s6, s3, 31 +; GFX6-NEXT: s_add_u32 s2, s2, s6 +; GFX6-NEXT: s_mov_b32 s7, s6 +; GFX6-NEXT: s_addc_u32 s3, s3, s6 +; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7] +; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GFX6-NEXT: s_sub_u32 s12, 0, s2 +; GFX6-NEXT: s_subb_u32 s13, 0, s3 +; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GFX6-NEXT: v_rcp_f32_e32 v0, v0 +; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GFX6-NEXT: v_trunc_f32_e32 v1, v1 +; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 +; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX6-NEXT: v_mul_hi_u32 v2, s12, v0 +; GFX6-NEXT: v_readfirstlane_b32 s14, v1 +; GFX6-NEXT: v_readfirstlane_b32 s6, v0 +; GFX6-NEXT: s_mul_i32 s7, s12, s14 +; GFX6-NEXT: v_readfirstlane_b32 s17, v2 +; GFX6-NEXT: s_mul_i32 s15, s13, s6 +; GFX6-NEXT: s_mul_i32 s16, s12, s6 +; GFX6-NEXT: s_add_i32 s7, s17, s7 +; GFX6-NEXT: v_mul_hi_u32 v3, v0, s16 +; GFX6-NEXT: s_add_i32 s7, s7, s15 +; GFX6-NEXT: v_mul_hi_u32 v0, v0, s7 +; GFX6-NEXT: v_mul_hi_u32 v4, v1, s16 +; GFX6-NEXT: v_readfirstlane_b32 s15, v3 +; GFX6-NEXT: s_mul_i32 s18, s6, s7 +; GFX6-NEXT: v_mul_hi_u32 v1, v1, s7 +; GFX6-NEXT: s_add_u32 s15, s15, s18 +; GFX6-NEXT: v_readfirstlane_b32 s18, v0 +; GFX6-NEXT: s_mul_i32 s16, s14, s16 +; GFX6-NEXT: s_addc_u32 s18, 0, s18 +; GFX6-NEXT: v_readfirstlane_b32 s17, v4 +; GFX6-NEXT: s_add_u32 s15, s15, s16 +; GFX6-NEXT: s_addc_u32 s15, s18, s17 +; GFX6-NEXT: v_readfirstlane_b32 s16, v1 +; GFX6-NEXT: s_addc_u32 s16, s16, 0 +; GFX6-NEXT: s_mul_i32 s7, s14, s7 +; GFX6-NEXT: s_add_u32 s7, s15, s7 +; GFX6-NEXT: s_addc_u32 s15, 0, s16 +; GFX6-NEXT: s_add_i32 s16, s6, s7 +; GFX6-NEXT: v_mov_b32_e32 v0, s16 +; GFX6-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX6-NEXT: v_mul_hi_u32 v0, s12, v0 +; GFX6-NEXT: s_or_b32 s6, s6, s7 +; GFX6-NEXT: s_cmp_lg_u32 s6, 0 +; GFX6-NEXT: s_addc_u32 s14, s14, s15 +; GFX6-NEXT: s_mul_i32 s6, s12, s14 +; GFX6-NEXT: v_readfirstlane_b32 s7, v0 +; GFX6-NEXT: s_add_i32 s6, s7, s6 +; GFX6-NEXT: s_mul_i32 s13, s13, s16 +; GFX6-NEXT: s_mul_i32 s7, s12, s16 +; GFX6-NEXT: s_add_i32 s6, s6, s13 +; GFX6-NEXT: v_mov_b32_e32 v2, s7 +; GFX6-NEXT: v_mov_b32_e32 v0, s6 +; GFX6-NEXT: v_mul_hi_u32 v3, s14, v2 +; GFX6-NEXT: v_mul_hi_u32 v2, s16, v2 +; GFX6-NEXT: v_mul_hi_u32 v1, s14, v0 +; GFX6-NEXT: v_mul_hi_u32 v0, s16, v0 +; GFX6-NEXT: s_mul_i32 s13, s16, s6 +; GFX6-NEXT: v_readfirstlane_b32 s17, v2 +; GFX6-NEXT: s_add_u32 s13, s17, s13 +; GFX6-NEXT: v_readfirstlane_b32 s15, v0 +; GFX6-NEXT: s_mul_i32 s7, s14, s7 +; GFX6-NEXT: s_addc_u32 s15, 0, s15 +; GFX6-NEXT: v_readfirstlane_b32 s12, v3 +; GFX6-NEXT: s_add_u32 s7, s13, s7 +; GFX6-NEXT: s_addc_u32 s7, s15, s12 +; GFX6-NEXT: v_readfirstlane_b32 s12, v1 +; GFX6-NEXT: s_addc_u32 s12, s12, 0 +; GFX6-NEXT: s_mul_i32 s6, s14, s6 +; GFX6-NEXT: s_add_u32 s6, s7, s6 +; GFX6-NEXT: s_addc_u32 s12, 0, s12 +; GFX6-NEXT: s_add_i32 s13, s16, s6 +; GFX6-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX6-NEXT: s_or_b32 s6, s6, s7 +; GFX6-NEXT: s_cmp_lg_u32 s6, 0 +; GFX6-NEXT: s_addc_u32 s12, s14, s12 +; GFX6-NEXT: s_ashr_i32 s6, s9, 31 +; GFX6-NEXT: s_add_u32 s8, s8, s6 +; GFX6-NEXT: s_mov_b32 s7, s6 +; GFX6-NEXT: s_addc_u32 s9, s9, s6 +; GFX6-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7] +; GFX6-NEXT: v_mov_b32_e32 v0, s12 +; GFX6-NEXT: v_mul_hi_u32 v1, s8, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, s13 +; GFX6-NEXT: v_mul_hi_u32 v3, s8, v2 +; GFX6-NEXT: s_mul_i32 s14, s8, s12 +; GFX6-NEXT: v_readfirstlane_b32 s15, v1 +; GFX6-NEXT: v_mul_hi_u32 v1, s9, v2 +; GFX6-NEXT: v_readfirstlane_b32 s16, v3 +; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0 +; GFX6-NEXT: s_add_u32 s14, s16, s14 +; GFX6-NEXT: s_addc_u32 s15, 0, s15 +; GFX6-NEXT: s_mul_i32 s13, s9, s13 +; GFX6-NEXT: v_readfirstlane_b32 s16, v1 +; GFX6-NEXT: s_add_u32 s13, s14, s13 +; GFX6-NEXT: s_addc_u32 s13, s15, s16 +; GFX6-NEXT: v_readfirstlane_b32 s14, v0 +; GFX6-NEXT: s_addc_u32 s14, s14, 0 +; GFX6-NEXT: s_mul_i32 s12, s9, s12 +; GFX6-NEXT: s_add_u32 s12, s13, s12 +; GFX6-NEXT: v_mov_b32_e32 v0, s12 +; GFX6-NEXT: v_mul_hi_u32 v0, s2, v0 +; GFX6-NEXT: s_addc_u32 s13, 0, s14 +; GFX6-NEXT: s_mul_i32 s13, s2, s13 +; GFX6-NEXT: v_readfirstlane_b32 s14, v0 +; GFX6-NEXT: s_add_i32 s13, s14, s13 +; GFX6-NEXT: s_mul_i32 s14, s3, s12 +; GFX6-NEXT: s_add_i32 s14, s13, s14 +; GFX6-NEXT: s_sub_i32 s15, s9, s14 +; GFX6-NEXT: s_mul_i32 s12, s2, s12 +; GFX6-NEXT: s_sub_i32 s8, s8, s12 +; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_or_b32 s16, s12, s13 +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 +; GFX6-NEXT: s_subb_u32 s15, s15, s3 +; GFX6-NEXT: s_sub_i32 s17, s8, s2 +; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_or_b32 s12, s12, s13 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_subb_u32 s18, s15, 0 +; GFX6-NEXT: s_cmp_ge_u32 s18, s3 +; GFX6-NEXT: s_cselect_b32 s13, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s17, s2 +; GFX6-NEXT: s_cselect_b32 s19, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s18, s3 +; GFX6-NEXT: s_cselect_b32 s19, s19, s13 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_subb_u32 s15, s15, s3 +; GFX6-NEXT: s_sub_i32 s20, s17, s2 +; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_or_b32 s12, s12, s13 +; GFX6-NEXT: s_cmp_lg_u32 s12, 0 +; GFX6-NEXT: s_subb_u32 s12, s15, 0 +; GFX6-NEXT: s_cmp_lg_u32 s19, 0 +; GFX6-NEXT: s_cselect_b32 s13, s20, s17 +; GFX6-NEXT: s_cselect_b32 s12, s12, s18 +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 +; GFX6-NEXT: s_subb_u32 s9, s9, s14 +; GFX6-NEXT: s_cmp_ge_u32 s9, s3 +; GFX6-NEXT: s_cselect_b32 s14, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s8, s2 +; GFX6-NEXT: s_cselect_b32 s2, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s9, s3 +; GFX6-NEXT: s_cselect_b32 s2, s2, s14 +; GFX6-NEXT: s_cmp_lg_u32 s2, 0 +; GFX6-NEXT: s_cselect_b32 s3, s12, s9 +; GFX6-NEXT: s_cselect_b32 s2, s13, s8 +; GFX6-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7] +; GFX6-NEXT: s_sub_u32 s12, s2, s6 +; GFX6-NEXT: s_subb_u32 s13, s3, s6 ; GFX6-NEXT: s_ashr_i32 s2, s1, 31 ; GFX6-NEXT: s_add_u32 s0, s0, s2 ; GFX6-NEXT: s_mov_b32 s3, s2 ; GFX6-NEXT: s_addc_u32 s1, s1, s2 -; GFX6-NEXT: s_xor_b64 s[14:15], s[0:1], s[2:3] -; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s14 -; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s15 -; GFX6-NEXT: s_sub_u32 s0, 0, s14 -; GFX6-NEXT: s_subb_u32 s1, 0, s15 -; GFX6-NEXT: s_ashr_i32 s12, s9, 31 +; GFX6-NEXT: s_xor_b64 s[6:7], s[0:1], s[2:3] +; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GFX6-NEXT: s_sub_u32 s8, 0, s6 +; GFX6-NEXT: s_subb_u32 s9, 0, s7 ; GFX6-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX6-NEXT: v_rcp_f32_e32 v0, v0 -; GFX6-NEXT: s_mov_b32 s13, s12 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GFX6-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GFX6-NEXT: v_trunc_f32_e32 v1, v1 ; GFX6-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 -; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0 -; GFX6-NEXT: v_mul_lo_u32 v5, s1, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s0, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v3, v0, v4 -; GFX6-NEXT: v_mul_lo_u32 v5, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v6, v1, v4 -; GFX6-NEXT: v_mul_lo_u32 v4, v1, v4 -; GFX6-NEXT: v_mul_hi_u32 v8, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, s0, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s0, v0 -; GFX6-NEXT: v_mul_lo_u32 v4, s1, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, s0, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_mul_lo_u32 v6, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, v0, v3 -; GFX6-NEXT: v_mul_hi_u32 v8, v0, v2 -; GFX6-NEXT: v_mul_hi_u32 v5, v1, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, v1, v3 -; GFX6-NEXT: v_mul_hi_u32 v4, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GFX6-NEXT: v_mul_lo_u32 v2, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: s_add_u32 s0, s8, s12 -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GFX6-NEXT: s_addc_u32 s1, s9, s12 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GFX6-NEXT: s_xor_b64 s[8:9], s[0:1], s[12:13] -; GFX6-NEXT: v_mul_lo_u32 v2, s8, v1 -; GFX6-NEXT: v_mul_hi_u32 v3, s8, v0 -; GFX6-NEXT: v_mul_hi_u32 v4, s8, v1 -; GFX6-NEXT: v_mul_hi_u32 v5, s9, v1 -; GFX6-NEXT: v_mul_lo_u32 v1, s9, v1 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s9, v0 +; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX6-NEXT: v_mul_hi_u32 v2, s8, v0 +; GFX6-NEXT: v_readfirstlane_b32 s14, v1 +; GFX6-NEXT: v_readfirstlane_b32 s2, v0 +; GFX6-NEXT: s_mul_i32 s1, s8, s14 +; GFX6-NEXT: v_readfirstlane_b32 s3, v2 +; GFX6-NEXT: s_mul_i32 s0, s9, s2 +; GFX6-NEXT: s_add_i32 s1, s3, s1 +; GFX6-NEXT: s_add_i32 s3, s1, s0 +; GFX6-NEXT: s_mul_i32 s15, s8, s2 +; GFX6-NEXT: v_mul_hi_u32 v2, v0, s3 +; GFX6-NEXT: v_mul_hi_u32 v0, v0, s15 +; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9 +; GFX6-NEXT: s_mul_i32 s4, s2, s3 +; GFX6-NEXT: v_readfirstlane_b32 s5, v2 +; GFX6-NEXT: v_readfirstlane_b32 s16, v0 +; GFX6-NEXT: v_mul_hi_u32 v0, v1, s15 +; GFX6-NEXT: v_mul_hi_u32 v1, v1, s3 +; GFX6-NEXT: s_add_u32 s4, s16, s4 +; GFX6-NEXT: s_addc_u32 s5, 0, s5 +; GFX6-NEXT: s_mul_i32 s15, s14, s15 +; GFX6-NEXT: v_readfirstlane_b32 s16, v0 +; GFX6-NEXT: s_add_u32 s4, s4, s15 +; GFX6-NEXT: s_addc_u32 s4, s5, s16 +; GFX6-NEXT: v_readfirstlane_b32 s5, v1 +; GFX6-NEXT: s_addc_u32 s5, s5, 0 +; GFX6-NEXT: s_mul_i32 s3, s14, s3 +; GFX6-NEXT: s_add_u32 s3, s4, s3 +; GFX6-NEXT: s_addc_u32 s4, 0, s5 +; GFX6-NEXT: s_add_i32 s5, s2, s3 +; GFX6-NEXT: v_mov_b32_e32 v0, s5 +; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 +; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0 +; GFX6-NEXT: s_or_b32 s2, s2, s3 +; GFX6-NEXT: s_cmp_lg_u32 s2, 0 +; GFX6-NEXT: s_addc_u32 s4, s14, s4 +; GFX6-NEXT: s_mul_i32 s2, s8, s4 +; GFX6-NEXT: v_readfirstlane_b32 s3, v0 +; GFX6-NEXT: s_add_i32 s2, s3, s2 +; GFX6-NEXT: s_mul_i32 s9, s9, s5 +; GFX6-NEXT: s_mul_i32 s3, s8, s5 +; GFX6-NEXT: s_add_i32 s2, s2, s9 +; GFX6-NEXT: v_mov_b32_e32 v2, s3 +; GFX6-NEXT: v_mov_b32_e32 v0, s2 +; GFX6-NEXT: v_mul_hi_u32 v3, s4, v2 +; GFX6-NEXT: v_mul_hi_u32 v2, s5, v2 +; GFX6-NEXT: v_mul_hi_u32 v1, s4, v0 +; GFX6-NEXT: v_mul_hi_u32 v0, s5, v0 +; GFX6-NEXT: s_mul_i32 s9, s5, s2 +; GFX6-NEXT: v_readfirstlane_b32 s15, v2 +; GFX6-NEXT: s_add_u32 s9, s15, s9 +; GFX6-NEXT: v_readfirstlane_b32 s14, v0 +; GFX6-NEXT: s_mul_i32 s3, s4, s3 +; GFX6-NEXT: s_addc_u32 s14, 0, s14 +; GFX6-NEXT: v_readfirstlane_b32 s8, v3 +; GFX6-NEXT: s_add_u32 s3, s9, s3 +; GFX6-NEXT: s_addc_u32 s3, s14, s8 +; GFX6-NEXT: v_readfirstlane_b32 s8, v1 +; GFX6-NEXT: s_addc_u32 s8, s8, 0 +; GFX6-NEXT: s_mul_i32 s2, s4, s2 +; GFX6-NEXT: s_add_u32 s2, s3, s2 +; GFX6-NEXT: s_addc_u32 s8, 0, s8 +; GFX6-NEXT: s_add_i32 s14, s5, s2 +; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 +; GFX6-NEXT: s_or_b32 s2, s2, s3 +; GFX6-NEXT: s_cmp_lg_u32 s2, 0 +; GFX6-NEXT: s_addc_u32 s15, s4, s8 +; GFX6-NEXT: s_ashr_i32 s4, s11, 31 +; GFX6-NEXT: s_add_u32 s2, s10, s4 +; GFX6-NEXT: s_mov_b32 s5, s4 +; GFX6-NEXT: s_addc_u32 s3, s11, s4 +; GFX6-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5] +; GFX6-NEXT: v_mov_b32_e32 v0, s15 +; GFX6-NEXT: v_mul_hi_u32 v1, s8, v0 +; GFX6-NEXT: v_mov_b32_e32 v2, s14 +; GFX6-NEXT: v_mul_hi_u32 v3, s8, v2 +; GFX6-NEXT: s_mul_i32 s2, s8, s15 +; GFX6-NEXT: v_readfirstlane_b32 s10, v1 +; GFX6-NEXT: v_mul_hi_u32 v1, s9, v2 +; GFX6-NEXT: v_readfirstlane_b32 s11, v3 ; GFX6-NEXT: v_mul_hi_u32 v0, s9, v0 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc -; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc -; GFX6-NEXT: v_mul_lo_u32 v1, s14, v1 -; GFX6-NEXT: v_mul_hi_u32 v2, s14, v0 -; GFX6-NEXT: v_mul_lo_u32 v3, s15, v0 -; GFX6-NEXT: v_mul_lo_u32 v0, s14, v0 -; GFX6-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s9, v1 -; GFX6-NEXT: v_mov_b32_e32 v3, s15 -; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s8, v0 -; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc -; GFX6-NEXT: v_subrev_i32_e64 v4, s[0:1], s14, v0 -; GFX6-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s15, v5 -; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3] -; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s14, v4 -; GFX6-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] -; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s15, v5 -; GFX6-NEXT: v_subrev_i32_e64 v3, s[0:1], s14, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3] -; GFX6-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] -; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] -; GFX6-NEXT: s_ashr_i32 s0, s17, 31 -; GFX6-NEXT: s_add_u32 s2, s16, s0 -; GFX6-NEXT: s_mov_b32 s1, s0 -; GFX6-NEXT: s_addc_u32 s3, s17, s0 -; GFX6-NEXT: v_mov_b32_e32 v4, s9 -; GFX6-NEXT: s_xor_b64 s[8:9], s[2:3], s[0:1] -; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc -; GFX6-NEXT: v_cvt_f32_u32_e32 v4, s8 -; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s9 -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s15, v1 -; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s14, v0 -; GFX6-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 -; GFX6-NEXT: v_rcp_f32_e32 v4, v4 -; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s15, v1 -; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v7, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 -; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GFX6-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v4 -; GFX6-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2 -; GFX6-NEXT: v_trunc_f32_e32 v4, v4 -; GFX6-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4 -; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GFX6-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GFX6-NEXT: s_sub_u32 s0, 0, s8 -; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GFX6-NEXT: v_mul_hi_u32 v3, s0, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, s0, v4 -; GFX6-NEXT: s_subb_u32 s1, 0, s9 -; GFX6-NEXT: v_mul_lo_u32 v6, s1, v2 -; GFX6-NEXT: s_ashr_i32 s14, s11, 31 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; GFX6-NEXT: v_mul_lo_u32 v5, s0, v2 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GFX6-NEXT: v_mul_lo_u32 v6, v2, v3 -; GFX6-NEXT: v_mul_hi_u32 v7, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v8, v2, v3 -; GFX6-NEXT: v_mul_hi_u32 v9, v4, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, v4, v3 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GFX6-NEXT: v_mul_lo_u32 v8, v4, v5 -; GFX6-NEXT: v_mul_hi_u32 v5, v4, v5 -; GFX6-NEXT: s_mov_b32 s15, s14 -; GFX6-NEXT: v_xor_b32_e32 v0, s12, v0 -; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v8 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v7, v5, vcc -; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v9, vcc -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v4, v5, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, s0, v3 -; GFX6-NEXT: v_mul_hi_u32 v5, s0, v2 -; GFX6-NEXT: v_mul_lo_u32 v6, s1, v2 -; GFX6-NEXT: v_xor_b32_e32 v1, s12, v1 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; GFX6-NEXT: v_mul_lo_u32 v5, s0, v2 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v6 -; GFX6-NEXT: v_mul_lo_u32 v8, v2, v4 -; GFX6-NEXT: v_mul_hi_u32 v9, v2, v5 -; GFX6-NEXT: v_mul_hi_u32 v10, v2, v4 -; GFX6-NEXT: v_mul_hi_u32 v7, v3, v5 -; GFX6-NEXT: v_mul_lo_u32 v5, v3, v5 -; GFX6-NEXT: v_mul_hi_u32 v6, v3, v4 -; GFX6-NEXT: v_add_i32_e32 v8, vcc, v9, v8 -; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v10, vcc -; GFX6-NEXT: v_mul_lo_u32 v4, v3, v4 -; GFX6-NEXT: v_add_i32_e32 v5, vcc, v8, v5 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v9, v7, vcc -; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v6, vcc -; GFX6-NEXT: s_add_u32 s0, s10, s14 -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GFX6-NEXT: s_addc_u32 s1, s11, s14 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v5, vcc -; GFX6-NEXT: s_xor_b64 s[10:11], s[0:1], s[14:15] -; GFX6-NEXT: v_mul_lo_u32 v4, s10, v3 -; GFX6-NEXT: v_mul_hi_u32 v5, s10, v2 -; GFX6-NEXT: v_mul_hi_u32 v7, s10, v3 -; GFX6-NEXT: v_mul_hi_u32 v8, s11, v3 -; GFX6-NEXT: v_mul_lo_u32 v3, s11, v3 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v5, v4 -; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GFX6-NEXT: v_mul_lo_u32 v7, s11, v2 -; GFX6-NEXT: v_mul_hi_u32 v2, s11, v2 -; GFX6-NEXT: v_mov_b32_e32 v6, s12 -; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v7 -; GFX6-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc -; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GFX6-NEXT: v_mul_lo_u32 v3, s8, v3 -; GFX6-NEXT: v_mul_hi_u32 v4, s8, v2 -; GFX6-NEXT: v_mul_lo_u32 v5, s9, v2 -; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s12, v0 -; GFX6-NEXT: v_mul_lo_u32 v2, s8, v2 -; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GFX6-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s11, v3 -; GFX6-NEXT: v_mov_b32_e32 v5, s9 -; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s10, v2 -; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc -; GFX6-NEXT: v_subrev_i32_e64 v6, s[0:1], s8, v2 -; GFX6-NEXT: v_subbrev_u32_e64 v7, s[2:3], 0, v4, s[0:1] -; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v7 -; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[2:3] -; GFX6-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v6 -; GFX6-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[2:3] -; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v7 -; GFX6-NEXT: v_subrev_i32_e64 v5, s[0:1], s8, v6 -; GFX6-NEXT: v_cndmask_b32_e64 v8, v8, v9, s[2:3] -; GFX6-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] -; GFX6-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v8 -; GFX6-NEXT: v_cndmask_b32_e64 v5, v6, v5, s[0:1] -; GFX6-NEXT: v_mov_b32_e32 v6, s11 -; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v6, v3, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v3 -; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v2 -; GFX6-NEXT: v_cndmask_b32_e64 v4, v7, v4, s[0:1] -; GFX6-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, s9, v3 -; GFX6-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc -; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc -; GFX6-NEXT: v_xor_b32_e32 v2, s14, v2 -; GFX6-NEXT: v_xor_b32_e32 v3, s14, v3 -; GFX6-NEXT: v_mov_b32_e32 v4, s14 -; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s14, v2 -; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v4, vcc -; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 +; GFX6-NEXT: s_add_u32 s2, s11, s2 +; GFX6-NEXT: s_addc_u32 s10, 0, s10 +; GFX6-NEXT: s_mul_i32 s11, s9, s14 +; GFX6-NEXT: v_readfirstlane_b32 s14, v1 +; GFX6-NEXT: s_add_u32 s2, s2, s11 +; GFX6-NEXT: s_addc_u32 s2, s10, s14 +; GFX6-NEXT: v_readfirstlane_b32 s10, v0 +; GFX6-NEXT: s_addc_u32 s10, s10, 0 +; GFX6-NEXT: s_mul_i32 s11, s9, s15 +; GFX6-NEXT: s_add_u32 s11, s2, s11 +; GFX6-NEXT: v_mov_b32_e32 v0, s11 +; GFX6-NEXT: v_mul_hi_u32 v0, s6, v0 +; GFX6-NEXT: s_addc_u32 s10, 0, s10 +; GFX6-NEXT: s_mul_i32 s10, s6, s10 +; GFX6-NEXT: s_mov_b32 s3, 0xf000 +; GFX6-NEXT: v_readfirstlane_b32 s14, v0 +; GFX6-NEXT: s_add_i32 s10, s14, s10 +; GFX6-NEXT: s_mul_i32 s14, s7, s11 +; GFX6-NEXT: s_add_i32 s14, s10, s14 +; GFX6-NEXT: s_sub_i32 s15, s9, s14 +; GFX6-NEXT: s_mul_i32 s10, s6, s11 +; GFX6-NEXT: s_sub_i32 s8, s8, s10 +; GFX6-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX6-NEXT: s_or_b32 s16, s10, s11 +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 +; GFX6-NEXT: s_subb_u32 s15, s15, s7 +; GFX6-NEXT: s_sub_i32 s17, s8, s6 +; GFX6-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX6-NEXT: s_or_b32 s10, s10, s11 +; GFX6-NEXT: s_cmp_lg_u32 s10, 0 +; GFX6-NEXT: s_subb_u32 s18, s15, 0 +; GFX6-NEXT: s_cmp_ge_u32 s18, s7 +; GFX6-NEXT: s_cselect_b32 s11, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s17, s6 +; GFX6-NEXT: s_cselect_b32 s19, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s18, s7 +; GFX6-NEXT: s_cselect_b32 s19, s19, s11 +; GFX6-NEXT: s_cmp_lg_u32 s10, 0 +; GFX6-NEXT: s_subb_u32 s15, s15, s7 +; GFX6-NEXT: s_sub_i32 s20, s17, s6 +; GFX6-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX6-NEXT: s_or_b32 s10, s10, s11 +; GFX6-NEXT: s_cmp_lg_u32 s10, 0 +; GFX6-NEXT: s_subb_u32 s10, s15, 0 +; GFX6-NEXT: s_cmp_lg_u32 s19, 0 +; GFX6-NEXT: s_cselect_b32 s11, s20, s17 +; GFX6-NEXT: s_cselect_b32 s10, s10, s18 +; GFX6-NEXT: s_cmp_lg_u32 s16, 0 +; GFX6-NEXT: s_subb_u32 s9, s9, s14 +; GFX6-NEXT: s_cmp_ge_u32 s9, s7 +; GFX6-NEXT: s_cselect_b32 s14, -1, 0 +; GFX6-NEXT: s_cmp_ge_u32 s8, s6 +; GFX6-NEXT: s_cselect_b32 s6, -1, 0 +; GFX6-NEXT: s_cmp_eq_u32 s9, s7 +; GFX6-NEXT: s_cselect_b32 s6, s6, s14 +; GFX6-NEXT: s_cmp_lg_u32 s6, 0 +; GFX6-NEXT: s_cselect_b32 s7, s10, s9 +; GFX6-NEXT: s_cselect_b32 s6, s11, s8 +; GFX6-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5] +; GFX6-NEXT: s_sub_u32 s5, s6, s4 +; GFX6-NEXT: s_subb_u32 s4, s7, s4 +; GFX6-NEXT: s_mov_b32 s2, -1 +; GFX6-NEXT: v_mov_b32_e32 v0, s12 +; GFX6-NEXT: v_mov_b32_e32 v1, s13 +; GFX6-NEXT: v_mov_b32_e32 v2, s5 +; GFX6-NEXT: v_mov_b32_e32 v3, s4 +; GFX6-NEXT: s_waitcnt lgkmcnt(0) +; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GFX6-NEXT: s_endpgm ; ; GFX9-LABEL: srem_v2i64_pow2_shl_denom: ; GFX9: ; %bb.0: ; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34 -; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 -; GFX9-NEXT: v_mov_b32_e32 v4, 0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s12 -; GFX9-NEXT: s_lshl_b64 s[14:15], 0x1000, s14 -; GFX9-NEXT: s_ashr_i32 s2, s1, 31 -; GFX9-NEXT: s_add_u32 s0, s0, s2 -; GFX9-NEXT: s_mov_b32 s3, s2 -; GFX9-NEXT: s_addc_u32 s1, s1, s2 -; GFX9-NEXT: s_xor_b64 s[12:13], s[0:1], s[2:3] -; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s12 -; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s13 -; GFX9-NEXT: s_sub_u32 s0, 0, s12 -; GFX9-NEXT: s_subb_u32 s1, 0, s13 +; GFX9-NEXT: s_lshl_b64 s[2:3], 0x1000, s12 +; GFX9-NEXT: s_lshl_b64 s[0:1], 0x1000, s14 +; GFX9-NEXT: s_ashr_i32 s6, s3, 31 +; GFX9-NEXT: s_add_u32 s2, s2, s6 +; GFX9-NEXT: s_mov_b32 s7, s6 +; GFX9-NEXT: s_addc_u32 s3, s3, s6 +; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7] +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GFX9-NEXT: s_sub_u32 s12, 0, s2 +; GFX9-NEXT: s_subb_u32 s13, 0, s3 ; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -9627,264 +9812,257 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: v_readfirstlane_b32 s2, v1 -; GFX9-NEXT: v_readfirstlane_b32 s3, v0 -; GFX9-NEXT: s_mul_i32 s4, s0, s2 -; GFX9-NEXT: s_mul_hi_u32 s16, s0, s3 -; GFX9-NEXT: s_mul_i32 s5, s1, s3 -; GFX9-NEXT: s_add_i32 s4, s16, s4 -; GFX9-NEXT: s_mul_i32 s17, s0, s3 -; GFX9-NEXT: s_add_i32 s4, s4, s5 -; GFX9-NEXT: s_mul_hi_u32 s5, s3, s4 -; GFX9-NEXT: s_mul_i32 s16, s3, s4 -; GFX9-NEXT: s_mul_hi_u32 s3, s3, s17 -; GFX9-NEXT: s_add_u32 s3, s3, s16 -; GFX9-NEXT: s_addc_u32 s5, 0, s5 -; GFX9-NEXT: s_mul_hi_u32 s18, s2, s17 -; GFX9-NEXT: s_mul_i32 s17, s2, s17 -; GFX9-NEXT: s_add_u32 s3, s3, s17 -; GFX9-NEXT: s_mul_hi_u32 s16, s2, s4 -; GFX9-NEXT: s_addc_u32 s3, s5, s18 -; GFX9-NEXT: s_addc_u32 s5, s16, 0 -; GFX9-NEXT: s_mul_i32 s4, s2, s4 -; GFX9-NEXT: s_add_u32 s3, s3, s4 -; GFX9-NEXT: s_addc_u32 s4, 0, s5 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s3, v0 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s2, s2, s4 -; GFX9-NEXT: v_readfirstlane_b32 s4, v0 -; GFX9-NEXT: s_mul_i32 s3, s0, s2 -; GFX9-NEXT: s_mul_hi_u32 s5, s0, s4 -; GFX9-NEXT: s_add_i32 s3, s5, s3 -; GFX9-NEXT: s_mul_i32 s1, s1, s4 -; GFX9-NEXT: s_add_i32 s3, s3, s1 -; GFX9-NEXT: s_mul_i32 s0, s0, s4 -; GFX9-NEXT: s_mul_hi_u32 s5, s2, s0 -; GFX9-NEXT: s_mul_i32 s16, s2, s0 -; GFX9-NEXT: s_mul_i32 s18, s4, s3 -; GFX9-NEXT: s_mul_hi_u32 s0, s4, s0 -; GFX9-NEXT: s_mul_hi_u32 s17, s4, s3 -; GFX9-NEXT: s_add_u32 s0, s0, s18 -; GFX9-NEXT: s_addc_u32 s4, 0, s17 -; GFX9-NEXT: s_add_u32 s0, s0, s16 -; GFX9-NEXT: s_mul_hi_u32 s1, s2, s3 -; GFX9-NEXT: s_addc_u32 s0, s4, s5 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 -; GFX9-NEXT: s_mul_i32 s3, s2, s3 -; GFX9-NEXT: s_add_u32 s0, s0, s3 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s2, s2, s1 -; GFX9-NEXT: s_ashr_i32 s16, s9, 31 -; GFX9-NEXT: s_add_u32 s0, s8, s16 -; GFX9-NEXT: s_mov_b32 s17, s16 -; GFX9-NEXT: s_addc_u32 s1, s9, s16 -; GFX9-NEXT: s_xor_b64 s[4:5], s[0:1], s[16:17] -; GFX9-NEXT: v_readfirstlane_b32 s3, v0 -; GFX9-NEXT: s_mul_i32 s1, s4, s2 -; GFX9-NEXT: s_mul_hi_u32 s8, s4, s3 -; GFX9-NEXT: s_mul_hi_u32 s0, s4, s2 -; GFX9-NEXT: s_add_u32 s1, s8, s1 -; GFX9-NEXT: s_addc_u32 s0, 0, s0 -; GFX9-NEXT: s_mul_hi_u32 s9, s5, s3 -; GFX9-NEXT: s_mul_i32 s3, s5, s3 -; GFX9-NEXT: s_add_u32 s1, s1, s3 -; GFX9-NEXT: s_mul_hi_u32 s8, s5, s2 -; GFX9-NEXT: s_addc_u32 s0, s0, s9 -; GFX9-NEXT: s_addc_u32 s1, s8, 0 -; GFX9-NEXT: s_mul_i32 s2, s5, s2 +; GFX9-NEXT: v_readfirstlane_b32 s14, v1 +; GFX9-NEXT: v_readfirstlane_b32 s6, v0 +; GFX9-NEXT: s_mul_i32 s7, s12, s14 +; GFX9-NEXT: s_mul_hi_u32 s16, s12, s6 +; GFX9-NEXT: s_mul_i32 s15, s13, s6 +; GFX9-NEXT: s_add_i32 s7, s16, s7 +; GFX9-NEXT: s_mul_i32 s17, s12, s6 +; GFX9-NEXT: s_add_i32 s7, s7, s15 +; GFX9-NEXT: s_mul_hi_u32 s16, s6, s17 +; GFX9-NEXT: s_mul_i32 s18, s6, s7 +; GFX9-NEXT: s_mul_hi_u32 s15, s6, s7 +; GFX9-NEXT: s_add_u32 s16, s16, s18 +; GFX9-NEXT: s_addc_u32 s15, 0, s15 +; GFX9-NEXT: s_mul_hi_u32 s18, s14, s17 +; GFX9-NEXT: s_mul_i32 s17, s14, s17 +; GFX9-NEXT: s_add_u32 s16, s16, s17 +; GFX9-NEXT: s_mul_hi_u32 s19, s14, s7 +; GFX9-NEXT: s_addc_u32 s15, s15, s18 +; GFX9-NEXT: s_addc_u32 s16, s19, 0 +; GFX9-NEXT: s_mul_i32 s7, s14, s7 +; GFX9-NEXT: s_add_u32 s7, s15, s7 +; GFX9-NEXT: s_addc_u32 s15, 0, s16 +; GFX9-NEXT: s_add_i32 s16, s6, s7 +; GFX9-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-NEXT: s_addc_u32 s14, s14, s15 +; GFX9-NEXT: s_mul_i32 s6, s12, s14 +; GFX9-NEXT: s_mul_hi_u32 s7, s12, s16 +; GFX9-NEXT: s_add_i32 s6, s7, s6 +; GFX9-NEXT: s_mul_i32 s13, s13, s16 +; GFX9-NEXT: s_add_i32 s6, s6, s13 +; GFX9-NEXT: s_mul_i32 s12, s12, s16 +; GFX9-NEXT: s_mul_hi_u32 s13, s14, s12 +; GFX9-NEXT: s_mul_i32 s15, s14, s12 +; GFX9-NEXT: s_mul_i32 s18, s16, s6 +; GFX9-NEXT: s_mul_hi_u32 s12, s16, s12 +; GFX9-NEXT: s_mul_hi_u32 s17, s16, s6 +; GFX9-NEXT: s_add_u32 s12, s12, s18 +; GFX9-NEXT: s_addc_u32 s17, 0, s17 +; GFX9-NEXT: s_add_u32 s12, s12, s15 +; GFX9-NEXT: s_mul_hi_u32 s7, s14, s6 +; GFX9-NEXT: s_addc_u32 s12, s17, s13 +; GFX9-NEXT: s_addc_u32 s7, s7, 0 +; GFX9-NEXT: s_mul_i32 s6, s14, s6 +; GFX9-NEXT: s_add_u32 s6, s12, s6 +; GFX9-NEXT: s_addc_u32 s12, 0, s7 +; GFX9-NEXT: s_add_i32 s16, s16, s6 +; GFX9-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX9-NEXT: s_addc_u32 s12, s14, s12 +; GFX9-NEXT: s_ashr_i32 s6, s9, 31 +; GFX9-NEXT: s_add_u32 s8, s8, s6 +; GFX9-NEXT: s_mov_b32 s7, s6 +; GFX9-NEXT: s_addc_u32 s9, s9, s6 +; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7] +; GFX9-NEXT: s_mul_i32 s14, s8, s12 +; GFX9-NEXT: s_mul_hi_u32 s15, s8, s16 +; GFX9-NEXT: s_mul_hi_u32 s13, s8, s12 +; GFX9-NEXT: s_add_u32 s14, s15, s14 +; GFX9-NEXT: s_addc_u32 s13, 0, s13 +; GFX9-NEXT: s_mul_hi_u32 s17, s9, s16 +; GFX9-NEXT: s_mul_i32 s16, s9, s16 +; GFX9-NEXT: s_add_u32 s14, s14, s16 +; GFX9-NEXT: s_mul_hi_u32 s15, s9, s12 +; GFX9-NEXT: s_addc_u32 s13, s13, s17 +; GFX9-NEXT: s_addc_u32 s14, s15, 0 +; GFX9-NEXT: s_mul_i32 s12, s9, s12 +; GFX9-NEXT: s_add_u32 s12, s13, s12 +; GFX9-NEXT: s_addc_u32 s13, 0, s14 +; GFX9-NEXT: s_mul_i32 s13, s2, s13 +; GFX9-NEXT: s_mul_hi_u32 s14, s2, s12 +; GFX9-NEXT: s_add_i32 s13, s14, s13 +; GFX9-NEXT: s_mul_i32 s14, s3, s12 +; GFX9-NEXT: s_add_i32 s16, s13, s14 +; GFX9-NEXT: s_sub_i32 s14, s9, s16 +; GFX9-NEXT: s_mul_i32 s12, s2, s12 +; GFX9-NEXT: s_sub_i32 s8, s8, s12 +; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GFX9-NEXT: s_subb_u32 s17, s14, s3 +; GFX9-NEXT: s_sub_i32 s18, s8, s2 +; GFX9-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 +; GFX9-NEXT: s_subb_u32 s19, s17, 0 +; GFX9-NEXT: s_cmp_ge_u32 s19, s3 +; GFX9-NEXT: s_cselect_b32 s20, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s18, s2 +; GFX9-NEXT: s_cselect_b32 s21, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s19, s3 +; GFX9-NEXT: s_cselect_b32 s20, s21, s20 +; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 +; GFX9-NEXT: s_subb_u32 s17, s17, s3 +; GFX9-NEXT: s_sub_i32 s21, s18, s2 +; GFX9-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 +; GFX9-NEXT: s_subb_u32 s14, s17, 0 +; GFX9-NEXT: s_cmp_lg_u32 s20, 0 +; GFX9-NEXT: s_cselect_b32 s15, s21, s18 +; GFX9-NEXT: s_cselect_b32 s14, s14, s19 +; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GFX9-NEXT: s_subb_u32 s9, s9, s16 +; GFX9-NEXT: s_cmp_ge_u32 s9, s3 +; GFX9-NEXT: s_cselect_b32 s12, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s8, s2 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s9, s3 +; GFX9-NEXT: s_cselect_b32 s2, s2, s12 +; GFX9-NEXT: s_cmp_lg_u32 s2, 0 +; GFX9-NEXT: s_cselect_b32 s3, s14, s9 +; GFX9-NEXT: s_cselect_b32 s2, s15, s8 +; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7] +; GFX9-NEXT: s_sub_u32 s12, s2, s6 +; GFX9-NEXT: s_subb_u32 s13, s3, s6 +; GFX9-NEXT: s_ashr_i32 s2, s1, 31 ; GFX9-NEXT: s_add_u32 s0, s0, s2 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: s_mul_i32 s1, s12, s1 -; GFX9-NEXT: s_mul_hi_u32 s2, s12, s0 -; GFX9-NEXT: s_add_i32 s1, s2, s1 -; GFX9-NEXT: s_mul_i32 s2, s13, s0 -; GFX9-NEXT: s_mul_i32 s0, s12, s0 -; GFX9-NEXT: s_add_i32 s8, s1, s2 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: s_sub_i32 s1, s5, s8 -; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s4, v0 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_subb_u32 s4, s1, s13 -; GFX9-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s12, v0 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s9, s4, 0 -; GFX9-NEXT: s_cmp_ge_u32 s9, s13 -; GFX9-NEXT: s_cselect_b32 s17, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v1 -; GFX9-NEXT: s_cmp_eq_u32 s9, s13 -; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[2:3] -; GFX9-NEXT: v_mov_b32_e32 v3, s17 -; GFX9-NEXT: s_cselect_b64 s[2:3], -1, 0 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[2:3] -; GFX9-NEXT: s_subb_u32 s2, s4, s13 -; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s12, v1 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s2, s2, 0 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v2, s9 -; GFX9-NEXT: v_mov_b32_e32 v3, s2 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; GFX9-NEXT: s_subb_u32 s0, s5, s8 -; GFX9-NEXT: s_cmp_ge_u32 s0, s13 -; GFX9-NEXT: s_cselect_b32 s1, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 -; GFX9-NEXT: s_cmp_eq_u32 s0, s13 -; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc -; GFX9-NEXT: v_mov_b32_e32 v5, s1 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc -; GFX9-NEXT: v_mov_b32_e32 v5, s0 -; GFX9-NEXT: s_ashr_i32 s0, s15, 31 -; GFX9-NEXT: s_add_u32 s2, s14, s0 -; GFX9-NEXT: s_mov_b32 s1, s0 -; GFX9-NEXT: s_addc_u32 s3, s15, s0 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GFX9-NEXT: s_xor_b64 s[4:5], s[2:3], s[0:1] -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s4 -; GFX9-NEXT: v_cvt_f32_u32_e32 v3, s5 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v5, v2, vcc -; GFX9-NEXT: v_xor_b32_e32 v0, s16, v0 -; GFX9-NEXT: v_xor_b32_e32 v2, s16, v2 -; GFX9-NEXT: v_mac_f32_e32 v1, 0x4f800000, v3 -; GFX9-NEXT: v_rcp_f32_e32 v3, v1 -; GFX9-NEXT: v_mov_b32_e32 v5, s16 -; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s16, v0 -; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v5, vcc -; GFX9-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v3 -; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 -; GFX9-NEXT: v_trunc_f32_e32 v3, v3 -; GFX9-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 +; GFX9-NEXT: s_mov_b32 s3, s2 +; GFX9-NEXT: s_addc_u32 s1, s1, s2 +; GFX9-NEXT: s_xor_b64 s[2:3], s[0:1], s[2:3] +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24 +; GFX9-NEXT: s_sub_u32 s6, 0, s2 +; GFX9-NEXT: s_subb_u32 s7, 0, s3 +; GFX9-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 +; GFX9-NEXT: v_rcp_f32_e32 v1, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 +; GFX9-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1 +; GFX9-NEXT: v_trunc_f32_e32 v2, v2 +; GFX9-NEXT: v_mac_f32_e32 v1, 0xcf800000, v2 +; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GFX9-NEXT: s_sub_u32 s0, 0, s4 -; GFX9-NEXT: s_subb_u32 s1, 0, s5 -; GFX9-NEXT: v_readfirstlane_b32 s2, v2 -; GFX9-NEXT: v_readfirstlane_b32 s9, v3 -; GFX9-NEXT: s_mul_hi_u32 s8, s0, s2 -; GFX9-NEXT: s_mul_i32 s12, s0, s9 -; GFX9-NEXT: s_mul_i32 s3, s1, s2 -; GFX9-NEXT: s_add_i32 s8, s8, s12 -; GFX9-NEXT: s_add_i32 s8, s8, s3 -; GFX9-NEXT: s_mul_i32 s13, s0, s2 -; GFX9-NEXT: s_mul_hi_u32 s3, s2, s8 -; GFX9-NEXT: s_mul_i32 s12, s2, s8 -; GFX9-NEXT: s_mul_hi_u32 s2, s2, s13 -; GFX9-NEXT: s_add_u32 s2, s2, s12 -; GFX9-NEXT: s_addc_u32 s3, 0, s3 -; GFX9-NEXT: s_mul_hi_u32 s14, s9, s13 -; GFX9-NEXT: s_mul_i32 s13, s9, s13 -; GFX9-NEXT: s_add_u32 s2, s2, s13 -; GFX9-NEXT: s_mul_hi_u32 s12, s9, s8 -; GFX9-NEXT: s_addc_u32 s2, s3, s14 -; GFX9-NEXT: s_addc_u32 s3, s12, 0 +; GFX9-NEXT: v_readfirstlane_b32 s4, v1 +; GFX9-NEXT: v_readfirstlane_b32 s9, v2 +; GFX9-NEXT: s_mul_hi_u32 s8, s6, s4 +; GFX9-NEXT: s_mul_i32 s14, s6, s9 +; GFX9-NEXT: s_mul_i32 s5, s7, s4 +; GFX9-NEXT: s_add_i32 s8, s8, s14 +; GFX9-NEXT: s_add_i32 s8, s8, s5 +; GFX9-NEXT: s_mul_i32 s15, s6, s4 +; GFX9-NEXT: s_mul_i32 s14, s4, s8 +; GFX9-NEXT: s_mul_hi_u32 s16, s4, s15 +; GFX9-NEXT: s_mul_hi_u32 s5, s4, s8 +; GFX9-NEXT: s_add_u32 s14, s16, s14 +; GFX9-NEXT: s_addc_u32 s5, 0, s5 +; GFX9-NEXT: s_mul_hi_u32 s17, s9, s15 +; GFX9-NEXT: s_mul_i32 s15, s9, s15 +; GFX9-NEXT: s_add_u32 s14, s14, s15 +; GFX9-NEXT: s_mul_hi_u32 s16, s9, s8 +; GFX9-NEXT: s_addc_u32 s5, s5, s17 +; GFX9-NEXT: s_addc_u32 s14, s16, 0 ; GFX9-NEXT: s_mul_i32 s8, s9, s8 -; GFX9-NEXT: s_add_u32 s2, s2, s8 -; GFX9-NEXT: s_addc_u32 s3, 0, s3 -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s2, v2 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s2, s9, s3 -; GFX9-NEXT: v_readfirstlane_b32 s8, v2 -; GFX9-NEXT: s_mul_i32 s3, s0, s2 -; GFX9-NEXT: s_mul_hi_u32 s9, s0, s8 -; GFX9-NEXT: s_add_i32 s3, s9, s3 -; GFX9-NEXT: s_mul_i32 s1, s1, s8 -; GFX9-NEXT: s_add_i32 s3, s3, s1 -; GFX9-NEXT: s_mul_i32 s0, s0, s8 -; GFX9-NEXT: s_mul_hi_u32 s9, s2, s0 -; GFX9-NEXT: s_mul_i32 s12, s2, s0 -; GFX9-NEXT: s_mul_i32 s14, s8, s3 -; GFX9-NEXT: s_mul_hi_u32 s0, s8, s0 -; GFX9-NEXT: s_mul_hi_u32 s13, s8, s3 -; GFX9-NEXT: s_add_u32 s0, s0, s14 -; GFX9-NEXT: s_addc_u32 s8, 0, s13 -; GFX9-NEXT: s_add_u32 s0, s0, s12 -; GFX9-NEXT: s_mul_hi_u32 s1, s2, s3 -; GFX9-NEXT: s_addc_u32 s0, s8, s9 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 -; GFX9-NEXT: s_mul_i32 s3, s2, s3 -; GFX9-NEXT: s_add_u32 s0, s0, s3 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s2, s2, s1 -; GFX9-NEXT: s_ashr_i32 s8, s11, 31 -; GFX9-NEXT: s_add_u32 s0, s10, s8 -; GFX9-NEXT: s_mov_b32 s9, s8 -; GFX9-NEXT: s_addc_u32 s1, s11, s8 -; GFX9-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9] -; GFX9-NEXT: v_readfirstlane_b32 s3, v2 -; GFX9-NEXT: s_mul_i32 s1, s10, s2 -; GFX9-NEXT: s_mul_hi_u32 s9, s10, s3 -; GFX9-NEXT: s_mul_hi_u32 s0, s10, s2 -; GFX9-NEXT: s_add_u32 s1, s9, s1 -; GFX9-NEXT: s_addc_u32 s0, 0, s0 -; GFX9-NEXT: s_mul_hi_u32 s12, s11, s3 -; GFX9-NEXT: s_mul_i32 s3, s11, s3 -; GFX9-NEXT: s_add_u32 s1, s1, s3 -; GFX9-NEXT: s_mul_hi_u32 s9, s11, s2 -; GFX9-NEXT: s_addc_u32 s0, s0, s12 -; GFX9-NEXT: s_addc_u32 s1, s9, 0 -; GFX9-NEXT: s_mul_i32 s2, s11, s2 -; GFX9-NEXT: s_add_u32 s0, s0, s2 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: s_mul_i32 s1, s4, s1 -; GFX9-NEXT: s_mul_hi_u32 s2, s4, s0 -; GFX9-NEXT: s_add_i32 s1, s2, s1 -; GFX9-NEXT: s_mul_i32 s2, s5, s0 -; GFX9-NEXT: s_mul_i32 s0, s4, s0 -; GFX9-NEXT: s_add_i32 s9, s1, s2 -; GFX9-NEXT: v_mov_b32_e32 v2, s0 -; GFX9-NEXT: s_sub_i32 s1, s11, s9 -; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s10, v2 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_subb_u32 s10, s1, s5 -; GFX9-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s4, v2 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s12, s10, 0 -; GFX9-NEXT: s_cmp_ge_u32 s12, s5 -; GFX9-NEXT: s_cselect_b32 s13, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e64 s[2:3], s4, v3 -; GFX9-NEXT: s_cmp_eq_u32 s12, s5 -; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[2:3] -; GFX9-NEXT: v_mov_b32_e32 v6, s13 -; GFX9-NEXT: s_cselect_b64 s[2:3], -1, 0 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: v_cndmask_b32_e64 v5, v6, v5, s[2:3] -; GFX9-NEXT: s_subb_u32 s2, s10, s5 -; GFX9-NEXT: v_subrev_co_u32_e64 v6, s[0:1], s4, v3 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s2, s2, 0 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v5 -; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, v6, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v5, s12 -; GFX9-NEXT: v_mov_b32_e32 v6, s2 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, v6, s[0:1] -; GFX9-NEXT: s_subb_u32 s0, s11, s9 -; GFX9-NEXT: s_cmp_ge_u32 s0, s5 -; GFX9-NEXT: s_cselect_b32 s1, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s4, v2 -; GFX9-NEXT: s_cmp_eq_u32 s0, s5 -; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GFX9-NEXT: v_mov_b32_e32 v7, s1 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6 -; GFX9-NEXT: v_mov_b32_e32 v7, s0 -; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc -; GFX9-NEXT: v_xor_b32_e32 v2, s8, v2 -; GFX9-NEXT: v_xor_b32_e32 v3, s8, v5 -; GFX9-NEXT: v_mov_b32_e32 v5, s8 -; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s8, v2 -; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v5, vcc -; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7] +; GFX9-NEXT: s_add_u32 s5, s5, s8 +; GFX9-NEXT: s_addc_u32 s8, 0, s14 +; GFX9-NEXT: s_add_i32 s14, s4, s5 +; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-NEXT: s_addc_u32 s8, s9, s8 +; GFX9-NEXT: s_mul_i32 s4, s6, s8 +; GFX9-NEXT: s_mul_hi_u32 s5, s6, s14 +; GFX9-NEXT: s_add_i32 s4, s5, s4 +; GFX9-NEXT: s_mul_i32 s7, s7, s14 +; GFX9-NEXT: s_add_i32 s4, s4, s7 +; GFX9-NEXT: s_mul_i32 s6, s6, s14 +; GFX9-NEXT: s_mul_hi_u32 s7, s8, s6 +; GFX9-NEXT: s_mul_i32 s9, s8, s6 +; GFX9-NEXT: s_mul_i32 s16, s14, s4 +; GFX9-NEXT: s_mul_hi_u32 s6, s14, s6 +; GFX9-NEXT: s_mul_hi_u32 s15, s14, s4 +; GFX9-NEXT: s_add_u32 s6, s6, s16 +; GFX9-NEXT: s_addc_u32 s15, 0, s15 +; GFX9-NEXT: s_add_u32 s6, s6, s9 +; GFX9-NEXT: s_mul_hi_u32 s5, s8, s4 +; GFX9-NEXT: s_addc_u32 s6, s15, s7 +; GFX9-NEXT: s_addc_u32 s5, s5, 0 +; GFX9-NEXT: s_mul_i32 s4, s8, s4 +; GFX9-NEXT: s_add_u32 s4, s6, s4 +; GFX9-NEXT: s_addc_u32 s6, 0, s5 +; GFX9-NEXT: s_add_i32 s14, s14, s4 +; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX9-NEXT: s_addc_u32 s8, s8, s6 +; GFX9-NEXT: s_ashr_i32 s4, s11, 31 +; GFX9-NEXT: s_add_u32 s6, s10, s4 +; GFX9-NEXT: s_mov_b32 s5, s4 +; GFX9-NEXT: s_addc_u32 s7, s11, s4 +; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5] +; GFX9-NEXT: s_mul_i32 s10, s6, s8 +; GFX9-NEXT: s_mul_hi_u32 s11, s6, s14 +; GFX9-NEXT: s_mul_hi_u32 s9, s6, s8 +; GFX9-NEXT: s_add_u32 s10, s11, s10 +; GFX9-NEXT: s_addc_u32 s9, 0, s9 +; GFX9-NEXT: s_mul_hi_u32 s15, s7, s14 +; GFX9-NEXT: s_mul_i32 s14, s7, s14 +; GFX9-NEXT: s_add_u32 s10, s10, s14 +; GFX9-NEXT: s_mul_hi_u32 s11, s7, s8 +; GFX9-NEXT: s_addc_u32 s9, s9, s15 +; GFX9-NEXT: s_addc_u32 s10, s11, 0 +; GFX9-NEXT: s_mul_i32 s8, s7, s8 +; GFX9-NEXT: s_add_u32 s8, s9, s8 +; GFX9-NEXT: s_addc_u32 s9, 0, s10 +; GFX9-NEXT: s_mul_i32 s9, s2, s9 +; GFX9-NEXT: s_mul_hi_u32 s10, s2, s8 +; GFX9-NEXT: s_add_i32 s9, s10, s9 +; GFX9-NEXT: s_mul_i32 s10, s3, s8 +; GFX9-NEXT: s_add_i32 s14, s9, s10 +; GFX9-NEXT: s_sub_i32 s10, s7, s14 +; GFX9-NEXT: s_mul_i32 s8, s2, s8 +; GFX9-NEXT: s_sub_i32 s6, s6, s8 +; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX9-NEXT: s_subb_u32 s15, s10, s3 +; GFX9-NEXT: s_sub_i32 s16, s6, s2 +; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s17, s15, 0 +; GFX9-NEXT: s_cmp_ge_u32 s17, s3 +; GFX9-NEXT: s_cselect_b32 s18, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s16, s2 +; GFX9-NEXT: s_cselect_b32 s19, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s17, s3 +; GFX9-NEXT: s_cselect_b32 s18, s19, s18 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s15, s15, s3 +; GFX9-NEXT: s_sub_i32 s19, s16, s2 +; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s10, s15, 0 +; GFX9-NEXT: s_cmp_lg_u32 s18, 0 +; GFX9-NEXT: s_cselect_b32 s11, s19, s16 +; GFX9-NEXT: s_cselect_b32 s10, s10, s17 +; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX9-NEXT: s_subb_u32 s7, s7, s14 +; GFX9-NEXT: s_cmp_ge_u32 s7, s3 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s6, s2 +; GFX9-NEXT: s_cselect_b32 s2, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s7, s3 +; GFX9-NEXT: s_cselect_b32 s2, s2, s8 +; GFX9-NEXT: s_cmp_lg_u32 s2, 0 +; GFX9-NEXT: s_cselect_b32 s3, s10, s7 +; GFX9-NEXT: s_cselect_b32 s2, s11, s6 +; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX9-NEXT: s_sub_u32 s2, s2, s4 +; GFX9-NEXT: s_subb_u32 s3, s3, s4 +; GFX9-NEXT: v_mov_b32_e32 v1, s12 +; GFX9-NEXT: v_mov_b32_e32 v2, s13 +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: v_mov_b32_e32 v4, s3 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: global_store_dwordx4 v0, v[1:4], s[0:1] ; GFX9-NEXT: s_endpgm %shl.y = shl <2 x i64> , %y %r = srem <2 x i64> %x, %shl.y diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll index 9b5161961da6c..cca83bdd0b956 100644 --- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll +++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll @@ -1973,9 +1973,9 @@ define amdgpu_kernel void @vusubo64(ptr addrspace(1) %out, ptr addrspace(1) %car ; GCN-ISEL-LABEL: name: sudiv64 ; GCN-ISEL-LABEL: body: ; GCN-ISEL-LABEL: bb.3 -; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 +; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = S_UADDO_PSEUDO ; GCN-ISEL: S_ADD_CO_PSEUDO %{{[0-9]+}}, killed %{{[0-9]+}}, killed %[[CARRY]] -; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = V_SUB_CO_U32_e64 +; GCN-ISEL: %[[CARRY:[0-9]+]]:sreg_64_xexec = S_USUBO_PSEUDO ; GCN-ISEL: S_SUB_CO_PSEUDO killed %{{[0-9]+}}, %{{[0-9]+}}, %[[CARRY]] define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { @@ -2029,7 +2029,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; CISI-NEXT: v_mul_lo_u32 v4, s1, v0 ; CISI-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; CISI-NEXT: v_mul_lo_u32 v3, s0, v0 -; CISI-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; CISI-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; CISI-NEXT: v_mul_lo_u32 v6, v0, v2 ; CISI-NEXT: v_mul_hi_u32 v7, v0, v3 ; CISI-NEXT: v_mul_hi_u32 v8, v0, v2 @@ -2132,18 +2132,18 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; ; VI-LABEL: sudiv64: ; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 -; VI-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34 +; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_or_b64 s[0:1], s[10:11], s[2:3] -; VI-NEXT: s_mov_b32 s0, 0 -; VI-NEXT: s_cmp_lg_u64 s[0:1], 0 -; VI-NEXT: s_cbranch_scc0 .LBB16_4 +; VI-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5] +; VI-NEXT: s_mov_b32 s6, 0 +; VI-NEXT: s_cmp_lg_u64 s[6:7], 0 +; VI-NEXT: s_cbranch_scc0 .LBB16_3 ; VI-NEXT: ; %bb.1: -; VI-NEXT: v_cvt_f32_u32_e32 v0, s2 -; VI-NEXT: v_cvt_f32_u32_e32 v1, s3 -; VI-NEXT: s_sub_u32 s4, 0, s2 -; VI-NEXT: s_subb_u32 s5, 0, s3 +; VI-NEXT: v_cvt_f32_u32_e32 v0, s4 +; VI-NEXT: v_cvt_f32_u32_e32 v1, s5 +; VI-NEXT: s_sub_u32 s8, 0, s4 +; VI-NEXT: s_subb_u32 s9, 0, s5 ; VI-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; VI-NEXT: v_rcp_f32_e32 v0, v0 ; VI-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -2152,17 +2152,17 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; VI-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 ; VI-NEXT: v_cvt_u32_f32_e32 v4, v1 ; VI-NEXT: v_cvt_u32_f32_e32 v5, v0 -; VI-NEXT: v_mul_lo_u32 v2, s4, v4 -; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s4, v5, 0 -; VI-NEXT: v_mul_lo_u32 v3, s5, v5 +; VI-NEXT: v_mul_lo_u32 v2, s8, v4 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[6:7], s8, v5, 0 +; VI-NEXT: v_mul_lo_u32 v3, s9, v5 ; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2 ; VI-NEXT: v_add_u32_e32 v3, vcc, v1, v3 ; VI-NEXT: v_mul_hi_u32 v6, v5, v0 -; VI-NEXT: v_mad_u64_u32 v[1:2], s[0:1], v5, v3, 0 +; VI-NEXT: v_mad_u64_u32 v[1:2], s[6:7], v5, v3, 0 ; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v1 -; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v4, v0, 0 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v4, v0, 0 ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v2, vcc -; VI-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v4, v3, 0 +; VI-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v4, v3, 0 ; VI-NEXT: v_add_u32_e32 v0, vcc, v6, v0 ; VI-NEXT: v_addc_u32_e32 v0, vcc, v7, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc @@ -2170,15 +2170,15 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_add_u32_e32 v6, vcc, v5, v0 ; VI-NEXT: v_addc_u32_e32 v7, vcc, v4, v1, vcc -; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s4, v6, 0 -; VI-NEXT: v_mul_lo_u32 v4, s4, v7 -; VI-NEXT: v_mul_lo_u32 v5, s5, v6 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[6:7], s8, v6, 0 +; VI-NEXT: v_mul_lo_u32 v4, s8, v7 +; VI-NEXT: v_mul_lo_u32 v5, s9, v6 ; VI-NEXT: v_mul_hi_u32 v8, v6, v0 -; VI-NEXT: v_mad_u64_u32 v[2:3], s[0:1], v7, v0, 0 +; VI-NEXT: v_mad_u64_u32 v[2:3], s[6:7], v7, v0, 0 ; VI-NEXT: v_add_u32_e32 v1, vcc, v4, v1 -; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v5 -; VI-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v6, v1, 0 -; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v7, v1, 0 +; VI-NEXT: v_add_u32_e32 v1, vcc, v5, v1 +; VI-NEXT: v_mad_u64_u32 v[4:5], s[6:7], v6, v1, 0 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[6:7], v7, v1, 0 ; VI-NEXT: v_add_u32_e32 v4, vcc, v8, v4 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_add_u32_e32 v2, vcc, v4, v2 @@ -2188,119 +2188,117 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_add_u32_e32 v2, vcc, v6, v0 ; VI-NEXT: v_addc_u32_e32 v3, vcc, v7, v1, vcc -; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s10, v3, 0 -; VI-NEXT: v_mul_hi_u32 v4, s10, v2 -; VI-NEXT: v_readfirstlane_b32 s4, v1 -; VI-NEXT: v_readfirstlane_b32 s5, v0 -; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s11, v3, 0 -; VI-NEXT: v_mad_u64_u32 v[2:3], s[0:1], s11, v2, 0 -; VI-NEXT: v_readfirstlane_b32 s6, v4 -; VI-NEXT: s_add_u32 s0, s6, s5 -; VI-NEXT: s_addc_u32 s1, 0, s4 -; VI-NEXT: v_readfirstlane_b32 s6, v2 -; VI-NEXT: v_readfirstlane_b32 s5, v3 -; VI-NEXT: s_add_u32 s0, s0, s6 -; VI-NEXT: v_readfirstlane_b32 s4, v1 -; VI-NEXT: s_addc_u32 s0, s1, s5 -; VI-NEXT: s_addc_u32 s6, s4, 0 -; VI-NEXT: v_readfirstlane_b32 s1, v0 -; VI-NEXT: s_add_u32 s7, s0, s1 -; VI-NEXT: v_mov_b32_e32 v2, s7 -; VI-NEXT: v_mad_u64_u32 v[0:1], s[0:1], s2, v2, 0 -; VI-NEXT: s_addc_u32 s6, 0, s6 -; VI-NEXT: s_mul_i32 s0, s2, s6 -; VI-NEXT: v_readfirstlane_b32 s1, v1 -; VI-NEXT: s_add_i32 s0, s1, s0 -; VI-NEXT: s_mul_i32 s1, s3, s7 -; VI-NEXT: s_add_i32 s12, s0, s1 -; VI-NEXT: s_sub_i32 s0, s11, s12 -; VI-NEXT: v_sub_u32_e32 v0, vcc, s10, v0 -; VI-NEXT: s_cmp_lg_u64 vcc, 0 -; VI-NEXT: s_subb_u32 s13, s0, s3 -; VI-NEXT: v_subrev_u32_e64 v1, s[0:1], s2, v0 -; VI-NEXT: s_cmp_lg_u64 s[0:1], 0 -; VI-NEXT: s_subb_u32 s13, s13, 0 -; VI-NEXT: s_cmp_ge_u32 s13, s3 -; VI-NEXT: s_cselect_b32 s14, -1, 0 -; VI-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v1 -; VI-NEXT: s_cmp_eq_u32 s13, s3 -; VI-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[0:1] -; VI-NEXT: v_mov_b32_e32 v3, s14 -; VI-NEXT: s_cselect_b64 s[0:1], -1, 0 -; VI-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[0:1] -; VI-NEXT: s_add_u32 s0, s7, 1 -; VI-NEXT: s_addc_u32 s13, s6, 0 -; VI-NEXT: s_add_u32 s1, s7, 2 -; VI-NEXT: s_addc_u32 s7, s6, 0 -; VI-NEXT: v_mov_b32_e32 v3, s0 -; VI-NEXT: v_mov_b32_e32 v4, s1 -; VI-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1 -; VI-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1] -; VI-NEXT: v_mov_b32_e32 v1, s13 -; VI-NEXT: v_mov_b32_e32 v4, s7 -; VI-NEXT: s_cmp_lg_u64 vcc, 0 -; VI-NEXT: v_cndmask_b32_e64 v1, v1, v4, s[0:1] -; VI-NEXT: s_subb_u32 s0, s11, s12 -; VI-NEXT: s_cmp_ge_u32 s0, s3 -; VI-NEXT: s_cselect_b32 s1, -1, 0 -; VI-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 -; VI-NEXT: s_cmp_eq_u32 s0, s3 -; VI-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; VI-NEXT: v_mov_b32_e32 v4, s1 -; VI-NEXT: s_cselect_b64 vcc, -1, 0 -; VI-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc -; VI-NEXT: v_mov_b32_e32 v4, s6 -; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; VI-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc -; VI-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc -; VI-NEXT: s_cbranch_execnz .LBB16_3 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[6:7], s2, v3, 0 +; VI-NEXT: v_mul_hi_u32 v4, s2, v2 +; VI-NEXT: v_readfirstlane_b32 s8, v1 +; VI-NEXT: v_readfirstlane_b32 s9, v0 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[6:7], s3, v3, 0 +; VI-NEXT: v_mad_u64_u32 v[2:3], s[6:7], s3, v2, 0 +; VI-NEXT: v_readfirstlane_b32 s10, v4 +; VI-NEXT: s_add_u32 s6, s10, s9 +; VI-NEXT: s_addc_u32 s7, 0, s8 +; VI-NEXT: v_readfirstlane_b32 s10, v2 +; VI-NEXT: v_readfirstlane_b32 s9, v3 +; VI-NEXT: s_add_u32 s6, s6, s10 +; VI-NEXT: v_readfirstlane_b32 s8, v1 +; VI-NEXT: s_addc_u32 s6, s7, s9 +; VI-NEXT: s_addc_u32 s8, s8, 0 +; VI-NEXT: v_readfirstlane_b32 s7, v0 +; VI-NEXT: s_add_u32 s12, s6, s7 +; VI-NEXT: v_mov_b32_e32 v0, s12 +; VI-NEXT: v_mad_u64_u32 v[0:1], s[6:7], s4, v0, 0 +; VI-NEXT: s_addc_u32 s13, 0, s8 +; VI-NEXT: s_mul_i32 s8, s4, s13 +; VI-NEXT: v_readfirstlane_b32 s9, v1 +; VI-NEXT: s_add_i32 s8, s9, s8 +; VI-NEXT: s_mul_i32 s9, s5, s12 +; VI-NEXT: s_add_i32 s14, s8, s9 +; VI-NEXT: s_sub_i32 s10, s3, s14 +; VI-NEXT: v_readfirstlane_b32 s8, v0 +; VI-NEXT: s_sub_i32 s15, s2, s8 +; VI-NEXT: s_cselect_b64 s[8:9], 1, 0 +; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 +; VI-NEXT: s_subb_u32 s16, s10, s5 +; VI-NEXT: s_sub_i32 s17, s15, s4 +; VI-NEXT: s_cselect_b64 s[10:11], 1, 0 +; VI-NEXT: s_cmp_lg_u64 s[10:11], 0 +; VI-NEXT: s_subb_u32 s10, s16, 0 +; VI-NEXT: s_cmp_ge_u32 s10, s5 +; VI-NEXT: s_cselect_b32 s11, -1, 0 +; VI-NEXT: s_cmp_ge_u32 s17, s4 +; VI-NEXT: s_cselect_b32 s16, -1, 0 +; VI-NEXT: s_cmp_eq_u32 s10, s5 +; VI-NEXT: s_cselect_b32 s10, s16, s11 +; VI-NEXT: s_add_u32 s11, s12, 1 +; VI-NEXT: s_addc_u32 s16, s13, 0 +; VI-NEXT: s_add_u32 s17, s12, 2 +; VI-NEXT: s_addc_u32 s18, s13, 0 +; VI-NEXT: s_cmp_lg_u32 s10, 0 +; VI-NEXT: s_cselect_b32 s10, s17, s11 +; VI-NEXT: s_cselect_b32 s11, s18, s16 +; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 +; VI-NEXT: s_subb_u32 s3, s3, s14 +; VI-NEXT: s_cmp_ge_u32 s3, s5 +; VI-NEXT: s_cselect_b32 s8, -1, 0 +; VI-NEXT: s_cmp_ge_u32 s15, s4 +; VI-NEXT: s_cselect_b32 s9, -1, 0 +; VI-NEXT: s_cmp_eq_u32 s3, s5 +; VI-NEXT: s_cselect_b32 s3, s9, s8 +; VI-NEXT: s_cmp_lg_u32 s3, 0 +; VI-NEXT: s_cselect_b32 s9, s11, s13 +; VI-NEXT: s_cselect_b32 s8, s10, s12 +; VI-NEXT: s_cbranch_execnz .LBB16_4 ; VI-NEXT: .LBB16_2: -; VI-NEXT: v_cvt_f32_u32_e32 v0, s2 -; VI-NEXT: s_sub_i32 s0, 0, s2 +; VI-NEXT: v_cvt_f32_u32_e32 v0, s4 +; VI-NEXT: s_sub_i32 s3, 0, s4 ; VI-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; VI-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; VI-NEXT: v_cvt_u32_f32_e32 v0, v0 -; VI-NEXT: v_mul_lo_u32 v1, s0, v0 +; VI-NEXT: v_mul_lo_u32 v1, s3, v0 ; VI-NEXT: v_mul_hi_u32 v1, v0, v1 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1 -; VI-NEXT: v_mul_hi_u32 v0, s10, v0 -; VI-NEXT: v_readfirstlane_b32 s0, v0 -; VI-NEXT: s_mul_i32 s0, s0, s2 -; VI-NEXT: s_sub_i32 s0, s10, s0 -; VI-NEXT: s_sub_i32 s1, s0, s2 +; VI-NEXT: v_mul_hi_u32 v0, s2, v0 +; VI-NEXT: v_readfirstlane_b32 s3, v0 +; VI-NEXT: s_mul_i32 s3, s3, s4 +; VI-NEXT: s_sub_i32 s2, s2, s3 +; VI-NEXT: s_sub_i32 s3, s2, s4 ; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v0 -; VI-NEXT: s_cmp_ge_u32 s0, s2 +; VI-NEXT: s_cmp_ge_u32 s2, s4 ; VI-NEXT: s_cselect_b64 vcc, -1, 0 -; VI-NEXT: s_cselect_b32 s0, s1, s0 +; VI-NEXT: s_cselect_b32 s2, s3, s2 ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; VI-NEXT: v_add_u32_e32 v1, vcc, 1, v0 -; VI-NEXT: s_cmp_ge_u32 s0, s2 +; VI-NEXT: s_cmp_ge_u32 s2, s4 ; VI-NEXT: s_cselect_b64 vcc, -1, 0 ; VI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; VI-NEXT: v_mov_b32_e32 v1, 0 +; VI-NEXT: s_branch .LBB16_5 ; VI-NEXT: .LBB16_3: -; VI-NEXT: v_mov_b32_e32 v2, s8 -; VI-NEXT: v_mov_b32_e32 v3, s9 +; VI-NEXT: ; implicit-def: $sgpr8_sgpr9 +; VI-NEXT: s_branch .LBB16_2 +; VI-NEXT: .LBB16_4: +; VI-NEXT: v_mov_b32_e32 v0, s8 +; VI-NEXT: v_mov_b32_e32 v1, s9 +; VI-NEXT: .LBB16_5: +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: s_endpgm -; VI-NEXT: .LBB16_4: -; VI-NEXT: ; implicit-def: $vgpr0_vgpr1 -; VI-NEXT: s_branch .LBB16_2 ; ; GFX9-LABEL: sudiv64: ; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 -; GFX9-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34 +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_or_b64 s[0:1], s[10:11], s[2:3] -; GFX9-NEXT: s_mov_b32 s0, 0 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX9-NEXT: s_or_b64 s[4:5], s[2:3], s[6:7] +; GFX9-NEXT: s_mov_b32 s4, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_cbranch_scc0 .LBB16_4 ; GFX9-NEXT: ; %bb.1: -; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s3 -; GFX9-NEXT: s_sub_u32 s0, 0, s2 -; GFX9-NEXT: s_subb_u32 s1, 0, s3 +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GFX9-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GFX9-NEXT: s_sub_u32 s10, 0, s6 +; GFX9-NEXT: s_subb_u32 s11, 0, s7 ; GFX9-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GFX9-NEXT: v_rcp_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -2309,166 +2307,157 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX9-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: v_readfirstlane_b32 s6, v1 -; GFX9-NEXT: v_readfirstlane_b32 s7, v0 -; GFX9-NEXT: s_mul_i32 s12, s0, s6 -; GFX9-NEXT: s_mul_hi_u32 s14, s0, s7 -; GFX9-NEXT: s_mul_i32 s13, s1, s7 -; GFX9-NEXT: s_add_i32 s12, s14, s12 -; GFX9-NEXT: s_add_i32 s12, s12, s13 -; GFX9-NEXT: s_mul_i32 s15, s0, s7 -; GFX9-NEXT: s_mul_hi_u32 s13, s7, s12 -; GFX9-NEXT: s_mul_i32 s14, s7, s12 -; GFX9-NEXT: s_mul_hi_u32 s7, s7, s15 -; GFX9-NEXT: s_add_u32 s7, s7, s14 +; GFX9-NEXT: v_readfirstlane_b32 s12, v1 +; GFX9-NEXT: v_readfirstlane_b32 s8, v0 +; GFX9-NEXT: s_mul_i32 s9, s10, s12 +; GFX9-NEXT: s_mul_hi_u32 s14, s10, s8 +; GFX9-NEXT: s_mul_i32 s13, s11, s8 +; GFX9-NEXT: s_add_i32 s9, s14, s9 +; GFX9-NEXT: s_add_i32 s9, s9, s13 +; GFX9-NEXT: s_mul_i32 s15, s10, s8 +; GFX9-NEXT: s_mul_i32 s14, s8, s9 +; GFX9-NEXT: s_mul_hi_u32 s16, s8, s15 +; GFX9-NEXT: s_mul_hi_u32 s13, s8, s9 +; GFX9-NEXT: s_add_u32 s14, s16, s14 ; GFX9-NEXT: s_addc_u32 s13, 0, s13 -; GFX9-NEXT: s_mul_hi_u32 s16, s6, s15 -; GFX9-NEXT: s_mul_i32 s15, s6, s15 -; GFX9-NEXT: s_add_u32 s7, s7, s15 -; GFX9-NEXT: s_mul_hi_u32 s14, s6, s12 -; GFX9-NEXT: s_addc_u32 s7, s13, s16 -; GFX9-NEXT: s_addc_u32 s13, s14, 0 -; GFX9-NEXT: s_mul_i32 s12, s6, s12 -; GFX9-NEXT: s_add_u32 s7, s7, s12 -; GFX9-NEXT: s_addc_u32 s12, 0, s13 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s7, v0 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s6, s6, s12 -; GFX9-NEXT: v_readfirstlane_b32 s12, v0 -; GFX9-NEXT: s_mul_i32 s7, s0, s6 -; GFX9-NEXT: s_mul_hi_u32 s13, s0, s12 -; GFX9-NEXT: s_add_i32 s7, s13, s7 -; GFX9-NEXT: s_mul_i32 s1, s1, s12 -; GFX9-NEXT: s_add_i32 s7, s7, s1 -; GFX9-NEXT: s_mul_i32 s0, s0, s12 -; GFX9-NEXT: s_mul_hi_u32 s13, s6, s0 -; GFX9-NEXT: s_mul_i32 s14, s6, s0 -; GFX9-NEXT: s_mul_i32 s16, s12, s7 -; GFX9-NEXT: s_mul_hi_u32 s0, s12, s0 -; GFX9-NEXT: s_mul_hi_u32 s15, s12, s7 -; GFX9-NEXT: s_add_u32 s0, s0, s16 -; GFX9-NEXT: s_addc_u32 s12, 0, s15 -; GFX9-NEXT: s_add_u32 s0, s0, s14 -; GFX9-NEXT: s_mul_hi_u32 s1, s6, s7 -; GFX9-NEXT: s_addc_u32 s0, s12, s13 -; GFX9-NEXT: s_addc_u32 s1, s1, 0 -; GFX9-NEXT: s_mul_i32 s7, s6, s7 -; GFX9-NEXT: s_add_u32 s0, s0, s7 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_addc_u32 s0, s6, s1 -; GFX9-NEXT: v_readfirstlane_b32 s7, v0 -; GFX9-NEXT: s_mul_i32 s6, s10, s0 -; GFX9-NEXT: s_mul_hi_u32 s12, s10, s7 -; GFX9-NEXT: s_mul_hi_u32 s1, s10, s0 -; GFX9-NEXT: s_add_u32 s6, s12, s6 -; GFX9-NEXT: s_addc_u32 s1, 0, s1 -; GFX9-NEXT: s_mul_hi_u32 s13, s11, s7 -; GFX9-NEXT: s_mul_i32 s7, s11, s7 -; GFX9-NEXT: s_add_u32 s6, s6, s7 -; GFX9-NEXT: s_mul_hi_u32 s12, s11, s0 -; GFX9-NEXT: s_addc_u32 s1, s1, s13 -; GFX9-NEXT: s_addc_u32 s6, s12, 0 -; GFX9-NEXT: s_mul_i32 s0, s11, s0 -; GFX9-NEXT: s_add_u32 s7, s1, s0 -; GFX9-NEXT: s_addc_u32 s6, 0, s6 -; GFX9-NEXT: s_mul_i32 s0, s2, s6 -; GFX9-NEXT: s_mul_hi_u32 s1, s2, s7 -; GFX9-NEXT: s_add_i32 s0, s1, s0 -; GFX9-NEXT: s_mul_i32 s1, s3, s7 -; GFX9-NEXT: s_add_i32 s12, s0, s1 -; GFX9-NEXT: s_mul_i32 s1, s2, s7 -; GFX9-NEXT: v_mov_b32_e32 v0, s1 -; GFX9-NEXT: s_sub_i32 s0, s11, s12 -; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s10, v0 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: s_subb_u32 s13, s0, s3 -; GFX9-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s2, v0 -; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX9-NEXT: s_subb_u32 s13, s13, 0 -; GFX9-NEXT: s_cmp_ge_u32 s13, s3 -; GFX9-NEXT: s_cselect_b32 s14, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v1 -; GFX9-NEXT: s_cmp_eq_u32 s13, s3 -; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v2, s14 -; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1] -; GFX9-NEXT: s_add_u32 s0, s7, 1 -; GFX9-NEXT: s_addc_u32 s13, s6, 0 -; GFX9-NEXT: s_add_u32 s1, s7, 2 -; GFX9-NEXT: s_addc_u32 s14, s6, 0 -; GFX9-NEXT: v_mov_b32_e32 v2, s0 -; GFX9-NEXT: v_mov_b32_e32 v3, s1 -; GFX9-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1 -; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; GFX9-NEXT: v_mov_b32_e32 v1, s13 -; GFX9-NEXT: v_mov_b32_e32 v3, s14 -; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 -; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GFX9-NEXT: s_subb_u32 s0, s11, s12 -; GFX9-NEXT: s_cmp_ge_u32 s0, s3 -; GFX9-NEXT: s_cselect_b32 s1, -1, 0 -; GFX9-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 -; GFX9-NEXT: s_cmp_eq_u32 s0, s3 -; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; GFX9-NEXT: v_mov_b32_e32 v3, s1 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc -; GFX9-NEXT: v_mov_b32_e32 v3, s6 -; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX9-NEXT: v_mov_b32_e32 v0, s7 -; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc -; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: s_mul_hi_u32 s17, s12, s15 +; GFX9-NEXT: s_mul_i32 s15, s12, s15 +; GFX9-NEXT: s_add_u32 s14, s14, s15 +; GFX9-NEXT: s_mul_hi_u32 s16, s12, s9 +; GFX9-NEXT: s_addc_u32 s13, s13, s17 +; GFX9-NEXT: s_addc_u32 s14, s16, 0 +; GFX9-NEXT: s_mul_i32 s9, s12, s9 +; GFX9-NEXT: s_add_u32 s9, s13, s9 +; GFX9-NEXT: s_addc_u32 s13, 0, s14 +; GFX9-NEXT: s_add_i32 s14, s8, s9 +; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX9-NEXT: s_addc_u32 s12, s12, s13 +; GFX9-NEXT: s_mul_i32 s8, s10, s12 +; GFX9-NEXT: s_mul_hi_u32 s9, s10, s14 +; GFX9-NEXT: s_add_i32 s8, s9, s8 +; GFX9-NEXT: s_mul_i32 s11, s11, s14 +; GFX9-NEXT: s_add_i32 s8, s8, s11 +; GFX9-NEXT: s_mul_i32 s10, s10, s14 +; GFX9-NEXT: s_mul_hi_u32 s11, s12, s10 +; GFX9-NEXT: s_mul_i32 s13, s12, s10 +; GFX9-NEXT: s_mul_i32 s16, s14, s8 +; GFX9-NEXT: s_mul_hi_u32 s10, s14, s10 +; GFX9-NEXT: s_mul_hi_u32 s15, s14, s8 +; GFX9-NEXT: s_add_u32 s10, s10, s16 +; GFX9-NEXT: s_addc_u32 s15, 0, s15 +; GFX9-NEXT: s_add_u32 s10, s10, s13 +; GFX9-NEXT: s_mul_hi_u32 s9, s12, s8 +; GFX9-NEXT: s_addc_u32 s10, s15, s11 +; GFX9-NEXT: s_addc_u32 s9, s9, 0 +; GFX9-NEXT: s_mul_i32 s8, s12, s8 +; GFX9-NEXT: s_add_u32 s8, s10, s8 +; GFX9-NEXT: s_addc_u32 s10, 0, s9 +; GFX9-NEXT: s_add_i32 s14, s14, s8 +; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX9-NEXT: s_addc_u32 s8, s12, s10 +; GFX9-NEXT: s_mul_i32 s10, s2, s8 +; GFX9-NEXT: s_mul_hi_u32 s11, s2, s14 +; GFX9-NEXT: s_mul_hi_u32 s9, s2, s8 +; GFX9-NEXT: s_add_u32 s10, s11, s10 +; GFX9-NEXT: s_addc_u32 s9, 0, s9 +; GFX9-NEXT: s_mul_i32 s13, s3, s14 +; GFX9-NEXT: s_mul_hi_u32 s12, s3, s14 +; GFX9-NEXT: s_add_u32 s10, s10, s13 +; GFX9-NEXT: s_mul_hi_u32 s11, s3, s8 +; GFX9-NEXT: s_addc_u32 s9, s9, s12 +; GFX9-NEXT: s_addc_u32 s10, s11, 0 +; GFX9-NEXT: s_mul_i32 s8, s3, s8 +; GFX9-NEXT: s_add_u32 s12, s9, s8 +; GFX9-NEXT: s_addc_u32 s13, 0, s10 +; GFX9-NEXT: s_mul_i32 s8, s6, s13 +; GFX9-NEXT: s_mul_hi_u32 s9, s6, s12 +; GFX9-NEXT: s_add_i32 s8, s9, s8 +; GFX9-NEXT: s_mul_i32 s9, s7, s12 +; GFX9-NEXT: s_add_i32 s14, s8, s9 +; GFX9-NEXT: s_sub_i32 s10, s3, s14 +; GFX9-NEXT: s_mul_i32 s8, s6, s12 +; GFX9-NEXT: s_sub_i32 s15, s2, s8 +; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX9-NEXT: s_subb_u32 s16, s10, s7 +; GFX9-NEXT: s_sub_i32 s17, s15, s6 +; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GFX9-NEXT: s_subb_u32 s10, s16, 0 +; GFX9-NEXT: s_cmp_ge_u32 s10, s7 +; GFX9-NEXT: s_cselect_b32 s11, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s17, s6 +; GFX9-NEXT: s_cselect_b32 s16, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s10, s7 +; GFX9-NEXT: s_cselect_b32 s10, s16, s11 +; GFX9-NEXT: s_add_u32 s11, s12, 1 +; GFX9-NEXT: s_addc_u32 s16, s13, 0 +; GFX9-NEXT: s_add_u32 s17, s12, 2 +; GFX9-NEXT: s_addc_u32 s18, s13, 0 +; GFX9-NEXT: s_cmp_lg_u32 s10, 0 +; GFX9-NEXT: s_cselect_b32 s10, s17, s11 +; GFX9-NEXT: s_cselect_b32 s11, s18, s16 +; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX9-NEXT: s_subb_u32 s3, s3, s14 +; GFX9-NEXT: s_cmp_ge_u32 s3, s7 +; GFX9-NEXT: s_cselect_b32 s8, -1, 0 +; GFX9-NEXT: s_cmp_ge_u32 s15, s6 +; GFX9-NEXT: s_cselect_b32 s9, -1, 0 +; GFX9-NEXT: s_cmp_eq_u32 s3, s7 +; GFX9-NEXT: s_cselect_b32 s3, s9, s8 +; GFX9-NEXT: s_cmp_lg_u32 s3, 0 +; GFX9-NEXT: s_cselect_b32 s9, s11, s13 +; GFX9-NEXT: s_cselect_b32 s8, s10, s12 ; GFX9-NEXT: s_cbranch_execnz .LBB16_3 ; GFX9-NEXT: .LBB16_2: -; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX9-NEXT: s_sub_i32 s0, 0, s2 -; GFX9-NEXT: s_mov_b32 s1, 0 +; GFX9-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GFX9-NEXT: s_sub_i32 s3, 0, s6 +; GFX9-NEXT: s_mov_b32 s9, 0 ; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX9-NEXT: v_readfirstlane_b32 s3, v0 -; GFX9-NEXT: s_mul_i32 s0, s0, s3 -; GFX9-NEXT: s_mul_hi_u32 s0, s3, s0 -; GFX9-NEXT: s_add_i32 s3, s3, s0 -; GFX9-NEXT: s_mul_hi_u32 s0, s10, s3 -; GFX9-NEXT: s_mul_i32 s4, s0, s2 -; GFX9-NEXT: s_sub_i32 s4, s10, s4 -; GFX9-NEXT: s_add_i32 s3, s0, 1 -; GFX9-NEXT: s_sub_i32 s5, s4, s2 -; GFX9-NEXT: s_cmp_ge_u32 s4, s2 -; GFX9-NEXT: s_cselect_b32 s0, s3, s0 -; GFX9-NEXT: s_cselect_b32 s4, s5, s4 -; GFX9-NEXT: s_add_i32 s3, s0, 1 -; GFX9-NEXT: s_cmp_ge_u32 s4, s2 -; GFX9-NEXT: s_cselect_b32 s0, s3, s0 -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-NEXT: v_readfirstlane_b32 s4, v0 +; GFX9-NEXT: s_mul_i32 s3, s3, s4 +; GFX9-NEXT: s_mul_hi_u32 s3, s4, s3 +; GFX9-NEXT: s_add_i32 s4, s4, s3 +; GFX9-NEXT: s_mul_hi_u32 s3, s2, s4 +; GFX9-NEXT: s_mul_i32 s5, s3, s6 +; GFX9-NEXT: s_sub_i32 s2, s2, s5 +; GFX9-NEXT: s_add_i32 s4, s3, 1 +; GFX9-NEXT: s_sub_i32 s5, s2, s6 +; GFX9-NEXT: s_cmp_ge_u32 s2, s6 +; GFX9-NEXT: s_cselect_b32 s3, s4, s3 +; GFX9-NEXT: s_cselect_b32 s2, s5, s2 +; GFX9-NEXT: s_add_i32 s4, s3, 1 +; GFX9-NEXT: s_cmp_ge_u32 s2, s6 +; GFX9-NEXT: s_cselect_b32 s8, s4, s3 ; GFX9-NEXT: .LBB16_3: +; GFX9-NEXT: v_mov_b32_e32 v0, s8 ; GFX9-NEXT: v_mov_b32_e32 v2, 0 -; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] +; GFX9-NEXT: v_mov_b32_e32 v1, s9 +; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX9-NEXT: s_endpgm ; GFX9-NEXT: .LBB16_4: -; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX9-NEXT: ; implicit-def: $sgpr8_sgpr9 ; GFX9-NEXT: s_branch .LBB16_2 ; ; GFX1010-LABEL: sudiv64: ; GFX1010: ; %bb.0: ; GFX1010-NEXT: s_clause 0x1 -; GFX1010-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 -; GFX1010-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34 +; GFX1010-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX1010-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34 ; GFX1010-NEXT: s_waitcnt lgkmcnt(0) -; GFX1010-NEXT: s_or_b64 s[4:5], s[10:11], s[2:3] +; GFX1010-NEXT: s_or_b64 s[4:5], s[2:3], s[6:7] ; GFX1010-NEXT: s_mov_b32 s4, 0 ; GFX1010-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX1010-NEXT: s_cbranch_scc0 .LBB16_4 ; GFX1010-NEXT: ; %bb.1: -; GFX1010-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX1010-NEXT: v_cvt_f32_u32_e32 v1, s3 -; GFX1010-NEXT: s_sub_u32 s5, 0, s2 -; GFX1010-NEXT: s_subb_u32 s6, 0, s3 +; GFX1010-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GFX1010-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GFX1010-NEXT: s_sub_u32 s9, 0, s6 +; GFX1010-NEXT: s_subb_u32 s10, 0, s7 ; GFX1010-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GFX1010-NEXT: v_rcp_f32_e32 v0, v0 ; GFX1010-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -2477,160 +2466,158 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1010-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 ; GFX1010-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX1010-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1010-NEXT: v_readfirstlane_b32 s0, v1 -; GFX1010-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1010-NEXT: s_mul_i32 s7, s5, s0 -; GFX1010-NEXT: s_mul_hi_u32 s13, s5, s1 -; GFX1010-NEXT: s_mul_i32 s12, s6, s1 -; GFX1010-NEXT: s_add_i32 s7, s13, s7 -; GFX1010-NEXT: s_mul_i32 s14, s5, s1 -; GFX1010-NEXT: s_add_i32 s7, s7, s12 -; GFX1010-NEXT: s_mul_hi_u32 s13, s1, s14 -; GFX1010-NEXT: s_mul_hi_u32 s15, s0, s14 -; GFX1010-NEXT: s_mul_i32 s12, s0, s14 -; GFX1010-NEXT: s_mul_hi_u32 s14, s1, s7 -; GFX1010-NEXT: s_mul_i32 s1, s1, s7 -; GFX1010-NEXT: s_mul_hi_u32 s16, s0, s7 -; GFX1010-NEXT: s_add_u32 s1, s13, s1 -; GFX1010-NEXT: s_addc_u32 s13, 0, s14 -; GFX1010-NEXT: s_add_u32 s1, s1, s12 -; GFX1010-NEXT: s_mul_i32 s7, s0, s7 -; GFX1010-NEXT: s_addc_u32 s1, s13, s15 -; GFX1010-NEXT: s_addc_u32 s12, s16, 0 -; GFX1010-NEXT: s_add_u32 s1, s1, s7 -; GFX1010-NEXT: s_addc_u32 s7, 0, s12 -; GFX1010-NEXT: v_add_co_u32 v0, s1, v0, s1 -; GFX1010-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1010-NEXT: s_addc_u32 s0, s0, s7 -; GFX1010-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1010-NEXT: s_mul_i32 s7, s5, s0 -; GFX1010-NEXT: s_mul_hi_u32 s12, s5, s1 -; GFX1010-NEXT: s_mul_i32 s6, s6, s1 -; GFX1010-NEXT: s_add_i32 s7, s12, s7 -; GFX1010-NEXT: s_mul_i32 s5, s5, s1 -; GFX1010-NEXT: s_add_i32 s7, s7, s6 -; GFX1010-NEXT: s_mul_hi_u32 s12, s0, s5 -; GFX1010-NEXT: s_mul_i32 s13, s0, s5 -; GFX1010-NEXT: s_mul_hi_u32 s5, s1, s5 -; GFX1010-NEXT: s_mul_hi_u32 s14, s1, s7 -; GFX1010-NEXT: s_mul_i32 s1, s1, s7 -; GFX1010-NEXT: s_mul_hi_u32 s6, s0, s7 -; GFX1010-NEXT: s_add_u32 s1, s5, s1 -; GFX1010-NEXT: s_addc_u32 s5, 0, s14 -; GFX1010-NEXT: s_add_u32 s1, s1, s13 -; GFX1010-NEXT: s_mul_i32 s7, s0, s7 -; GFX1010-NEXT: s_addc_u32 s1, s5, s12 -; GFX1010-NEXT: s_addc_u32 s5, s6, 0 -; GFX1010-NEXT: s_add_u32 s1, s1, s7 -; GFX1010-NEXT: s_addc_u32 s5, 0, s5 -; GFX1010-NEXT: v_add_co_u32 v0, s1, v0, s1 -; GFX1010-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1010-NEXT: s_addc_u32 s0, s0, s5 -; GFX1010-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1010-NEXT: s_mul_i32 s6, s10, s0 -; GFX1010-NEXT: s_mul_hi_u32 s5, s10, s0 -; GFX1010-NEXT: s_mul_hi_u32 s7, s11, s0 -; GFX1010-NEXT: s_mul_i32 s0, s11, s0 -; GFX1010-NEXT: s_mul_hi_u32 s12, s10, s1 -; GFX1010-NEXT: s_mul_hi_u32 s13, s11, s1 -; GFX1010-NEXT: s_mul_i32 s1, s11, s1 -; GFX1010-NEXT: s_add_u32 s6, s12, s6 -; GFX1010-NEXT: s_addc_u32 s5, 0, s5 -; GFX1010-NEXT: s_add_u32 s1, s6, s1 -; GFX1010-NEXT: s_addc_u32 s1, s5, s13 -; GFX1010-NEXT: s_addc_u32 s5, s7, 0 -; GFX1010-NEXT: s_add_u32 s1, s1, s0 -; GFX1010-NEXT: s_addc_u32 s5, 0, s5 -; GFX1010-NEXT: s_mul_hi_u32 s0, s2, s1 -; GFX1010-NEXT: s_mul_i32 s7, s2, s5 -; GFX1010-NEXT: s_mul_i32 s12, s2, s1 -; GFX1010-NEXT: s_add_i32 s0, s0, s7 -; GFX1010-NEXT: v_sub_co_u32 v0, s7, s10, s12 -; GFX1010-NEXT: s_mul_i32 s6, s3, s1 -; GFX1010-NEXT: s_add_i32 s0, s0, s6 -; GFX1010-NEXT: v_sub_co_u32 v1, s12, v0, s2 -; GFX1010-NEXT: s_sub_i32 s6, s11, s0 -; GFX1010-NEXT: s_cmp_lg_u32 s7, 0 -; GFX1010-NEXT: s_subb_u32 s6, s6, s3 +; GFX1010-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1010-NEXT: v_readfirstlane_b32 s8, v0 +; GFX1010-NEXT: s_mul_i32 s11, s9, s5 +; GFX1010-NEXT: s_mul_hi_u32 s13, s9, s8 +; GFX1010-NEXT: s_mul_i32 s12, s10, s8 +; GFX1010-NEXT: s_add_i32 s11, s13, s11 +; GFX1010-NEXT: s_mul_i32 s14, s9, s8 +; GFX1010-NEXT: s_add_i32 s11, s11, s12 +; GFX1010-NEXT: s_mul_hi_u32 s13, s8, s14 +; GFX1010-NEXT: s_mul_i32 s16, s8, s11 +; GFX1010-NEXT: s_mul_hi_u32 s15, s5, s14 +; GFX1010-NEXT: s_mul_i32 s12, s5, s14 +; GFX1010-NEXT: s_mul_hi_u32 s14, s8, s11 +; GFX1010-NEXT: s_add_u32 s13, s13, s16 +; GFX1010-NEXT: s_addc_u32 s14, 0, s14 +; GFX1010-NEXT: s_mul_hi_u32 s17, s5, s11 +; GFX1010-NEXT: s_add_u32 s12, s13, s12 +; GFX1010-NEXT: s_mul_i32 s11, s5, s11 +; GFX1010-NEXT: s_addc_u32 s12, s14, s15 +; GFX1010-NEXT: s_addc_u32 s13, s17, 0 +; GFX1010-NEXT: s_add_u32 s11, s12, s11 +; GFX1010-NEXT: s_addc_u32 s12, 0, s13 +; GFX1010-NEXT: s_add_i32 s8, s8, s11 +; GFX1010-NEXT: s_cselect_b32 s11, 1, 0 +; GFX1010-NEXT: s_mul_hi_u32 s13, s9, s8 +; GFX1010-NEXT: s_cmp_lg_u32 s11, 0 +; GFX1010-NEXT: s_mul_i32 s11, s9, s8 +; GFX1010-NEXT: s_addc_u32 s5, s5, s12 +; GFX1010-NEXT: s_mul_i32 s10, s10, s8 +; GFX1010-NEXT: s_mul_i32 s9, s9, s5 +; GFX1010-NEXT: s_mul_hi_u32 s12, s8, s11 +; GFX1010-NEXT: s_add_i32 s9, s13, s9 +; GFX1010-NEXT: s_mul_hi_u32 s13, s5, s11 +; GFX1010-NEXT: s_add_i32 s9, s9, s10 +; GFX1010-NEXT: s_mul_i32 s10, s5, s11 +; GFX1010-NEXT: s_mul_i32 s15, s8, s9 +; GFX1010-NEXT: s_mul_hi_u32 s14, s8, s9 +; GFX1010-NEXT: s_add_u32 s12, s12, s15 +; GFX1010-NEXT: s_addc_u32 s14, 0, s14 +; GFX1010-NEXT: s_mul_hi_u32 s11, s5, s9 +; GFX1010-NEXT: s_add_u32 s10, s12, s10 +; GFX1010-NEXT: s_mul_i32 s9, s5, s9 +; GFX1010-NEXT: s_addc_u32 s10, s14, s13 +; GFX1010-NEXT: s_addc_u32 s11, s11, 0 +; GFX1010-NEXT: s_add_u32 s9, s10, s9 +; GFX1010-NEXT: s_addc_u32 s10, 0, s11 +; GFX1010-NEXT: s_add_i32 s8, s8, s9 +; GFX1010-NEXT: s_cselect_b32 s9, 1, 0 +; GFX1010-NEXT: s_mul_hi_u32 s11, s2, s8 +; GFX1010-NEXT: s_cmp_lg_u32 s9, 0 +; GFX1010-NEXT: s_mul_hi_u32 s9, s3, s8 +; GFX1010-NEXT: s_addc_u32 s5, s5, s10 +; GFX1010-NEXT: s_mul_i32 s8, s3, s8 +; GFX1010-NEXT: s_mul_i32 s12, s2, s5 +; GFX1010-NEXT: s_mul_hi_u32 s10, s2, s5 +; GFX1010-NEXT: s_add_u32 s11, s11, s12 +; GFX1010-NEXT: s_addc_u32 s10, 0, s10 +; GFX1010-NEXT: s_mul_hi_u32 s13, s3, s5 +; GFX1010-NEXT: s_add_u32 s8, s11, s8 +; GFX1010-NEXT: s_mul_i32 s5, s3, s5 +; GFX1010-NEXT: s_addc_u32 s8, s10, s9 +; GFX1010-NEXT: s_addc_u32 s9, s13, 0 +; GFX1010-NEXT: s_add_u32 s5, s8, s5 +; GFX1010-NEXT: s_addc_u32 s8, 0, s9 +; GFX1010-NEXT: s_mul_hi_u32 s9, s6, s5 +; GFX1010-NEXT: s_mul_i32 s10, s6, s8 +; GFX1010-NEXT: s_mul_i32 s11, s7, s5 +; GFX1010-NEXT: s_add_i32 s9, s9, s10 +; GFX1010-NEXT: s_mul_i32 s10, s6, s5 +; GFX1010-NEXT: s_add_i32 s9, s9, s11 +; GFX1010-NEXT: s_sub_i32 s11, s3, s9 +; GFX1010-NEXT: s_sub_i32 s10, s2, s10 +; GFX1010-NEXT: s_cselect_b32 s12, 1, 0 ; GFX1010-NEXT: s_cmp_lg_u32 s12, 0 -; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1 -; GFX1010-NEXT: s_subb_u32 s6, s6, 0 -; GFX1010-NEXT: s_cmp_ge_u32 s6, s3 -; GFX1010-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo -; GFX1010-NEXT: s_cselect_b32 s12, -1, 0 -; GFX1010-NEXT: s_cmp_eq_u32 s6, s3 -; GFX1010-NEXT: s_cselect_b32 vcc_lo, -1, 0 -; GFX1010-NEXT: s_add_u32 s6, s1, 1 -; GFX1010-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo -; GFX1010-NEXT: s_addc_u32 s12, s5, 0 -; GFX1010-NEXT: s_add_u32 s13, s1, 2 -; GFX1010-NEXT: s_addc_u32 s14, s5, 0 -; GFX1010-NEXT: s_cmp_lg_u32 s7, 0 -; GFX1010-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v0 -; GFX1010-NEXT: s_subb_u32 s0, s11, s0 -; GFX1010-NEXT: v_mov_b32_e32 v2, s13 -; GFX1010-NEXT: s_cmp_ge_u32 s0, s3 -; GFX1010-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo -; GFX1010-NEXT: s_cselect_b32 s7, -1, 0 -; GFX1010-NEXT: s_cmp_eq_u32 s0, s3 -; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX1010-NEXT: s_cselect_b32 s0, -1, 0 -; GFX1010-NEXT: v_mov_b32_e32 v1, s14 -; GFX1010-NEXT: v_cndmask_b32_e64 v0, s7, v0, s0 -; GFX1010-NEXT: v_cndmask_b32_e32 v2, s6, v2, vcc_lo -; GFX1010-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo -; GFX1010-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX1010-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo -; GFX1010-NEXT: v_cndmask_b32_e32 v0, s1, v2, vcc_lo +; GFX1010-NEXT: s_subb_u32 s11, s11, s7 +; GFX1010-NEXT: s_sub_i32 s13, s10, s6 +; GFX1010-NEXT: s_cselect_b32 s14, 1, 0 +; GFX1010-NEXT: s_cmp_lg_u32 s14, 0 +; GFX1010-NEXT: s_subb_u32 s11, s11, 0 +; GFX1010-NEXT: s_cmp_ge_u32 s11, s7 +; GFX1010-NEXT: s_cselect_b32 s14, -1, 0 +; GFX1010-NEXT: s_cmp_ge_u32 s13, s6 +; GFX1010-NEXT: s_cselect_b32 s13, -1, 0 +; GFX1010-NEXT: s_cmp_eq_u32 s11, s7 +; GFX1010-NEXT: s_cselect_b32 s11, s13, s14 +; GFX1010-NEXT: s_add_u32 s13, s5, 1 +; GFX1010-NEXT: s_addc_u32 s14, s8, 0 +; GFX1010-NEXT: s_add_u32 s15, s5, 2 +; GFX1010-NEXT: s_addc_u32 s16, s8, 0 +; GFX1010-NEXT: s_cmp_lg_u32 s11, 0 +; GFX1010-NEXT: s_cselect_b32 s11, s15, s13 +; GFX1010-NEXT: s_cselect_b32 s13, s16, s14 +; GFX1010-NEXT: s_cmp_lg_u32 s12, 0 +; GFX1010-NEXT: s_subb_u32 s3, s3, s9 +; GFX1010-NEXT: s_cmp_ge_u32 s3, s7 +; GFX1010-NEXT: s_cselect_b32 s9, -1, 0 +; GFX1010-NEXT: s_cmp_ge_u32 s10, s6 +; GFX1010-NEXT: s_cselect_b32 s10, -1, 0 +; GFX1010-NEXT: s_cmp_eq_u32 s3, s7 +; GFX1010-NEXT: s_cselect_b32 s3, s10, s9 +; GFX1010-NEXT: s_cmp_lg_u32 s3, 0 +; GFX1010-NEXT: s_cselect_b32 s9, s13, s8 +; GFX1010-NEXT: s_cselect_b32 s8, s11, s5 ; GFX1010-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4 ; GFX1010-NEXT: s_cbranch_vccnz .LBB16_3 ; GFX1010-NEXT: .LBB16_2: -; GFX1010-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX1010-NEXT: s_sub_i32 s1, 0, s2 +; GFX1010-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GFX1010-NEXT: s_sub_i32 s4, 0, s6 +; GFX1010-NEXT: s_mov_b32 s9, 0 ; GFX1010-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX1010-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX1010-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1010-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1010-NEXT: s_mul_i32 s1, s1, s0 -; GFX1010-NEXT: s_mul_hi_u32 s1, s0, s1 -; GFX1010-NEXT: s_add_i32 s0, s0, s1 -; GFX1010-NEXT: s_mul_hi_u32 s0, s10, s0 -; GFX1010-NEXT: s_mul_i32 s1, s0, s2 -; GFX1010-NEXT: s_add_i32 s3, s0, 1 -; GFX1010-NEXT: s_sub_i32 s1, s10, s1 -; GFX1010-NEXT: s_sub_i32 s4, s1, s2 -; GFX1010-NEXT: s_cmp_ge_u32 s1, s2 -; GFX1010-NEXT: s_cselect_b32 s0, s3, s0 -; GFX1010-NEXT: s_cselect_b32 s1, s4, s1 -; GFX1010-NEXT: s_add_i32 s3, s0, 1 -; GFX1010-NEXT: s_cmp_ge_u32 s1, s2 -; GFX1010-NEXT: s_mov_b32 s1, 0 -; GFX1010-NEXT: s_cselect_b32 s0, s3, s0 -; GFX1010-NEXT: v_mov_b32_e32 v0, s0 -; GFX1010-NEXT: v_mov_b32_e32 v1, s1 +; GFX1010-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1010-NEXT: s_mul_i32 s4, s4, s3 +; GFX1010-NEXT: s_mul_hi_u32 s4, s3, s4 +; GFX1010-NEXT: s_add_i32 s3, s3, s4 +; GFX1010-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX1010-NEXT: s_mul_i32 s4, s3, s6 +; GFX1010-NEXT: s_sub_i32 s2, s2, s4 +; GFX1010-NEXT: s_add_i32 s4, s3, 1 +; GFX1010-NEXT: s_sub_i32 s5, s2, s6 +; GFX1010-NEXT: s_cmp_ge_u32 s2, s6 +; GFX1010-NEXT: s_cselect_b32 s3, s4, s3 +; GFX1010-NEXT: s_cselect_b32 s2, s5, s2 +; GFX1010-NEXT: s_add_i32 s4, s3, 1 +; GFX1010-NEXT: s_cmp_ge_u32 s2, s6 +; GFX1010-NEXT: s_cselect_b32 s8, s4, s3 ; GFX1010-NEXT: .LBB16_3: +; GFX1010-NEXT: v_mov_b32_e32 v0, s8 ; GFX1010-NEXT: v_mov_b32_e32 v2, 0 -; GFX1010-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] +; GFX1010-NEXT: v_mov_b32_e32 v1, s9 +; GFX1010-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: .LBB16_4: -; GFX1010-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1010-NEXT: ; implicit-def: $sgpr8_sgpr9 ; GFX1010-NEXT: s_branch .LBB16_2 ; ; GFX1030W32-LABEL: sudiv64: ; GFX1030W32: ; %bb.0: ; GFX1030W32-NEXT: s_clause 0x1 -; GFX1030W32-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 -; GFX1030W32-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34 +; GFX1030W32-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX1030W32-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 ; GFX1030W32-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030W32-NEXT: s_or_b64 s[4:5], s[10:11], s[2:3] -; GFX1030W32-NEXT: s_mov_b32 s4, 0 -; GFX1030W32-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX1030W32-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5] +; GFX1030W32-NEXT: s_mov_b32 s6, 0 +; GFX1030W32-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX1030W32-NEXT: s_cbranch_scc0 .LBB16_4 ; GFX1030W32-NEXT: ; %bb.1: -; GFX1030W32-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX1030W32-NEXT: v_cvt_f32_u32_e32 v1, s3 -; GFX1030W32-NEXT: s_sub_u32 s5, 0, s2 -; GFX1030W32-NEXT: s_subb_u32 s6, 0, s3 +; GFX1030W32-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GFX1030W32-NEXT: v_cvt_f32_u32_e32 v1, s5 +; GFX1030W32-NEXT: s_sub_u32 s9, 0, s4 +; GFX1030W32-NEXT: s_subb_u32 s10, 0, s5 ; GFX1030W32-NEXT: v_fmamk_f32 v0, v1, 0x4f800000, v0 ; GFX1030W32-NEXT: v_rcp_f32_e32 v0, v0 ; GFX1030W32-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -2639,160 +2626,158 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W32-NEXT: v_fmamk_f32 v0, v1, 0xcf800000, v0 ; GFX1030W32-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX1030W32-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1030W32-NEXT: v_readfirstlane_b32 s0, v1 -; GFX1030W32-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1030W32-NEXT: s_mul_i32 s7, s5, s0 -; GFX1030W32-NEXT: s_mul_hi_u32 s13, s5, s1 -; GFX1030W32-NEXT: s_mul_i32 s12, s6, s1 -; GFX1030W32-NEXT: s_add_i32 s7, s13, s7 -; GFX1030W32-NEXT: s_mul_i32 s14, s5, s1 -; GFX1030W32-NEXT: s_add_i32 s7, s7, s12 -; GFX1030W32-NEXT: s_mul_hi_u32 s13, s1, s14 -; GFX1030W32-NEXT: s_mul_hi_u32 s15, s0, s14 -; GFX1030W32-NEXT: s_mul_i32 s12, s0, s14 -; GFX1030W32-NEXT: s_mul_hi_u32 s14, s1, s7 -; GFX1030W32-NEXT: s_mul_i32 s1, s1, s7 -; GFX1030W32-NEXT: s_mul_hi_u32 s16, s0, s7 -; GFX1030W32-NEXT: s_add_u32 s1, s13, s1 -; GFX1030W32-NEXT: s_addc_u32 s13, 0, s14 -; GFX1030W32-NEXT: s_add_u32 s1, s1, s12 -; GFX1030W32-NEXT: s_mul_i32 s7, s0, s7 -; GFX1030W32-NEXT: s_addc_u32 s1, s13, s15 -; GFX1030W32-NEXT: s_addc_u32 s12, s16, 0 -; GFX1030W32-NEXT: s_add_u32 s1, s1, s7 -; GFX1030W32-NEXT: s_addc_u32 s7, 0, s12 -; GFX1030W32-NEXT: v_add_co_u32 v0, s1, v0, s1 -; GFX1030W32-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1030W32-NEXT: s_addc_u32 s0, s0, s7 -; GFX1030W32-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1030W32-NEXT: s_mul_i32 s7, s5, s0 -; GFX1030W32-NEXT: s_mul_hi_u32 s12, s5, s1 -; GFX1030W32-NEXT: s_mul_i32 s6, s6, s1 -; GFX1030W32-NEXT: s_add_i32 s7, s12, s7 -; GFX1030W32-NEXT: s_mul_i32 s5, s5, s1 -; GFX1030W32-NEXT: s_add_i32 s7, s7, s6 -; GFX1030W32-NEXT: s_mul_hi_u32 s12, s0, s5 -; GFX1030W32-NEXT: s_mul_i32 s13, s0, s5 -; GFX1030W32-NEXT: s_mul_hi_u32 s5, s1, s5 -; GFX1030W32-NEXT: s_mul_hi_u32 s14, s1, s7 -; GFX1030W32-NEXT: s_mul_i32 s1, s1, s7 -; GFX1030W32-NEXT: s_mul_hi_u32 s6, s0, s7 -; GFX1030W32-NEXT: s_add_u32 s1, s5, s1 -; GFX1030W32-NEXT: s_addc_u32 s5, 0, s14 -; GFX1030W32-NEXT: s_add_u32 s1, s1, s13 -; GFX1030W32-NEXT: s_mul_i32 s7, s0, s7 -; GFX1030W32-NEXT: s_addc_u32 s1, s5, s12 -; GFX1030W32-NEXT: s_addc_u32 s5, s6, 0 -; GFX1030W32-NEXT: s_add_u32 s1, s1, s7 -; GFX1030W32-NEXT: s_addc_u32 s5, 0, s5 -; GFX1030W32-NEXT: v_add_co_u32 v0, s1, v0, s1 -; GFX1030W32-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1030W32-NEXT: s_addc_u32 s0, s0, s5 -; GFX1030W32-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1030W32-NEXT: s_mul_i32 s6, s10, s0 -; GFX1030W32-NEXT: s_mul_hi_u32 s5, s10, s0 -; GFX1030W32-NEXT: s_mul_hi_u32 s7, s11, s0 -; GFX1030W32-NEXT: s_mul_i32 s0, s11, s0 -; GFX1030W32-NEXT: s_mul_hi_u32 s12, s10, s1 -; GFX1030W32-NEXT: s_mul_hi_u32 s13, s11, s1 -; GFX1030W32-NEXT: s_mul_i32 s1, s11, s1 -; GFX1030W32-NEXT: s_add_u32 s6, s12, s6 -; GFX1030W32-NEXT: s_addc_u32 s5, 0, s5 -; GFX1030W32-NEXT: s_add_u32 s1, s6, s1 -; GFX1030W32-NEXT: s_addc_u32 s1, s5, s13 -; GFX1030W32-NEXT: s_addc_u32 s5, s7, 0 -; GFX1030W32-NEXT: s_add_u32 s1, s1, s0 -; GFX1030W32-NEXT: s_addc_u32 s5, 0, s5 -; GFX1030W32-NEXT: s_mul_hi_u32 s0, s2, s1 -; GFX1030W32-NEXT: s_mul_i32 s7, s2, s5 -; GFX1030W32-NEXT: s_mul_i32 s12, s2, s1 -; GFX1030W32-NEXT: s_add_i32 s0, s0, s7 -; GFX1030W32-NEXT: v_sub_co_u32 v0, s7, s10, s12 -; GFX1030W32-NEXT: s_mul_i32 s6, s3, s1 -; GFX1030W32-NEXT: s_add_i32 s0, s0, s6 -; GFX1030W32-NEXT: v_sub_co_u32 v1, s12, v0, s2 -; GFX1030W32-NEXT: s_sub_i32 s6, s11, s0 -; GFX1030W32-NEXT: s_cmp_lg_u32 s7, 0 -; GFX1030W32-NEXT: s_subb_u32 s6, s6, s3 +; GFX1030W32-NEXT: v_readfirstlane_b32 s7, v1 +; GFX1030W32-NEXT: v_readfirstlane_b32 s8, v0 +; GFX1030W32-NEXT: s_mul_i32 s11, s9, s7 +; GFX1030W32-NEXT: s_mul_hi_u32 s13, s9, s8 +; GFX1030W32-NEXT: s_mul_i32 s12, s10, s8 +; GFX1030W32-NEXT: s_add_i32 s11, s13, s11 +; GFX1030W32-NEXT: s_mul_i32 s14, s9, s8 +; GFX1030W32-NEXT: s_add_i32 s11, s11, s12 +; GFX1030W32-NEXT: s_mul_hi_u32 s13, s8, s14 +; GFX1030W32-NEXT: s_mul_i32 s16, s8, s11 +; GFX1030W32-NEXT: s_mul_hi_u32 s15, s7, s14 +; GFX1030W32-NEXT: s_mul_i32 s12, s7, s14 +; GFX1030W32-NEXT: s_mul_hi_u32 s14, s8, s11 +; GFX1030W32-NEXT: s_add_u32 s13, s13, s16 +; GFX1030W32-NEXT: s_addc_u32 s14, 0, s14 +; GFX1030W32-NEXT: s_mul_hi_u32 s17, s7, s11 +; GFX1030W32-NEXT: s_add_u32 s12, s13, s12 +; GFX1030W32-NEXT: s_mul_i32 s11, s7, s11 +; GFX1030W32-NEXT: s_addc_u32 s12, s14, s15 +; GFX1030W32-NEXT: s_addc_u32 s13, s17, 0 +; GFX1030W32-NEXT: s_add_u32 s11, s12, s11 +; GFX1030W32-NEXT: s_addc_u32 s12, 0, s13 +; GFX1030W32-NEXT: s_add_i32 s8, s8, s11 +; GFX1030W32-NEXT: s_cselect_b32 s11, 1, 0 +; GFX1030W32-NEXT: s_mul_hi_u32 s13, s9, s8 +; GFX1030W32-NEXT: s_cmp_lg_u32 s11, 0 +; GFX1030W32-NEXT: s_mul_i32 s11, s9, s8 +; GFX1030W32-NEXT: s_addc_u32 s7, s7, s12 +; GFX1030W32-NEXT: s_mul_i32 s10, s10, s8 +; GFX1030W32-NEXT: s_mul_i32 s9, s9, s7 +; GFX1030W32-NEXT: s_mul_hi_u32 s12, s8, s11 +; GFX1030W32-NEXT: s_add_i32 s9, s13, s9 +; GFX1030W32-NEXT: s_mul_hi_u32 s13, s7, s11 +; GFX1030W32-NEXT: s_add_i32 s9, s9, s10 +; GFX1030W32-NEXT: s_mul_i32 s10, s7, s11 +; GFX1030W32-NEXT: s_mul_i32 s15, s8, s9 +; GFX1030W32-NEXT: s_mul_hi_u32 s14, s8, s9 +; GFX1030W32-NEXT: s_add_u32 s12, s12, s15 +; GFX1030W32-NEXT: s_addc_u32 s14, 0, s14 +; GFX1030W32-NEXT: s_mul_hi_u32 s11, s7, s9 +; GFX1030W32-NEXT: s_add_u32 s10, s12, s10 +; GFX1030W32-NEXT: s_mul_i32 s9, s7, s9 +; GFX1030W32-NEXT: s_addc_u32 s10, s14, s13 +; GFX1030W32-NEXT: s_addc_u32 s11, s11, 0 +; GFX1030W32-NEXT: s_add_u32 s9, s10, s9 +; GFX1030W32-NEXT: s_addc_u32 s10, 0, s11 +; GFX1030W32-NEXT: s_add_i32 s8, s8, s9 +; GFX1030W32-NEXT: s_cselect_b32 s9, 1, 0 +; GFX1030W32-NEXT: s_mul_hi_u32 s11, s2, s8 +; GFX1030W32-NEXT: s_cmp_lg_u32 s9, 0 +; GFX1030W32-NEXT: s_mul_hi_u32 s9, s3, s8 +; GFX1030W32-NEXT: s_addc_u32 s7, s7, s10 +; GFX1030W32-NEXT: s_mul_i32 s8, s3, s8 +; GFX1030W32-NEXT: s_mul_i32 s12, s2, s7 +; GFX1030W32-NEXT: s_mul_hi_u32 s10, s2, s7 +; GFX1030W32-NEXT: s_add_u32 s11, s11, s12 +; GFX1030W32-NEXT: s_addc_u32 s10, 0, s10 +; GFX1030W32-NEXT: s_mul_hi_u32 s13, s3, s7 +; GFX1030W32-NEXT: s_add_u32 s8, s11, s8 +; GFX1030W32-NEXT: s_mul_i32 s7, s3, s7 +; GFX1030W32-NEXT: s_addc_u32 s8, s10, s9 +; GFX1030W32-NEXT: s_addc_u32 s9, s13, 0 +; GFX1030W32-NEXT: s_add_u32 s7, s8, s7 +; GFX1030W32-NEXT: s_addc_u32 s8, 0, s9 +; GFX1030W32-NEXT: s_mul_hi_u32 s9, s4, s7 +; GFX1030W32-NEXT: s_mul_i32 s10, s4, s8 +; GFX1030W32-NEXT: s_mul_i32 s11, s5, s7 +; GFX1030W32-NEXT: s_add_i32 s9, s9, s10 +; GFX1030W32-NEXT: s_mul_i32 s10, s4, s7 +; GFX1030W32-NEXT: s_add_i32 s9, s9, s11 +; GFX1030W32-NEXT: s_sub_i32 s11, s3, s9 +; GFX1030W32-NEXT: s_sub_i32 s10, s2, s10 +; GFX1030W32-NEXT: s_cselect_b32 s12, 1, 0 +; GFX1030W32-NEXT: s_cmp_lg_u32 s12, 0 +; GFX1030W32-NEXT: s_subb_u32 s11, s11, s5 +; GFX1030W32-NEXT: s_sub_i32 s13, s10, s4 +; GFX1030W32-NEXT: s_cselect_b32 s14, 1, 0 +; GFX1030W32-NEXT: s_cmp_lg_u32 s14, 0 +; GFX1030W32-NEXT: s_subb_u32 s11, s11, 0 +; GFX1030W32-NEXT: s_cmp_ge_u32 s11, s5 +; GFX1030W32-NEXT: s_cselect_b32 s14, -1, 0 +; GFX1030W32-NEXT: s_cmp_ge_u32 s13, s4 +; GFX1030W32-NEXT: s_cselect_b32 s13, -1, 0 +; GFX1030W32-NEXT: s_cmp_eq_u32 s11, s5 +; GFX1030W32-NEXT: s_cselect_b32 s11, s13, s14 +; GFX1030W32-NEXT: s_add_u32 s13, s7, 1 +; GFX1030W32-NEXT: s_addc_u32 s14, s8, 0 +; GFX1030W32-NEXT: s_add_u32 s15, s7, 2 +; GFX1030W32-NEXT: s_addc_u32 s16, s8, 0 +; GFX1030W32-NEXT: s_cmp_lg_u32 s11, 0 +; GFX1030W32-NEXT: s_cselect_b32 s11, s15, s13 +; GFX1030W32-NEXT: s_cselect_b32 s13, s16, s14 ; GFX1030W32-NEXT: s_cmp_lg_u32 s12, 0 -; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1 -; GFX1030W32-NEXT: s_subb_u32 s6, s6, 0 -; GFX1030W32-NEXT: s_cmp_ge_u32 s6, s3 -; GFX1030W32-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo -; GFX1030W32-NEXT: s_cselect_b32 s12, -1, 0 -; GFX1030W32-NEXT: s_cmp_eq_u32 s6, s3 -; GFX1030W32-NEXT: s_cselect_b32 vcc_lo, -1, 0 -; GFX1030W32-NEXT: s_add_u32 s6, s1, 1 -; GFX1030W32-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo -; GFX1030W32-NEXT: s_addc_u32 s12, s5, 0 -; GFX1030W32-NEXT: s_add_u32 s13, s1, 2 -; GFX1030W32-NEXT: s_addc_u32 s14, s5, 0 -; GFX1030W32-NEXT: s_cmp_lg_u32 s7, 0 -; GFX1030W32-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v0 -; GFX1030W32-NEXT: s_subb_u32 s0, s11, s0 -; GFX1030W32-NEXT: v_mov_b32_e32 v2, s13 -; GFX1030W32-NEXT: s_cmp_ge_u32 s0, s3 -; GFX1030W32-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo -; GFX1030W32-NEXT: s_cselect_b32 s7, -1, 0 -; GFX1030W32-NEXT: s_cmp_eq_u32 s0, s3 -; GFX1030W32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX1030W32-NEXT: s_cselect_b32 s0, -1, 0 -; GFX1030W32-NEXT: v_mov_b32_e32 v1, s14 -; GFX1030W32-NEXT: v_cndmask_b32_e64 v0, s7, v0, s0 -; GFX1030W32-NEXT: v_cndmask_b32_e32 v2, s6, v2, vcc_lo -; GFX1030W32-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo -; GFX1030W32-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX1030W32-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo -; GFX1030W32-NEXT: v_cndmask_b32_e32 v0, s1, v2, vcc_lo -; GFX1030W32-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4 +; GFX1030W32-NEXT: s_subb_u32 s3, s3, s9 +; GFX1030W32-NEXT: s_cmp_ge_u32 s3, s5 +; GFX1030W32-NEXT: s_cselect_b32 s9, -1, 0 +; GFX1030W32-NEXT: s_cmp_ge_u32 s10, s4 +; GFX1030W32-NEXT: s_cselect_b32 s10, -1, 0 +; GFX1030W32-NEXT: s_cmp_eq_u32 s3, s5 +; GFX1030W32-NEXT: s_cselect_b32 s3, s10, s9 +; GFX1030W32-NEXT: s_cmp_lg_u32 s3, 0 +; GFX1030W32-NEXT: s_cselect_b32 s9, s13, s8 +; GFX1030W32-NEXT: s_cselect_b32 s8, s11, s7 +; GFX1030W32-NEXT: s_andn2_b32 vcc_lo, exec_lo, s6 ; GFX1030W32-NEXT: s_cbranch_vccnz .LBB16_3 ; GFX1030W32-NEXT: .LBB16_2: -; GFX1030W32-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX1030W32-NEXT: s_sub_i32 s1, 0, s2 +; GFX1030W32-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GFX1030W32-NEXT: s_sub_i32 s5, 0, s4 +; GFX1030W32-NEXT: s_mov_b32 s9, 0 ; GFX1030W32-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX1030W32-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX1030W32-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1030W32-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1030W32-NEXT: s_mul_i32 s1, s1, s0 -; GFX1030W32-NEXT: s_mul_hi_u32 s1, s0, s1 -; GFX1030W32-NEXT: s_add_i32 s0, s0, s1 -; GFX1030W32-NEXT: s_mul_hi_u32 s0, s10, s0 -; GFX1030W32-NEXT: s_mul_i32 s1, s0, s2 -; GFX1030W32-NEXT: s_add_i32 s3, s0, 1 -; GFX1030W32-NEXT: s_sub_i32 s1, s10, s1 -; GFX1030W32-NEXT: s_sub_i32 s4, s1, s2 -; GFX1030W32-NEXT: s_cmp_ge_u32 s1, s2 -; GFX1030W32-NEXT: s_cselect_b32 s0, s3, s0 -; GFX1030W32-NEXT: s_cselect_b32 s1, s4, s1 -; GFX1030W32-NEXT: s_add_i32 s3, s0, 1 -; GFX1030W32-NEXT: s_cmp_ge_u32 s1, s2 -; GFX1030W32-NEXT: s_mov_b32 s1, 0 -; GFX1030W32-NEXT: s_cselect_b32 s0, s3, s0 -; GFX1030W32-NEXT: v_mov_b32_e32 v0, s0 -; GFX1030W32-NEXT: v_mov_b32_e32 v1, s1 +; GFX1030W32-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1030W32-NEXT: s_mul_i32 s5, s5, s3 +; GFX1030W32-NEXT: s_mul_hi_u32 s5, s3, s5 +; GFX1030W32-NEXT: s_add_i32 s3, s3, s5 +; GFX1030W32-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX1030W32-NEXT: s_mul_i32 s5, s3, s4 +; GFX1030W32-NEXT: s_sub_i32 s2, s2, s5 +; GFX1030W32-NEXT: s_add_i32 s5, s3, 1 +; GFX1030W32-NEXT: s_sub_i32 s6, s2, s4 +; GFX1030W32-NEXT: s_cmp_ge_u32 s2, s4 +; GFX1030W32-NEXT: s_cselect_b32 s3, s5, s3 +; GFX1030W32-NEXT: s_cselect_b32 s2, s6, s2 +; GFX1030W32-NEXT: s_add_i32 s5, s3, 1 +; GFX1030W32-NEXT: s_cmp_ge_u32 s2, s4 +; GFX1030W32-NEXT: s_cselect_b32 s8, s5, s3 ; GFX1030W32-NEXT: .LBB16_3: +; GFX1030W32-NEXT: v_mov_b32_e32 v0, s8 ; GFX1030W32-NEXT: v_mov_b32_e32 v2, 0 -; GFX1030W32-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] +; GFX1030W32-NEXT: v_mov_b32_e32 v1, s9 +; GFX1030W32-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX1030W32-NEXT: s_endpgm ; GFX1030W32-NEXT: .LBB16_4: -; GFX1030W32-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1030W32-NEXT: ; implicit-def: $sgpr8_sgpr9 ; GFX1030W32-NEXT: s_branch .LBB16_2 ; ; GFX1030W64-LABEL: sudiv64: ; GFX1030W64: ; %bb.0: ; GFX1030W64-NEXT: s_clause 0x1 -; GFX1030W64-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 -; GFX1030W64-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34 +; GFX1030W64-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GFX1030W64-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34 ; GFX1030W64-NEXT: s_waitcnt lgkmcnt(0) -; GFX1030W64-NEXT: s_or_b64 s[0:1], s[10:11], s[2:3] -; GFX1030W64-NEXT: s_mov_b32 s0, 0 -; GFX1030W64-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1030W64-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5] +; GFX1030W64-NEXT: s_mov_b32 s6, 0 +; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX1030W64-NEXT: s_cbranch_scc0 .LBB16_4 ; GFX1030W64-NEXT: ; %bb.1: -; GFX1030W64-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX1030W64-NEXT: v_cvt_f32_u32_e32 v1, s3 -; GFX1030W64-NEXT: s_sub_u32 s5, 0, s2 -; GFX1030W64-NEXT: s_subb_u32 s6, 0, s3 +; GFX1030W64-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GFX1030W64-NEXT: v_cvt_f32_u32_e32 v1, s5 +; GFX1030W64-NEXT: s_sub_u32 s9, 0, s4 +; GFX1030W64-NEXT: s_subb_u32 s10, 0, s5 ; GFX1030W64-NEXT: v_fmamk_f32 v0, v1, 0x4f800000, v0 ; GFX1030W64-NEXT: v_rcp_f32_e32 v0, v0 ; GFX1030W64-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -2801,160 +2786,158 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W64-NEXT: v_fmamk_f32 v0, v1, 0xcf800000, v0 ; GFX1030W64-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX1030W64-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1030W64-NEXT: v_readfirstlane_b32 s4, v1 -; GFX1030W64-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1030W64-NEXT: s_mul_i32 s1, s5, s4 -; GFX1030W64-NEXT: s_mul_hi_u32 s12, s5, s0 -; GFX1030W64-NEXT: s_mul_i32 s7, s6, s0 -; GFX1030W64-NEXT: s_add_i32 s1, s12, s1 -; GFX1030W64-NEXT: s_mul_i32 s13, s5, s0 -; GFX1030W64-NEXT: s_add_i32 s1, s1, s7 -; GFX1030W64-NEXT: s_mul_hi_u32 s12, s0, s13 -; GFX1030W64-NEXT: s_mul_hi_u32 s14, s4, s13 -; GFX1030W64-NEXT: s_mul_i32 s7, s4, s13 -; GFX1030W64-NEXT: s_mul_hi_u32 s13, s0, s1 -; GFX1030W64-NEXT: s_mul_i32 s0, s0, s1 -; GFX1030W64-NEXT: s_mul_hi_u32 s15, s4, s1 -; GFX1030W64-NEXT: s_add_u32 s0, s12, s0 -; GFX1030W64-NEXT: s_addc_u32 s12, 0, s13 -; GFX1030W64-NEXT: s_add_u32 s0, s0, s7 -; GFX1030W64-NEXT: s_mul_i32 s1, s4, s1 -; GFX1030W64-NEXT: s_addc_u32 s0, s12, s14 -; GFX1030W64-NEXT: s_addc_u32 s7, s15, 0 -; GFX1030W64-NEXT: s_add_u32 s0, s0, s1 -; GFX1030W64-NEXT: s_addc_u32 s7, 0, s7 -; GFX1030W64-NEXT: v_add_co_u32 v0, s[0:1], v0, s0 -; GFX1030W64-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1030W64-NEXT: s_addc_u32 s4, s4, s7 -; GFX1030W64-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1030W64-NEXT: s_mul_i32 s1, s5, s4 -; GFX1030W64-NEXT: s_mul_hi_u32 s7, s5, s0 -; GFX1030W64-NEXT: s_mul_i32 s6, s6, s0 -; GFX1030W64-NEXT: s_add_i32 s1, s7, s1 -; GFX1030W64-NEXT: s_mul_i32 s5, s5, s0 -; GFX1030W64-NEXT: s_add_i32 s1, s1, s6 -; GFX1030W64-NEXT: s_mul_hi_u32 s7, s4, s5 -; GFX1030W64-NEXT: s_mul_i32 s12, s4, s5 -; GFX1030W64-NEXT: s_mul_hi_u32 s5, s0, s5 -; GFX1030W64-NEXT: s_mul_hi_u32 s13, s0, s1 -; GFX1030W64-NEXT: s_mul_i32 s0, s0, s1 -; GFX1030W64-NEXT: s_mul_hi_u32 s6, s4, s1 -; GFX1030W64-NEXT: s_add_u32 s0, s5, s0 -; GFX1030W64-NEXT: s_addc_u32 s5, 0, s13 -; GFX1030W64-NEXT: s_add_u32 s0, s0, s12 -; GFX1030W64-NEXT: s_mul_i32 s1, s4, s1 -; GFX1030W64-NEXT: s_addc_u32 s0, s5, s7 -; GFX1030W64-NEXT: s_addc_u32 s5, s6, 0 -; GFX1030W64-NEXT: s_add_u32 s0, s0, s1 -; GFX1030W64-NEXT: s_addc_u32 s5, 0, s5 -; GFX1030W64-NEXT: v_add_co_u32 v0, s[0:1], v0, s0 -; GFX1030W64-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1030W64-NEXT: s_addc_u32 s0, s4, s5 -; GFX1030W64-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1030W64-NEXT: s_mul_i32 s5, s10, s0 -; GFX1030W64-NEXT: s_mul_hi_u32 s4, s10, s0 -; GFX1030W64-NEXT: s_mul_hi_u32 s6, s11, s0 -; GFX1030W64-NEXT: s_mul_i32 s0, s11, s0 -; GFX1030W64-NEXT: s_mul_hi_u32 s7, s10, s1 -; GFX1030W64-NEXT: s_mul_hi_u32 s12, s11, s1 -; GFX1030W64-NEXT: s_mul_i32 s1, s11, s1 -; GFX1030W64-NEXT: s_add_u32 s5, s7, s5 -; GFX1030W64-NEXT: s_addc_u32 s4, 0, s4 -; GFX1030W64-NEXT: s_add_u32 s1, s5, s1 -; GFX1030W64-NEXT: s_addc_u32 s1, s4, s12 -; GFX1030W64-NEXT: s_addc_u32 s4, s6, 0 -; GFX1030W64-NEXT: s_add_u32 s6, s1, s0 -; GFX1030W64-NEXT: s_addc_u32 s7, 0, s4 -; GFX1030W64-NEXT: s_mul_hi_u32 s0, s2, s6 -; GFX1030W64-NEXT: s_mul_i32 s1, s2, s7 -; GFX1030W64-NEXT: s_mul_i32 s5, s2, s6 -; GFX1030W64-NEXT: s_add_i32 s12, s0, s1 -; GFX1030W64-NEXT: v_sub_co_u32 v0, s[0:1], s10, s5 -; GFX1030W64-NEXT: s_mul_i32 s4, s3, s6 -; GFX1030W64-NEXT: s_add_i32 s12, s12, s4 -; GFX1030W64-NEXT: v_sub_co_u32 v1, s[4:5], v0, s2 -; GFX1030W64-NEXT: s_sub_i32 s13, s11, s12 -; GFX1030W64-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1030W64-NEXT: s_subb_u32 s13, s13, s3 -; GFX1030W64-NEXT: s_cmp_lg_u64 s[4:5], 0 -; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s2, v1 -; GFX1030W64-NEXT: s_subb_u32 s4, s13, 0 -; GFX1030W64-NEXT: s_cmp_ge_u32 s4, s3 -; GFX1030W64-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc -; GFX1030W64-NEXT: s_cselect_b32 s5, -1, 0 -; GFX1030W64-NEXT: s_cmp_eq_u32 s4, s3 -; GFX1030W64-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX1030W64-NEXT: s_add_u32 s4, s6, 1 -; GFX1030W64-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc -; GFX1030W64-NEXT: s_addc_u32 s5, s7, 0 -; GFX1030W64-NEXT: s_add_u32 s13, s6, 2 -; GFX1030W64-NEXT: s_addc_u32 s14, s7, 0 -; GFX1030W64-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1030W64-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 -; GFX1030W64-NEXT: s_subb_u32 s0, s11, s12 -; GFX1030W64-NEXT: v_mov_b32_e32 v2, s13 -; GFX1030W64-NEXT: s_cmp_ge_u32 s0, s3 -; GFX1030W64-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; GFX1030W64-NEXT: s_cselect_b32 s11, -1, 0 -; GFX1030W64-NEXT: s_cmp_eq_u32 s0, s3 -; GFX1030W64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GFX1030W64-NEXT: s_cselect_b64 s[0:1], -1, 0 -; GFX1030W64-NEXT: v_mov_b32_e32 v1, s14 -; GFX1030W64-NEXT: v_cndmask_b32_e64 v0, s11, v0, s[0:1] -; GFX1030W64-NEXT: v_cndmask_b32_e32 v2, s4, v2, vcc -; GFX1030W64-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc -; GFX1030W64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX1030W64-NEXT: v_cndmask_b32_e32 v1, s7, v1, vcc -; GFX1030W64-NEXT: v_cndmask_b32_e32 v0, s6, v2, vcc +; GFX1030W64-NEXT: v_readfirstlane_b32 s8, v1 +; GFX1030W64-NEXT: v_readfirstlane_b32 s6, v0 +; GFX1030W64-NEXT: s_mul_i32 s7, s9, s8 +; GFX1030W64-NEXT: s_mul_hi_u32 s12, s9, s6 +; GFX1030W64-NEXT: s_mul_i32 s11, s10, s6 +; GFX1030W64-NEXT: s_add_i32 s7, s12, s7 +; GFX1030W64-NEXT: s_mul_i32 s13, s9, s6 +; GFX1030W64-NEXT: s_add_i32 s7, s7, s11 +; GFX1030W64-NEXT: s_mul_hi_u32 s12, s6, s13 +; GFX1030W64-NEXT: s_mul_i32 s15, s6, s7 +; GFX1030W64-NEXT: s_mul_hi_u32 s14, s8, s13 +; GFX1030W64-NEXT: s_mul_i32 s11, s8, s13 +; GFX1030W64-NEXT: s_mul_hi_u32 s13, s6, s7 +; GFX1030W64-NEXT: s_add_u32 s12, s12, s15 +; GFX1030W64-NEXT: s_addc_u32 s13, 0, s13 +; GFX1030W64-NEXT: s_mul_hi_u32 s16, s8, s7 +; GFX1030W64-NEXT: s_add_u32 s11, s12, s11 +; GFX1030W64-NEXT: s_mul_i32 s7, s8, s7 +; GFX1030W64-NEXT: s_addc_u32 s11, s13, s14 +; GFX1030W64-NEXT: s_addc_u32 s12, s16, 0 +; GFX1030W64-NEXT: s_add_u32 s7, s11, s7 +; GFX1030W64-NEXT: s_addc_u32 s11, 0, s12 +; GFX1030W64-NEXT: s_add_i32 s12, s6, s7 +; GFX1030W64-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX1030W64-NEXT: s_mul_hi_u32 s13, s9, s12 +; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1030W64-NEXT: s_mul_i32 s6, s9, s12 +; GFX1030W64-NEXT: s_addc_u32 s8, s8, s11 +; GFX1030W64-NEXT: s_mul_i32 s10, s10, s12 +; GFX1030W64-NEXT: s_mul_i32 s9, s9, s8 +; GFX1030W64-NEXT: s_mul_hi_u32 s7, s12, s6 +; GFX1030W64-NEXT: s_add_i32 s9, s13, s9 +; GFX1030W64-NEXT: s_mul_hi_u32 s11, s8, s6 +; GFX1030W64-NEXT: s_add_i32 s9, s9, s10 +; GFX1030W64-NEXT: s_mul_i32 s6, s8, s6 +; GFX1030W64-NEXT: s_mul_i32 s14, s12, s9 +; GFX1030W64-NEXT: s_mul_hi_u32 s13, s12, s9 +; GFX1030W64-NEXT: s_add_u32 s7, s7, s14 +; GFX1030W64-NEXT: s_addc_u32 s13, 0, s13 +; GFX1030W64-NEXT: s_mul_hi_u32 s10, s8, s9 +; GFX1030W64-NEXT: s_add_u32 s6, s7, s6 +; GFX1030W64-NEXT: s_mul_i32 s9, s8, s9 +; GFX1030W64-NEXT: s_addc_u32 s6, s13, s11 +; GFX1030W64-NEXT: s_addc_u32 s7, s10, 0 +; GFX1030W64-NEXT: s_add_u32 s6, s6, s9 +; GFX1030W64-NEXT: s_addc_u32 s9, 0, s7 +; GFX1030W64-NEXT: s_add_i32 s12, s12, s6 +; GFX1030W64-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX1030W64-NEXT: s_mul_hi_u32 s10, s2, s12 +; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1030W64-NEXT: s_mul_hi_u32 s6, s3, s12 +; GFX1030W64-NEXT: s_addc_u32 s7, s8, s9 +; GFX1030W64-NEXT: s_mul_i32 s8, s3, s12 +; GFX1030W64-NEXT: s_mul_i32 s11, s2, s7 +; GFX1030W64-NEXT: s_mul_hi_u32 s9, s2, s7 +; GFX1030W64-NEXT: s_add_u32 s10, s10, s11 +; GFX1030W64-NEXT: s_addc_u32 s9, 0, s9 +; GFX1030W64-NEXT: s_mul_hi_u32 s12, s3, s7 +; GFX1030W64-NEXT: s_add_u32 s8, s10, s8 +; GFX1030W64-NEXT: s_mul_i32 s7, s3, s7 +; GFX1030W64-NEXT: s_addc_u32 s6, s9, s6 +; GFX1030W64-NEXT: s_addc_u32 s8, s12, 0 +; GFX1030W64-NEXT: s_add_u32 s10, s6, s7 +; GFX1030W64-NEXT: s_addc_u32 s11, 0, s8 +; GFX1030W64-NEXT: s_mul_hi_u32 s6, s4, s10 +; GFX1030W64-NEXT: s_mul_i32 s7, s4, s11 +; GFX1030W64-NEXT: s_mul_i32 s8, s5, s10 +; GFX1030W64-NEXT: s_add_i32 s6, s6, s7 +; GFX1030W64-NEXT: s_add_i32 s12, s6, s8 +; GFX1030W64-NEXT: s_mul_i32 s6, s4, s10 +; GFX1030W64-NEXT: s_sub_i32 s8, s3, s12 +; GFX1030W64-NEXT: s_sub_i32 s13, s2, s6 +; GFX1030W64-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1030W64-NEXT: s_subb_u32 s14, s8, s5 +; GFX1030W64-NEXT: s_sub_i32 s15, s13, s4 +; GFX1030W64-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX1030W64-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX1030W64-NEXT: s_subb_u32 s8, s14, 0 +; GFX1030W64-NEXT: s_cmp_ge_u32 s8, s5 +; GFX1030W64-NEXT: s_cselect_b32 s9, -1, 0 +; GFX1030W64-NEXT: s_cmp_ge_u32 s15, s4 +; GFX1030W64-NEXT: s_cselect_b32 s14, -1, 0 +; GFX1030W64-NEXT: s_cmp_eq_u32 s8, s5 +; GFX1030W64-NEXT: s_cselect_b32 s8, s14, s9 +; GFX1030W64-NEXT: s_add_u32 s9, s10, 1 +; GFX1030W64-NEXT: s_addc_u32 s14, s11, 0 +; GFX1030W64-NEXT: s_add_u32 s15, s10, 2 +; GFX1030W64-NEXT: s_addc_u32 s16, s11, 0 +; GFX1030W64-NEXT: s_cmp_lg_u32 s8, 0 +; GFX1030W64-NEXT: s_cselect_b32 s15, s15, s9 +; GFX1030W64-NEXT: s_cselect_b32 s14, s16, s14 +; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GFX1030W64-NEXT: s_subb_u32 s3, s3, s12 +; GFX1030W64-NEXT: s_cmp_ge_u32 s3, s5 +; GFX1030W64-NEXT: s_cselect_b32 s6, -1, 0 +; GFX1030W64-NEXT: s_cmp_ge_u32 s13, s4 +; GFX1030W64-NEXT: s_cselect_b32 s7, -1, 0 +; GFX1030W64-NEXT: s_cmp_eq_u32 s3, s5 +; GFX1030W64-NEXT: s_cselect_b32 s3, s7, s6 +; GFX1030W64-NEXT: s_cmp_lg_u32 s3, 0 +; GFX1030W64-NEXT: s_cselect_b32 s7, s14, s11 +; GFX1030W64-NEXT: s_cselect_b32 s6, s15, s10 ; GFX1030W64-NEXT: s_cbranch_execnz .LBB16_3 ; GFX1030W64-NEXT: .LBB16_2: -; GFX1030W64-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX1030W64-NEXT: s_sub_i32 s1, 0, s2 +; GFX1030W64-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GFX1030W64-NEXT: s_sub_i32 s5, 0, s4 +; GFX1030W64-NEXT: s_mov_b32 s7, 0 ; GFX1030W64-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX1030W64-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX1030W64-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1030W64-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1030W64-NEXT: s_mul_i32 s1, s1, s0 -; GFX1030W64-NEXT: s_mul_hi_u32 s1, s0, s1 -; GFX1030W64-NEXT: s_add_i32 s0, s0, s1 -; GFX1030W64-NEXT: s_mul_hi_u32 s0, s10, s0 -; GFX1030W64-NEXT: s_mul_i32 s1, s0, s2 -; GFX1030W64-NEXT: s_add_i32 s3, s0, 1 -; GFX1030W64-NEXT: s_sub_i32 s1, s10, s1 -; GFX1030W64-NEXT: s_sub_i32 s4, s1, s2 -; GFX1030W64-NEXT: s_cmp_ge_u32 s1, s2 -; GFX1030W64-NEXT: s_cselect_b32 s0, s3, s0 -; GFX1030W64-NEXT: s_cselect_b32 s1, s4, s1 -; GFX1030W64-NEXT: s_add_i32 s3, s0, 1 -; GFX1030W64-NEXT: s_cmp_ge_u32 s1, s2 -; GFX1030W64-NEXT: s_mov_b32 s1, 0 -; GFX1030W64-NEXT: s_cselect_b32 s0, s3, s0 -; GFX1030W64-NEXT: v_mov_b32_e32 v0, s0 -; GFX1030W64-NEXT: v_mov_b32_e32 v1, s1 +; GFX1030W64-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1030W64-NEXT: s_mul_i32 s5, s5, s3 +; GFX1030W64-NEXT: s_mul_hi_u32 s5, s3, s5 +; GFX1030W64-NEXT: s_add_i32 s3, s3, s5 +; GFX1030W64-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX1030W64-NEXT: s_mul_i32 s5, s3, s4 +; GFX1030W64-NEXT: s_sub_i32 s2, s2, s5 +; GFX1030W64-NEXT: s_add_i32 s5, s3, 1 +; GFX1030W64-NEXT: s_sub_i32 s6, s2, s4 +; GFX1030W64-NEXT: s_cmp_ge_u32 s2, s4 +; GFX1030W64-NEXT: s_cselect_b32 s3, s5, s3 +; GFX1030W64-NEXT: s_cselect_b32 s2, s6, s2 +; GFX1030W64-NEXT: s_add_i32 s5, s3, 1 +; GFX1030W64-NEXT: s_cmp_ge_u32 s2, s4 +; GFX1030W64-NEXT: s_cselect_b32 s6, s5, s3 ; GFX1030W64-NEXT: .LBB16_3: +; GFX1030W64-NEXT: v_mov_b32_e32 v0, s6 ; GFX1030W64-NEXT: v_mov_b32_e32 v2, 0 -; GFX1030W64-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] +; GFX1030W64-NEXT: v_mov_b32_e32 v1, s7 +; GFX1030W64-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX1030W64-NEXT: s_endpgm ; GFX1030W64-NEXT: .LBB16_4: -; GFX1030W64-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1030W64-NEXT: ; implicit-def: $sgpr6_sgpr7 ; GFX1030W64-NEXT: s_branch .LBB16_2 ; ; GFX11-LABEL: sudiv64: ; GFX11: ; %bb.0: ; GFX11-NEXT: s_clause 0x1 -; GFX11-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 -; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x34 +; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_or_b64 s[4:5], s[10:11], s[2:3] -; GFX11-NEXT: s_mov_b32 s4, 0 +; GFX11-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5] +; GFX11-NEXT: s_mov_b32 s6, 0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX11-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX11-NEXT: s_cbranch_scc0 .LBB16_4 ; GFX11-NEXT: ; %bb.1: -; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX11-NEXT: v_cvt_f32_u32_e32 v1, s3 -; GFX11-NEXT: s_sub_u32 s5, 0, s2 -; GFX11-NEXT: s_subb_u32 s6, 0, s3 +; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GFX11-NEXT: v_cvt_f32_u32_e32 v1, s5 +; GFX11-NEXT: s_sub_u32 s9, 0, s4 +; GFX11-NEXT: s_subb_u32 s10, 0, s5 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_fmamk_f32 v0, v1, 0x4f800000, v0 ; GFX11-NEXT: v_rcp_f32_e32 v0, v0 @@ -2968,310 +2951,308 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX11-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) -; GFX11-NEXT: v_readfirstlane_b32 s0, v1 -; GFX11-NEXT: v_readfirstlane_b32 s1, v0 -; GFX11-NEXT: s_mul_i32 s7, s5, s0 -; GFX11-NEXT: s_mul_hi_u32 s13, s5, s1 -; GFX11-NEXT: s_mul_i32 s12, s6, s1 -; GFX11-NEXT: s_add_i32 s7, s13, s7 -; GFX11-NEXT: s_mul_i32 s14, s5, s1 -; GFX11-NEXT: s_add_i32 s7, s7, s12 -; GFX11-NEXT: s_mul_hi_u32 s13, s1, s14 -; GFX11-NEXT: s_mul_hi_u32 s15, s0, s14 -; GFX11-NEXT: s_mul_i32 s12, s0, s14 -; GFX11-NEXT: s_mul_hi_u32 s14, s1, s7 -; GFX11-NEXT: s_mul_i32 s1, s1, s7 -; GFX11-NEXT: s_mul_hi_u32 s16, s0, s7 -; GFX11-NEXT: s_add_u32 s1, s13, s1 -; GFX11-NEXT: s_addc_u32 s13, 0, s14 -; GFX11-NEXT: s_add_u32 s1, s1, s12 -; GFX11-NEXT: s_mul_i32 s7, s0, s7 -; GFX11-NEXT: s_addc_u32 s1, s13, s15 -; GFX11-NEXT: s_addc_u32 s12, s16, 0 -; GFX11-NEXT: s_add_u32 s1, s1, s7 -; GFX11-NEXT: s_addc_u32 s7, 0, s12 -; GFX11-NEXT: v_add_co_u32 v0, s1, v0, s1 -; GFX11-NEXT: s_cmp_lg_u32 s1, 0 -; GFX11-NEXT: s_addc_u32 s0, s0, s7 -; GFX11-NEXT: v_readfirstlane_b32 s1, v0 -; GFX11-NEXT: s_mul_i32 s7, s5, s0 -; GFX11-NEXT: s_mul_hi_u32 s12, s5, s1 -; GFX11-NEXT: s_mul_i32 s6, s6, s1 -; GFX11-NEXT: s_add_i32 s7, s12, s7 -; GFX11-NEXT: s_mul_i32 s5, s5, s1 -; GFX11-NEXT: s_add_i32 s7, s7, s6 -; GFX11-NEXT: s_mul_hi_u32 s12, s0, s5 -; GFX11-NEXT: s_mul_i32 s13, s0, s5 -; GFX11-NEXT: s_mul_hi_u32 s5, s1, s5 -; GFX11-NEXT: s_mul_hi_u32 s14, s1, s7 -; GFX11-NEXT: s_mul_i32 s1, s1, s7 -; GFX11-NEXT: s_mul_hi_u32 s6, s0, s7 -; GFX11-NEXT: s_add_u32 s1, s5, s1 -; GFX11-NEXT: s_addc_u32 s5, 0, s14 -; GFX11-NEXT: s_add_u32 s1, s1, s13 -; GFX11-NEXT: s_mul_i32 s7, s0, s7 -; GFX11-NEXT: s_addc_u32 s1, s5, s12 -; GFX11-NEXT: s_addc_u32 s5, s6, 0 -; GFX11-NEXT: s_add_u32 s1, s1, s7 -; GFX11-NEXT: s_addc_u32 s5, 0, s5 -; GFX11-NEXT: v_add_co_u32 v0, s1, v0, s1 -; GFX11-NEXT: s_cmp_lg_u32 s1, 0 -; GFX11-NEXT: s_addc_u32 s0, s0, s5 -; GFX11-NEXT: v_readfirstlane_b32 s1, v0 -; GFX11-NEXT: s_mul_i32 s6, s10, s0 -; GFX11-NEXT: s_mul_hi_u32 s5, s10, s0 -; GFX11-NEXT: s_mul_hi_u32 s7, s11, s0 -; GFX11-NEXT: s_mul_i32 s0, s11, s0 -; GFX11-NEXT: s_mul_hi_u32 s12, s10, s1 -; GFX11-NEXT: s_mul_hi_u32 s13, s11, s1 -; GFX11-NEXT: s_mul_i32 s1, s11, s1 -; GFX11-NEXT: s_add_u32 s6, s12, s6 -; GFX11-NEXT: s_addc_u32 s5, 0, s5 -; GFX11-NEXT: s_add_u32 s1, s6, s1 -; GFX11-NEXT: s_addc_u32 s1, s5, s13 -; GFX11-NEXT: s_addc_u32 s5, s7, 0 -; GFX11-NEXT: s_add_u32 s1, s1, s0 -; GFX11-NEXT: s_addc_u32 s5, 0, s5 -; GFX11-NEXT: s_mul_hi_u32 s0, s2, s1 -; GFX11-NEXT: s_mul_i32 s7, s2, s5 -; GFX11-NEXT: s_mul_i32 s12, s2, s1 -; GFX11-NEXT: s_add_i32 s0, s0, s7 -; GFX11-NEXT: v_sub_co_u32 v0, s7, s10, s12 -; GFX11-NEXT: s_mul_i32 s6, s3, s1 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_add_i32 s0, s0, s6 -; GFX11-NEXT: v_sub_co_u32 v1, s12, v0, s2 -; GFX11-NEXT: s_sub_i32 s6, s11, s0 -; GFX11-NEXT: s_cmp_lg_u32 s7, 0 -; GFX11-NEXT: s_subb_u32 s6, s6, s3 +; GFX11-NEXT: v_readfirstlane_b32 s7, v1 +; GFX11-NEXT: v_readfirstlane_b32 s8, v0 +; GFX11-NEXT: s_mul_i32 s11, s9, s7 +; GFX11-NEXT: s_mul_hi_u32 s13, s9, s8 +; GFX11-NEXT: s_mul_i32 s12, s10, s8 +; GFX11-NEXT: s_add_i32 s11, s13, s11 +; GFX11-NEXT: s_mul_i32 s14, s9, s8 +; GFX11-NEXT: s_add_i32 s11, s11, s12 +; GFX11-NEXT: s_mul_hi_u32 s13, s8, s14 +; GFX11-NEXT: s_mul_i32 s16, s8, s11 +; GFX11-NEXT: s_mul_hi_u32 s15, s7, s14 +; GFX11-NEXT: s_mul_i32 s12, s7, s14 +; GFX11-NEXT: s_mul_hi_u32 s14, s8, s11 +; GFX11-NEXT: s_add_u32 s13, s13, s16 +; GFX11-NEXT: s_addc_u32 s14, 0, s14 +; GFX11-NEXT: s_mul_hi_u32 s17, s7, s11 +; GFX11-NEXT: s_add_u32 s12, s13, s12 +; GFX11-NEXT: s_mul_i32 s11, s7, s11 +; GFX11-NEXT: s_addc_u32 s12, s14, s15 +; GFX11-NEXT: s_addc_u32 s13, s17, 0 +; GFX11-NEXT: s_add_u32 s11, s12, s11 +; GFX11-NEXT: s_addc_u32 s12, 0, s13 +; GFX11-NEXT: s_add_i32 s8, s8, s11 +; GFX11-NEXT: s_cselect_b32 s11, 1, 0 +; GFX11-NEXT: s_mul_hi_u32 s13, s9, s8 +; GFX11-NEXT: s_cmp_lg_u32 s11, 0 +; GFX11-NEXT: s_mul_i32 s11, s9, s8 +; GFX11-NEXT: s_addc_u32 s7, s7, s12 +; GFX11-NEXT: s_mul_i32 s10, s10, s8 +; GFX11-NEXT: s_mul_i32 s9, s9, s7 +; GFX11-NEXT: s_mul_hi_u32 s12, s8, s11 +; GFX11-NEXT: s_add_i32 s9, s13, s9 +; GFX11-NEXT: s_mul_hi_u32 s13, s7, s11 +; GFX11-NEXT: s_add_i32 s9, s9, s10 +; GFX11-NEXT: s_mul_i32 s10, s7, s11 +; GFX11-NEXT: s_mul_i32 s15, s8, s9 +; GFX11-NEXT: s_mul_hi_u32 s14, s8, s9 +; GFX11-NEXT: s_add_u32 s12, s12, s15 +; GFX11-NEXT: s_addc_u32 s14, 0, s14 +; GFX11-NEXT: s_mul_hi_u32 s11, s7, s9 +; GFX11-NEXT: s_add_u32 s10, s12, s10 +; GFX11-NEXT: s_mul_i32 s9, s7, s9 +; GFX11-NEXT: s_addc_u32 s10, s14, s13 +; GFX11-NEXT: s_addc_u32 s11, s11, 0 +; GFX11-NEXT: s_add_u32 s9, s10, s9 +; GFX11-NEXT: s_addc_u32 s10, 0, s11 +; GFX11-NEXT: s_add_i32 s8, s8, s9 +; GFX11-NEXT: s_cselect_b32 s9, 1, 0 +; GFX11-NEXT: s_mul_hi_u32 s11, s2, s8 +; GFX11-NEXT: s_cmp_lg_u32 s9, 0 +; GFX11-NEXT: s_mul_hi_u32 s9, s3, s8 +; GFX11-NEXT: s_addc_u32 s7, s7, s10 +; GFX11-NEXT: s_mul_i32 s8, s3, s8 +; GFX11-NEXT: s_mul_i32 s12, s2, s7 +; GFX11-NEXT: s_mul_hi_u32 s10, s2, s7 +; GFX11-NEXT: s_add_u32 s11, s11, s12 +; GFX11-NEXT: s_addc_u32 s10, 0, s10 +; GFX11-NEXT: s_mul_hi_u32 s13, s3, s7 +; GFX11-NEXT: s_add_u32 s8, s11, s8 +; GFX11-NEXT: s_mul_i32 s7, s3, s7 +; GFX11-NEXT: s_addc_u32 s8, s10, s9 +; GFX11-NEXT: s_addc_u32 s9, s13, 0 +; GFX11-NEXT: s_add_u32 s7, s8, s7 +; GFX11-NEXT: s_addc_u32 s8, 0, s9 +; GFX11-NEXT: s_mul_hi_u32 s9, s4, s7 +; GFX11-NEXT: s_mul_i32 s10, s4, s8 +; GFX11-NEXT: s_mul_i32 s11, s5, s7 +; GFX11-NEXT: s_add_i32 s9, s9, s10 +; GFX11-NEXT: s_mul_i32 s10, s4, s7 +; GFX11-NEXT: s_add_i32 s9, s9, s11 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_sub_i32 s11, s3, s9 +; GFX11-NEXT: s_sub_i32 s10, s2, s10 +; GFX11-NEXT: s_cselect_b32 s12, 1, 0 ; GFX11-NEXT: s_cmp_lg_u32 s12, 0 -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1 -; GFX11-NEXT: s_subb_u32 s6, s6, 0 +; GFX11-NEXT: s_subb_u32 s11, s11, s5 +; GFX11-NEXT: s_sub_i32 s13, s10, s4 +; GFX11-NEXT: s_cselect_b32 s14, 1, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_cmp_lg_u32 s14, 0 +; GFX11-NEXT: s_subb_u32 s11, s11, 0 +; GFX11-NEXT: s_cmp_ge_u32 s11, s5 +; GFX11-NEXT: s_cselect_b32 s14, -1, 0 +; GFX11-NEXT: s_cmp_ge_u32 s13, s4 +; GFX11-NEXT: s_cselect_b32 s13, -1, 0 +; GFX11-NEXT: s_cmp_eq_u32 s11, s5 +; GFX11-NEXT: s_cselect_b32 s11, s13, s14 +; GFX11-NEXT: s_add_u32 s13, s7, 1 +; GFX11-NEXT: s_addc_u32 s14, s8, 0 +; GFX11-NEXT: s_add_u32 s15, s7, 2 +; GFX11-NEXT: s_addc_u32 s16, s8, 0 +; GFX11-NEXT: s_cmp_lg_u32 s11, 0 +; GFX11-NEXT: s_cselect_b32 s11, s15, s13 +; GFX11-NEXT: s_cselect_b32 s13, s16, s14 +; GFX11-NEXT: s_cmp_lg_u32 s12, 0 +; GFX11-NEXT: s_subb_u32 s3, s3, s9 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: s_cmp_ge_u32 s3, s5 +; GFX11-NEXT: s_cselect_b32 s9, -1, 0 +; GFX11-NEXT: s_cmp_ge_u32 s10, s4 +; GFX11-NEXT: s_cselect_b32 s10, -1, 0 +; GFX11-NEXT: s_cmp_eq_u32 s3, s5 +; GFX11-NEXT: s_cselect_b32 s3, s10, s9 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_cmp_ge_u32 s6, s3 -; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo -; GFX11-NEXT: s_cselect_b32 s12, -1, 0 -; GFX11-NEXT: s_cmp_eq_u32 s6, s3 -; GFX11-NEXT: s_cselect_b32 vcc_lo, -1, 0 -; GFX11-NEXT: s_add_u32 s6, s1, 1 -; GFX11-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo -; GFX11-NEXT: s_addc_u32 s12, s5, 0 -; GFX11-NEXT: s_add_u32 s13, s1, 2 -; GFX11-NEXT: s_addc_u32 s14, s5, 0 -; GFX11-NEXT: s_cmp_lg_u32 s7, 0 -; GFX11-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v0 -; GFX11-NEXT: s_subb_u32 s0, s11, s0 -; GFX11-NEXT: v_mov_b32_e32 v2, s13 -; GFX11-NEXT: s_cmp_ge_u32 s0, s3 -; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo -; GFX11-NEXT: s_cselect_b32 s7, -1, 0 -; GFX11-NEXT: s_cmp_eq_u32 s0, s3 -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: s_cselect_b32 s0, -1, 0 -; GFX11-NEXT: v_mov_b32_e32 v1, s14 -; GFX11-NEXT: v_cndmask_b32_e64 v0, s7, v0, s0 -; GFX11-NEXT: v_cndmask_b32_e32 v2, s6, v2, vcc_lo -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) -; GFX11-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo -; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX11-NEXT: v_cndmask_b32_e32 v1, s5, v1, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e32 v0, s1, v2, vcc_lo -; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4 +; GFX11-NEXT: s_cmp_lg_u32 s3, 0 +; GFX11-NEXT: s_cselect_b32 s9, s13, s8 +; GFX11-NEXT: s_cselect_b32 s8, s11, s7 +; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s6 ; GFX11-NEXT: s_cbranch_vccnz .LBB16_3 ; GFX11-NEXT: .LBB16_2: -; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX11-NEXT: s_sub_i32 s1, 0, s2 +; GFX11-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GFX11-NEXT: s_sub_i32 s5, 0, s4 +; GFX11-NEXT: s_mov_b32 s9, 0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX11-NEXT: s_waitcnt_depctr 0xfff ; GFX11-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX11-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_readfirstlane_b32 s0, v0 -; GFX11-NEXT: s_mul_i32 s1, s1, s0 -; GFX11-NEXT: s_mul_hi_u32 s1, s0, s1 +; GFX11-NEXT: v_readfirstlane_b32 s3, v0 +; GFX11-NEXT: s_mul_i32 s5, s5, s3 +; GFX11-NEXT: s_mul_hi_u32 s5, s3, s5 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_add_i32 s0, s0, s1 -; GFX11-NEXT: s_mul_hi_u32 s0, s10, s0 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_mul_i32 s1, s0, s2 -; GFX11-NEXT: s_add_i32 s3, s0, 1 -; GFX11-NEXT: s_sub_i32 s1, s10, s1 -; GFX11-NEXT: s_sub_i32 s4, s1, s2 -; GFX11-NEXT: s_cmp_ge_u32 s1, s2 -; GFX11-NEXT: s_cselect_b32 s0, s3, s0 -; GFX11-NEXT: s_cselect_b32 s1, s4, s1 -; GFX11-NEXT: s_add_i32 s3, s0, 1 -; GFX11-NEXT: s_cmp_ge_u32 s1, s2 -; GFX11-NEXT: s_mov_b32 s1, 0 -; GFX11-NEXT: s_cselect_b32 s0, s3, s0 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: s_add_i32 s3, s3, s5 +; GFX11-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_mul_i32 s5, s3, s4 +; GFX11-NEXT: s_sub_i32 s2, s2, s5 +; GFX11-NEXT: s_add_i32 s5, s3, 1 +; GFX11-NEXT: s_sub_i32 s6, s2, s4 +; GFX11-NEXT: s_cmp_ge_u32 s2, s4 +; GFX11-NEXT: s_cselect_b32 s3, s5, s3 +; GFX11-NEXT: s_cselect_b32 s2, s6, s2 +; GFX11-NEXT: s_add_i32 s5, s3, 1 +; GFX11-NEXT: s_cmp_ge_u32 s2, s4 +; GFX11-NEXT: s_cselect_b32 s8, s5, s3 ; GFX11-NEXT: .LBB16_3: -; GFX11-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-NEXT: global_store_b64 v2, v[0:1], s[8:9] +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_mov_b32_e32 v0, s8 +; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s9 +; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX11-NEXT: s_endpgm ; GFX11-NEXT: .LBB16_4: -; GFX11-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX11-NEXT: ; implicit-def: $sgpr8_sgpr9 ; GFX11-NEXT: s_branch .LBB16_2 ; ; GFX1250-LABEL: sudiv64: ; GFX1250: ; %bb.0: -; GFX1250-NEXT: s_clause 0x1 -; GFX1250-NEXT: s_load_b128 s[8:11], s[4:5], 0x24 -; GFX1250-NEXT: s_load_b64 s[2:3], s[4:5], 0x34 +; GFX1250-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 +; GFX1250-NEXT: s_wait_xcnt 0x0 +; GFX1250-NEXT: s_load_b64 s[4:5], s[4:5], 0x34 ; GFX1250-NEXT: s_wait_kmcnt 0x0 -; GFX1250-NEXT: s_or_b64 s[0:1], s[10:11], s[2:3] +; GFX1250-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5] ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: s_and_b64 s[0:1], s[0:1], 0xffffffff00000000 -; GFX1250-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1250-NEXT: s_and_b64 s[6:7], s[6:7], lit64(0xffffffff00000000) +; GFX1250-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX1250-NEXT: s_cbranch_scc0 .LBB16_4 ; GFX1250-NEXT: ; %bb.1: -; GFX1250-NEXT: s_cvt_f32_u32 s0, s2 -; GFX1250-NEXT: s_cvt_f32_u32 s1, s3 -; GFX1250-NEXT: s_sub_nc_u64 s[6:7], 0, s[2:3] +; GFX1250-NEXT: s_cvt_f32_u32 s6, s4 +; GFX1250-NEXT: s_cvt_f32_u32 s7, s5 +; GFX1250-NEXT: s_sub_nc_u64 s[10:11], 0, s[4:5] ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(NEXT) | instid1(SALU_CYCLE_3) -; GFX1250-NEXT: s_fmac_f32 s0, s1, 0x4f800000 -; GFX1250-NEXT: v_s_rcp_f32 s0, s0 +; GFX1250-NEXT: s_fmac_f32 s6, s7, 0x4f800000 +; GFX1250-NEXT: v_s_rcp_f32 s6, s6 ; GFX1250-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) -; GFX1250-NEXT: s_mul_f32 s0, s0, 0x5f7ffffc -; GFX1250-NEXT: s_mul_f32 s1, s0, 0x2f800000 +; GFX1250-NEXT: s_mul_f32 s6, s6, 0x5f7ffffc +; GFX1250-NEXT: s_mul_f32 s7, s6, 0x2f800000 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3) -; GFX1250-NEXT: s_trunc_f32 s1, s1 -; GFX1250-NEXT: s_fmac_f32 s0, s1, 0xcf800000 -; GFX1250-NEXT: s_cvt_u32_f32 s5, s1 -; GFX1250-NEXT: s_mov_b32 s1, 0 +; GFX1250-NEXT: s_trunc_f32 s7, s7 +; GFX1250-NEXT: s_fmac_f32 s6, s7, 0xcf800000 +; GFX1250-NEXT: s_cvt_u32_f32 s9, s7 +; GFX1250-NEXT: s_mov_b32 s7, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3) -; GFX1250-NEXT: s_cvt_u32_f32 s4, s0 -; GFX1250-NEXT: s_mul_u64 s[12:13], s[6:7], s[4:5] +; GFX1250-NEXT: s_cvt_u32_f32 s8, s6 +; GFX1250-NEXT: s_mul_u64 s[12:13], s[10:11], s[8:9] ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-NEXT: s_mul_hi_u32 s15, s4, s13 -; GFX1250-NEXT: s_mul_i32 s14, s4, s13 -; GFX1250-NEXT: s_mul_hi_u32 s0, s4, s12 -; GFX1250-NEXT: s_mul_i32 s17, s5, s12 -; GFX1250-NEXT: s_add_nc_u64 s[14:15], s[0:1], s[14:15] -; GFX1250-NEXT: s_mul_hi_u32 s16, s5, s12 -; GFX1250-NEXT: s_mul_hi_u32 s18, s5, s13 -; GFX1250-NEXT: s_add_co_u32 s0, s14, s17 -; GFX1250-NEXT: s_add_co_ci_u32 s0, s15, s16 -; GFX1250-NEXT: s_mul_i32 s12, s5, s13 +; GFX1250-NEXT: s_mul_hi_u32 s15, s8, s13 +; GFX1250-NEXT: s_mul_i32 s14, s8, s13 +; GFX1250-NEXT: s_mul_hi_u32 s6, s8, s12 +; GFX1250-NEXT: s_mul_i32 s17, s9, s12 +; GFX1250-NEXT: s_add_nc_u64 s[14:15], s[6:7], s[14:15] +; GFX1250-NEXT: s_mul_hi_u32 s16, s9, s12 +; GFX1250-NEXT: s_mul_hi_u32 s18, s9, s13 +; GFX1250-NEXT: s_add_co_u32 s6, s14, s17 +; GFX1250-NEXT: s_add_co_ci_u32 s6, s15, s16 +; GFX1250-NEXT: s_mul_i32 s12, s9, s13 ; GFX1250-NEXT: s_add_co_ci_u32 s13, s18, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: s_add_nc_u64 s[12:13], s[0:1], s[12:13] -; GFX1250-NEXT: v_add_co_u32 v0, s0, s4, s12 -; GFX1250-NEXT: s_cmp_lg_u32 s0, 0 -; GFX1250-NEXT: s_add_co_ci_u32 s5, s5, s13 -; GFX1250-NEXT: v_readfirstlane_b32 s4, v0 -; GFX1250-NEXT: s_mul_u64 s[6:7], s[6:7], s[4:5] +; GFX1250-NEXT: s_add_nc_u64 s[12:13], s[6:7], s[12:13] +; GFX1250-NEXT: s_add_co_i32 s8, s8, s12 +; GFX1250-NEXT: s_cselect_b32 s6, 1, 0 +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1250-NEXT: s_cmp_lg_u32 s6, 0 +; GFX1250-NEXT: s_add_co_ci_u32 s9, s9, s13 +; GFX1250-NEXT: s_mul_u64 s[10:11], s[10:11], s[8:9] ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-NEXT: s_mul_hi_u32 s13, s4, s7 -; GFX1250-NEXT: s_mul_i32 s12, s4, s7 -; GFX1250-NEXT: s_mul_hi_u32 s0, s4, s6 -; GFX1250-NEXT: s_mul_i32 s15, s5, s6 -; GFX1250-NEXT: s_add_nc_u64 s[12:13], s[0:1], s[12:13] -; GFX1250-NEXT: s_mul_hi_u32 s14, s5, s6 -; GFX1250-NEXT: s_mul_hi_u32 s4, s5, s7 -; GFX1250-NEXT: s_add_co_u32 s0, s12, s15 -; GFX1250-NEXT: s_add_co_ci_u32 s0, s13, s14 -; GFX1250-NEXT: s_mul_i32 s6, s5, s7 -; GFX1250-NEXT: s_add_co_ci_u32 s7, s4, 0 +; GFX1250-NEXT: s_mul_hi_u32 s13, s8, s11 +; GFX1250-NEXT: s_mul_i32 s12, s8, s11 +; GFX1250-NEXT: s_mul_hi_u32 s6, s8, s10 +; GFX1250-NEXT: s_mul_i32 s15, s9, s10 +; GFX1250-NEXT: s_add_nc_u64 s[12:13], s[6:7], s[12:13] +; GFX1250-NEXT: s_mul_hi_u32 s14, s9, s10 +; GFX1250-NEXT: s_mul_hi_u32 s16, s9, s11 +; GFX1250-NEXT: s_add_co_u32 s6, s12, s15 +; GFX1250-NEXT: s_add_co_ci_u32 s6, s13, s14 +; GFX1250-NEXT: s_mul_i32 s10, s9, s11 +; GFX1250-NEXT: s_add_co_ci_u32 s11, s16, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: s_add_nc_u64 s[6:7], s[0:1], s[6:7] -; GFX1250-NEXT: v_add_co_u32 v0, s0, v0, s6 -; GFX1250-NEXT: s_cmp_lg_u32 s0, 0 -; GFX1250-NEXT: s_add_co_ci_u32 s0, s5, s7 -; GFX1250-NEXT: v_readfirstlane_b32 s7, v0 -; GFX1250-NEXT: s_mul_hi_u32 s5, s10, s0 -; GFX1250-NEXT: s_mul_i32 s4, s10, s0 -; GFX1250-NEXT: s_mul_hi_u32 s12, s11, s0 -; GFX1250-NEXT: s_mul_i32 s6, s11, s0 -; GFX1250-NEXT: s_mul_hi_u32 s0, s10, s7 -; GFX1250-NEXT: s_mul_i32 s13, s11, s7 -; GFX1250-NEXT: s_add_nc_u64 s[4:5], s[0:1], s[4:5] -; GFX1250-NEXT: s_mul_hi_u32 s0, s11, s7 -; GFX1250-NEXT: s_add_co_u32 s4, s4, s13 -; GFX1250-NEXT: s_add_co_ci_u32 s0, s5, s0 -; GFX1250-NEXT: s_add_co_ci_u32 s7, s12, 0 +; GFX1250-NEXT: s_add_nc_u64 s[10:11], s[6:7], s[10:11] +; GFX1250-NEXT: s_add_co_i32 s8, s8, s10 +; GFX1250-NEXT: s_cselect_b32 s10, 1, 0 +; GFX1250-NEXT: s_mul_hi_u32 s6, s2, s8 +; GFX1250-NEXT: s_cmp_lg_u32 s10, 0 +; GFX1250-NEXT: s_mul_hi_u32 s12, s3, s8 +; GFX1250-NEXT: s_add_co_ci_u32 s10, s9, s11 +; GFX1250-NEXT: s_mul_i32 s11, s3, s8 +; GFX1250-NEXT: s_mul_hi_u32 s9, s2, s10 +; GFX1250-NEXT: s_mul_i32 s8, s2, s10 +; GFX1250-NEXT: s_mul_hi_u32 s13, s3, s10 +; GFX1250-NEXT: s_add_nc_u64 s[8:9], s[6:7], s[8:9] +; GFX1250-NEXT: s_mul_i32 s10, s3, s10 +; GFX1250-NEXT: s_add_co_u32 s6, s8, s11 +; GFX1250-NEXT: s_add_co_ci_u32 s6, s9, s12 +; GFX1250-NEXT: s_add_co_ci_u32 s11, s13, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: s_add_nc_u64 s[4:5], s[0:1], s[6:7] -; GFX1250-NEXT: s_and_b64 s[6:7], s[4:5], 0xffffffff00000000 +; GFX1250-NEXT: s_add_nc_u64 s[8:9], s[6:7], s[10:11] +; GFX1250-NEXT: s_and_b64 s[10:11], s[8:9], lit64(0xffffffff00000000) ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: s_or_b32 s6, s6, s4 -; GFX1250-NEXT: s_mul_u64 s[4:5], s[2:3], s[6:7] -; GFX1250-NEXT: s_add_nc_u64 s[14:15], s[6:7], 2 -; GFX1250-NEXT: v_sub_co_u32 v0, s0, s10, s4 -; GFX1250-NEXT: s_sub_co_i32 s4, s11, s5 -; GFX1250-NEXT: s_cmp_lg_u32 s0, 0 -; GFX1250-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15 -; GFX1250-NEXT: v_sub_co_u32 v1, s12, v0, s2 -; GFX1250-NEXT: s_sub_co_ci_u32 s4, s4, s3 -; GFX1250-NEXT: s_cmp_lg_u32 s12, 0 -; GFX1250-NEXT: s_add_nc_u64 s[12:13], s[6:7], 1 -; GFX1250-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v1 -; GFX1250-NEXT: s_sub_co_ci_u32 s4, s4, 0 +; GFX1250-NEXT: s_or_b32 s10, s10, s8 +; GFX1250-NEXT: s_mul_u64 s[8:9], s[4:5], s[10:11] ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-NEXT: s_cmp_ge_u32 s4, s3 -; GFX1250-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX1250-NEXT: s_sub_co_i32 s6, s2, s8 +; GFX1250-NEXT: s_cselect_b32 s8, 1, 0 +; GFX1250-NEXT: s_sub_co_i32 s12, s3, s9 +; GFX1250-NEXT: s_cmp_lg_u32 s8, 0 +; GFX1250-NEXT: s_sub_co_ci_u32 s12, s12, s5 +; GFX1250-NEXT: s_sub_co_i32 s13, s6, s4 +; GFX1250-NEXT: s_cselect_b32 s14, 1, 0 +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX1250-NEXT: s_cmp_lg_u32 s14, 0 +; GFX1250-NEXT: s_sub_co_ci_u32 s12, s12, 0 +; GFX1250-NEXT: s_cmp_ge_u32 s12, s5 ; GFX1250-NEXT: s_cselect_b32 s14, -1, 0 -; GFX1250-NEXT: s_cmp_eq_u32 s4, s3 -; GFX1250-NEXT: s_cselect_b32 vcc_lo, -1, 0 -; GFX1250-NEXT: s_cmp_lg_u32 s0, 0 -; GFX1250-NEXT: v_cndmask_b32_e32 v1, s14, v1, vcc_lo -; GFX1250-NEXT: v_cmp_le_u32_e32 vcc_lo, s2, v0 -; GFX1250-NEXT: s_sub_co_ci_u32 s0, s11, s5 +; GFX1250-NEXT: s_cmp_ge_u32 s13, s4 +; GFX1250-NEXT: s_cselect_b32 s15, -1, 0 +; GFX1250-NEXT: s_cmp_eq_u32 s12, s5 +; GFX1250-NEXT: s_add_nc_u64 s[12:13], s[10:11], 1 +; GFX1250-NEXT: s_cselect_b32 s16, s15, s14 +; GFX1250-NEXT: s_add_nc_u64 s[14:15], s[10:11], 2 +; GFX1250-NEXT: s_cmp_lg_u32 s16, 0 +; GFX1250-NEXT: s_cselect_b32 s12, s14, s12 +; GFX1250-NEXT: s_cselect_b32 s13, s15, s13 +; GFX1250-NEXT: s_cmp_lg_u32 s8, 0 +; GFX1250-NEXT: s_sub_co_ci_u32 s3, s3, s9 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-NEXT: s_cmp_ge_u32 s0, s3 -; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo -; GFX1250-NEXT: s_cselect_b32 s4, -1, 0 -; GFX1250-NEXT: s_cmp_eq_u32 s0, s3 -; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX1250-NEXT: s_cselect_b32 s0, -1, 0 -; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX1250-NEXT: v_cndmask_b32_e64 v0, s4, v0, s0 -; GFX1250-NEXT: v_cndmask_b32_e32 v2, s12, v2, vcc_lo -; GFX1250-NEXT: v_cndmask_b32_e32 v1, s13, v3, vcc_lo -; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) -; GFX1250-NEXT: v_cndmask_b32_e32 v1, s7, v1, vcc_lo -; GFX1250-NEXT: v_cndmask_b32_e32 v0, s6, v2, vcc_lo +; GFX1250-NEXT: s_cmp_ge_u32 s3, s5 +; GFX1250-NEXT: s_cselect_b32 s8, -1, 0 +; GFX1250-NEXT: s_cmp_ge_u32 s6, s4 +; GFX1250-NEXT: s_cselect_b32 s6, -1, 0 +; GFX1250-NEXT: s_cmp_eq_u32 s3, s5 +; GFX1250-NEXT: s_cselect_b32 s3, s6, s8 +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-NEXT: s_cmp_lg_u32 s3, 0 +; GFX1250-NEXT: s_cselect_b32 s9, s13, s11 +; GFX1250-NEXT: s_cselect_b32 s8, s12, s10 ; GFX1250-NEXT: s_cbranch_execnz .LBB16_3 ; GFX1250-NEXT: .LBB16_2: -; GFX1250-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GFX1250-NEXT: s_sub_co_i32 s1, 0, s2 +; GFX1250-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GFX1250-NEXT: s_sub_co_i32 s5, 0, s4 +; GFX1250-NEXT: s_mov_b32 s9, 0 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(TRANS32_DEP_1) ; GFX1250-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1250-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1250-NEXT: s_mul_i32 s1, s1, s0 +; GFX1250-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1250-NEXT: s_mul_i32 s5, s5, s3 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: s_mul_hi_u32 s1, s0, s1 -; GFX1250-NEXT: s_add_co_i32 s0, s0, s1 +; GFX1250-NEXT: s_mul_hi_u32 s5, s3, s5 +; GFX1250-NEXT: s_add_co_i32 s3, s3, s5 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: s_mul_hi_u32 s0, s10, s0 -; GFX1250-NEXT: s_mul_i32 s1, s0, s2 -; GFX1250-NEXT: s_add_co_i32 s3, s0, 1 -; GFX1250-NEXT: s_sub_co_i32 s1, s10, s1 +; GFX1250-NEXT: s_mul_hi_u32 s3, s2, s3 +; GFX1250-NEXT: s_mul_i32 s5, s3, s4 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-NEXT: s_sub_co_i32 s4, s1, s2 -; GFX1250-NEXT: s_cmp_ge_u32 s1, s2 -; GFX1250-NEXT: s_cselect_b32 s0, s3, s0 -; GFX1250-NEXT: s_cselect_b32 s1, s4, s1 -; GFX1250-NEXT: s_add_co_i32 s3, s0, 1 -; GFX1250-NEXT: s_cmp_ge_u32 s1, s2 -; GFX1250-NEXT: s_mov_b32 s1, 0 -; GFX1250-NEXT: s_cselect_b32 s0, s3, s0 -; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[0:1] +; GFX1250-NEXT: s_sub_co_i32 s2, s2, s5 +; GFX1250-NEXT: s_add_co_i32 s5, s3, 1 +; GFX1250-NEXT: s_sub_co_i32 s6, s2, s4 +; GFX1250-NEXT: s_cmp_ge_u32 s2, s4 +; GFX1250-NEXT: s_cselect_b32 s3, s5, s3 +; GFX1250-NEXT: s_cselect_b32 s2, s6, s2 +; GFX1250-NEXT: s_add_co_i32 s5, s3, 1 +; GFX1250-NEXT: s_cmp_ge_u32 s2, s4 +; GFX1250-NEXT: s_cselect_b32 s8, s5, s3 ; GFX1250-NEXT: .LBB16_3: +; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[8:9] ; GFX1250-NEXT: v_mov_b32_e32 v2, 0 -; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[8:9] +; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[0:1] ; GFX1250-NEXT: s_endpgm ; GFX1250-NEXT: .LBB16_4: -; GFX1250-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1250-NEXT: ; implicit-def: $sgpr8_sgpr9 ; GFX1250-NEXT: s_branch .LBB16_2 %result = udiv i64 %x, %y store i64 %result, ptr addrspace(1) %out diff --git a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll index 3f699a5ca218b..4f5e4eb4eaeb4 100644 --- a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll +++ b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll @@ -11,17 +11,17 @@ define i32 @s_add_co_select_user() { ; GFX7-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: v_add_i32_e64 v0, s[4:5], s6, s6 +; GFX7-NEXT: s_add_i32 s7, s6, s6 +; GFX7-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX7-NEXT: s_or_b32 s4, s4, s5 ; GFX7-NEXT: s_cmp_lg_u32 s4, 0 -; GFX7-NEXT: s_addc_u32 s7, s6, 0 +; GFX7-NEXT: s_addc_u32 s8, s6, 0 ; GFX7-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX7-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GFX7-NEXT: s_cselect_b32 s4, s7, 0 +; GFX7-NEXT: s_cselect_b32 s4, s8, 0 ; GFX7-NEXT: s_cmp_gt_u32 s6, 31 -; GFX7-NEXT: v_mov_b32_e32 v1, s4 -; GFX7-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX7-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX7-NEXT: s_cselect_b32 s4, s7, s4 +; GFX7-NEXT: v_mov_b32_e32 v0, s4 ; GFX7-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-LABEL: s_add_co_select_user: @@ -30,16 +30,16 @@ define i32 @s_add_co_select_user() { ; GFX9-NEXT: s_mov_b64 s[4:5], 0 ; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e64 v0, s[4:5], s6, s6 +; GFX9-NEXT: s_add_i32 s7, s6, s6 +; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 -; GFX9-NEXT: s_addc_u32 s7, s6, 0 +; GFX9-NEXT: s_addc_u32 s8, s6, 0 ; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GFX9-NEXT: s_cselect_b32 s4, s7, 0 +; GFX9-NEXT: s_cselect_b32 s4, s8, 0 ; GFX9-NEXT: s_cmp_gt_u32 s6, 31 -; GFX9-NEXT: v_mov_b32_e32 v1, s4 -; GFX9-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc +; GFX9-NEXT: s_cselect_b32 s4, s7, s4 +; GFX9-NEXT: v_mov_b32_e32 v0, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; ; GFX10-LABEL: s_add_co_select_user: @@ -48,15 +48,16 @@ define i32 @s_add_co_select_user() { ; GFX10-NEXT: s_mov_b64 s[4:5], 0 ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s5, s4, s4 -; GFX10-NEXT: s_cmp_lg_u32 s5, 0 -; GFX10-NEXT: s_addc_u32 s5, s4, 0 -; GFX10-NEXT: s_cselect_b32 s6, -1, 0 -; GFX10-NEXT: s_and_b32 s6, s6, exec_lo -; GFX10-NEXT: s_cselect_b32 s5, s5, 0 +; GFX10-NEXT: s_add_i32 s5, s4, s4 +; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: s_cmp_lg_u32 s6, 0 +; GFX10-NEXT: s_addc_u32 s6, s4, 0 +; GFX10-NEXT: s_cselect_b32 s7, -1, 0 +; GFX10-NEXT: s_and_b32 s7, s7, exec_lo +; GFX10-NEXT: s_cselect_b32 s6, s6, 0 ; GFX10-NEXT: s_cmp_gt_u32 s4, 31 -; GFX10-NEXT: s_cselect_b32 vcc_lo, -1, 0 -; GFX10-NEXT: v_cndmask_b32_e32 v0, s5, v0, vcc_lo +; GFX10-NEXT: s_cselect_b32 s4, s5, s6 +; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: s_add_co_select_user: @@ -65,16 +66,18 @@ define i32 @s_add_co_select_user() { ; GFX11-NEXT: s_mov_b64 s[0:1], 0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s1, s0, s0 -; GFX11-NEXT: s_cmp_lg_u32 s1, 0 -; GFX11-NEXT: s_addc_u32 s1, s0, 0 -; GFX11-NEXT: s_cselect_b32 s2, -1, 0 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_and_b32 s2, s2, exec_lo -; GFX11-NEXT: s_cselect_b32 s1, s1, 0 +; GFX11-NEXT: s_add_i32 s1, s0, s0 +; GFX11-NEXT: s_cselect_b32 s2, 1, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) +; GFX11-NEXT: s_cmp_lg_u32 s2, 0 +; GFX11-NEXT: s_addc_u32 s2, s0, 0 +; GFX11-NEXT: s_cselect_b32 s3, -1, 0 +; GFX11-NEXT: s_and_b32 s3, s3, exec_lo +; GFX11-NEXT: s_cselect_b32 s2, s2, 0 ; GFX11-NEXT: s_cmp_gt_u32 s0, 31 -; GFX11-NEXT: s_cselect_b32 vcc_lo, -1, 0 -; GFX11-NEXT: v_cndmask_b32_e32 v0, s1, v0, vcc_lo +; GFX11-NEXT: s_cselect_b32 s0, s1, s2 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: s_setpc_b64 s[30:31] bb: %i = load volatile i32, ptr addrspace(4) null, align 8 diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index 5e76c7d7c734f..58b019cc2d27a 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -6,8 +6,9 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_sdiv: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_ashr_i32 s8, s1, 31 ; GCN-NEXT: s_add_u32 s0, s0, s8 @@ -16,126 +17,158 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_xor_b64 s[10:11], s[0:1], s[8:9] ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s11 -; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 -; GCN-NEXT: s_sub_u32 s4, 0, s10 -; GCN-NEXT: s_subb_u32 s5, 0, s11 +; GCN-NEXT: s_sub_u32 s12, 0, s10 +; GCN-NEXT: s_subb_u32 s13, 0, s11 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_ashr_i32 s12, s3, 31 -; GCN-NEXT: s_add_u32 s2, s2, s12 -; GCN-NEXT: s_mov_b32 s13, s12 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: s_addc_u32 s3, s3, s12 -; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[12:13] -; GCN-NEXT: v_mul_lo_u32 v2, s4, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v5, s5, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s4, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s4, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s5, v0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s4, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 -; GCN-NEXT: v_mul_hi_u32 v4, s2, v1 -; GCN-NEXT: v_mul_hi_u32 v5, s3, v1 -; GCN-NEXT: v_mul_lo_u32 v1, s3, v1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 -; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 -; GCN-NEXT: v_mov_b32_e32 v5, s11 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s10, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 -; GCN-NEXT: v_sub_i32_e32 v4, vcc, s3, v2 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, s2, v3 -; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc -; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s10, v3 -; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s11, v4 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s10, v5 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s11, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] -; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 1, v0 -; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] -; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 2, v0 -; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v5, v6, v8, s[0:1] -; GCN-NEXT: v_mov_b32_e32 v6, s3 -; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s11, v2 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s10, v3 -; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s11, v2 -; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; GCN-NEXT: s_xor_b64 s[0:1], s[12:13], s[8:9] -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; GCN-NEXT: v_xor_b32_e32 v0, s0, v0 -; GCN-NEXT: v_xor_b32_e32 v1, s1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 +; GCN-NEXT: v_readfirstlane_b32 s14, v1 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s1, s12, s14 +; GCN-NEXT: v_readfirstlane_b32 s17, v2 +; GCN-NEXT: s_mul_i32 s15, s13, s0 +; GCN-NEXT: s_mul_i32 s16, s12, s0 +; GCN-NEXT: s_add_i32 s1, s17, s1 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s16 +; GCN-NEXT: s_add_i32 s1, s1, s15 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s1 +; GCN-NEXT: v_mul_hi_u32 v4, v1, s16 +; GCN-NEXT: v_readfirstlane_b32 s15, v3 +; GCN-NEXT: s_mul_i32 s17, s0, s1 +; GCN-NEXT: v_mul_hi_u32 v1, v1, s1 +; GCN-NEXT: s_add_u32 s15, s15, s17 +; GCN-NEXT: v_readfirstlane_b32 s17, v0 +; GCN-NEXT: s_addc_u32 s17, 0, s17 +; GCN-NEXT: s_mul_i32 s16, s14, s16 +; GCN-NEXT: v_readfirstlane_b32 s18, v4 +; GCN-NEXT: s_add_u32 s15, s15, s16 +; GCN-NEXT: s_addc_u32 s15, s17, s18 +; GCN-NEXT: v_readfirstlane_b32 s16, v1 +; GCN-NEXT: s_addc_u32 s16, s16, 0 +; GCN-NEXT: s_mul_i32 s1, s14, s1 +; GCN-NEXT: s_add_u32 s1, s15, s1 +; GCN-NEXT: s_addc_u32 s15, 0, s16 +; GCN-NEXT: s_add_i32 s16, s0, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s16 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: v_mul_hi_u32 v0, s12, v0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_addc_u32 s14, s14, s15 +; GCN-NEXT: s_mul_i32 s0, s12, s14 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_add_i32 s0, s1, s0 +; GCN-NEXT: s_mul_i32 s13, s13, s16 +; GCN-NEXT: s_mul_i32 s1, s12, s16 +; GCN-NEXT: s_add_i32 s0, s0, s13 ; GCN-NEXT: v_mov_b32_e32 v2, s1 -; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mul_hi_u32 v3, s14, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s16, v2 +; GCN-NEXT: v_mul_hi_u32 v1, s14, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s16, v0 +; GCN-NEXT: s_mul_i32 s13, s16, s0 +; GCN-NEXT: v_readfirstlane_b32 s17, v2 +; GCN-NEXT: s_add_u32 s13, s17, s13 +; GCN-NEXT: v_readfirstlane_b32 s15, v0 +; GCN-NEXT: s_mul_i32 s1, s14, s1 +; GCN-NEXT: s_addc_u32 s15, 0, s15 +; GCN-NEXT: v_readfirstlane_b32 s12, v3 +; GCN-NEXT: s_add_u32 s1, s13, s1 +; GCN-NEXT: s_addc_u32 s1, s15, s12 +; GCN-NEXT: v_readfirstlane_b32 s12, v1 +; GCN-NEXT: s_addc_u32 s12, s12, 0 +; GCN-NEXT: s_mul_i32 s0, s14, s0 +; GCN-NEXT: s_add_u32 s0, s1, s0 +; GCN-NEXT: s_addc_u32 s12, 0, s12 +; GCN-NEXT: s_add_i32 s15, s16, s0 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_addc_u32 s14, s14, s12 +; GCN-NEXT: s_ashr_i32 s12, s7, 31 +; GCN-NEXT: s_add_u32 s0, s6, s12 +; GCN-NEXT: s_mov_b32 s13, s12 +; GCN-NEXT: s_addc_u32 s1, s7, s12 +; GCN-NEXT: s_xor_b64 s[6:7], s[0:1], s[12:13] +; GCN-NEXT: v_mov_b32_e32 v0, s14 +; GCN-NEXT: v_mul_hi_u32 v1, s6, v0 +; GCN-NEXT: v_mov_b32_e32 v2, s15 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v2 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_readfirstlane_b32 s4, v1 +; GCN-NEXT: v_mul_hi_u32 v1, s7, v2 +; GCN-NEXT: s_mul_i32 s1, s6, s14 +; GCN-NEXT: v_readfirstlane_b32 s16, v3 +; GCN-NEXT: v_mul_hi_u32 v0, s7, v0 +; GCN-NEXT: s_add_u32 s1, s16, s1 +; GCN-NEXT: s_addc_u32 s4, 0, s4 +; GCN-NEXT: s_mul_i32 s15, s7, s15 +; GCN-NEXT: v_readfirstlane_b32 s16, v1 +; GCN-NEXT: s_add_u32 s1, s1, s15 +; GCN-NEXT: s_addc_u32 s1, s4, s16 +; GCN-NEXT: v_readfirstlane_b32 s4, v0 +; GCN-NEXT: s_addc_u32 s4, s4, 0 +; GCN-NEXT: s_mul_i32 s14, s7, s14 +; GCN-NEXT: s_add_u32 s14, s1, s14 +; GCN-NEXT: v_mov_b32_e32 v0, s14 +; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 +; GCN-NEXT: s_addc_u32 s15, 0, s4 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_mul_i32 s4, s10, s15 +; GCN-NEXT: v_readfirstlane_b32 s5, v0 +; GCN-NEXT: s_add_i32 s4, s5, s4 +; GCN-NEXT: s_mul_i32 s5, s11, s14 +; GCN-NEXT: s_add_i32 s16, s4, s5 +; GCN-NEXT: s_sub_i32 s17, s7, s16 +; GCN-NEXT: s_mul_i32 s4, s10, s14 +; GCN-NEXT: s_sub_i32 s6, s6, s4 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s18, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s18, 0 +; GCN-NEXT: s_subb_u32 s17, s17, s11 +; GCN-NEXT: s_sub_i32 s19, s6, s10 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s4, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_subb_u32 s4, s17, 0 +; GCN-NEXT: s_cmp_ge_u32 s4, s11 +; GCN-NEXT: s_cselect_b32 s5, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s19, s10 +; GCN-NEXT: s_cselect_b32 s17, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s4, s11 +; GCN-NEXT: s_cselect_b32 s4, s17, s5 +; GCN-NEXT: s_add_u32 s5, s14, 1 +; GCN-NEXT: s_addc_u32 s17, s15, 0 +; GCN-NEXT: s_add_u32 s19, s14, 2 +; GCN-NEXT: s_addc_u32 s20, s15, 0 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_cselect_b32 s4, s19, s5 +; GCN-NEXT: s_cselect_b32 s5, s20, s17 +; GCN-NEXT: s_cmp_lg_u32 s18, 0 +; GCN-NEXT: s_subb_u32 s7, s7, s16 +; GCN-NEXT: s_cmp_ge_u32 s7, s11 +; GCN-NEXT: s_cselect_b32 s16, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s6, s10 +; GCN-NEXT: s_cselect_b32 s6, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s7, s11 +; GCN-NEXT: s_cselect_b32 s6, s6, s16 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_cselect_b32 s5, s5, s15 +; GCN-NEXT: s_cselect_b32 s4, s4, s14 +; GCN-NEXT: s_xor_b64 s[6:7], s[12:13], s[8:9] +; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] +; GCN-NEXT: s_sub_u32 s4, s4, s6 +; GCN-NEXT: s_subb_u32 s5, s5, s7 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv: @@ -1111,116 +1144,145 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-LABEL: s_test_sdiv_k_num_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_ashr_i32 s8, s3, 31 -; GCN-NEXT: s_add_u32 s2, s2, s8 -; GCN-NEXT: s_mov_b32 s9, s8 -; GCN-NEXT: s_addc_u32 s3, s3, s8 -; GCN-NEXT: s_xor_b64 s[2:3], s[2:3], s[8:9] -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 -; GCN-NEXT: s_sub_u32 s4, 0, s2 -; GCN-NEXT: s_subb_u32 s5, 0, s3 +; GCN-NEXT: s_ashr_i32 s4, s3, 31 +; GCN-NEXT: s_add_u32 s2, s2, s4 +; GCN-NEXT: s_mov_b32 s5, s4 +; GCN-NEXT: s_addc_u32 s3, s3, s4 +; GCN-NEXT: s_xor_b64 s[6:7], s[2:3], s[4:5] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GCN-NEXT: s_sub_u32 s2, 0, s6 +; GCN-NEXT: s_subb_u32 s10, 0, s7 +; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v2, s4, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v5, s5, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s4, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v6, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s4, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s5, v0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s4, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 -; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 -; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 -; GCN-NEXT: v_mov_b32_e32 v4, s3 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_mul_hi_u32 v2, s2, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s2, v0 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v2 -; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v2 -; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v3 -; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1] -; GCN-NEXT: v_add_i32_e64 v4, s[0:1], 1, v0 -; GCN-NEXT: v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1] -; GCN-NEXT: v_add_i32_e64 v6, s[0:1], 2, v0 -; GCN-NEXT: v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1] -; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v6, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 -; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc -; GCN-NEXT: v_xor_b32_e32 v0, s8, v0 -; GCN-NEXT: v_xor_b32_e32 v1, s8, v1 -; GCN-NEXT: v_mov_b32_e32 v2, s8 -; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s8, v0 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_readfirstlane_b32 s11, v1 +; GCN-NEXT: v_readfirstlane_b32 s8, v0 +; GCN-NEXT: s_mul_i32 s9, s2, s11 +; GCN-NEXT: v_readfirstlane_b32 s14, v2 +; GCN-NEXT: s_mul_i32 s12, s10, s8 +; GCN-NEXT: s_mul_i32 s13, s2, s8 +; GCN-NEXT: s_add_i32 s9, s14, s9 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s13 +; GCN-NEXT: s_add_i32 s9, s9, s12 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s9 +; GCN-NEXT: v_mul_hi_u32 v4, v1, s13 +; GCN-NEXT: v_readfirstlane_b32 s12, v3 +; GCN-NEXT: s_mul_i32 s15, s8, s9 +; GCN-NEXT: v_mul_hi_u32 v1, v1, s9 +; GCN-NEXT: s_add_u32 s12, s12, s15 +; GCN-NEXT: v_readfirstlane_b32 s15, v0 +; GCN-NEXT: s_mul_i32 s13, s11, s13 +; GCN-NEXT: s_addc_u32 s15, 0, s15 +; GCN-NEXT: v_readfirstlane_b32 s14, v4 +; GCN-NEXT: s_add_u32 s12, s12, s13 +; GCN-NEXT: s_addc_u32 s12, s15, s14 +; GCN-NEXT: v_readfirstlane_b32 s13, v1 +; GCN-NEXT: s_addc_u32 s13, s13, 0 +; GCN-NEXT: s_mul_i32 s9, s11, s9 +; GCN-NEXT: s_add_u32 s9, s12, s9 +; GCN-NEXT: s_addc_u32 s12, 0, s13 +; GCN-NEXT: s_add_i32 s13, s8, s9 +; GCN-NEXT: v_mov_b32_e32 v0, s13 +; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: s_or_b32 s8, s8, s9 +; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_addc_u32 s11, s11, s12 +; GCN-NEXT: s_mul_i32 s8, s2, s11 +; GCN-NEXT: v_readfirstlane_b32 s9, v0 +; GCN-NEXT: s_add_i32 s8, s9, s8 +; GCN-NEXT: s_mul_i32 s10, s10, s13 +; GCN-NEXT: s_mul_i32 s2, s2, s13 +; GCN-NEXT: s_add_i32 s8, s8, s10 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mul_hi_u32 v3, s11, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s13, v2 +; GCN-NEXT: v_mul_hi_u32 v1, s11, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s13, v0 +; GCN-NEXT: s_mul_i32 s10, s13, s8 +; GCN-NEXT: v_readfirstlane_b32 s14, v2 +; GCN-NEXT: s_add_u32 s10, s14, s10 +; GCN-NEXT: v_readfirstlane_b32 s12, v0 +; GCN-NEXT: s_mul_i32 s2, s11, s2 +; GCN-NEXT: s_addc_u32 s12, 0, s12 +; GCN-NEXT: v_readfirstlane_b32 s9, v3 +; GCN-NEXT: s_add_u32 s2, s10, s2 +; GCN-NEXT: s_addc_u32 s2, s12, s9 +; GCN-NEXT: v_readfirstlane_b32 s9, v1 +; GCN-NEXT: s_addc_u32 s9, s9, 0 +; GCN-NEXT: s_mul_i32 s8, s11, s8 +; GCN-NEXT: s_add_u32 s2, s2, s8 +; GCN-NEXT: s_addc_u32 s10, 0, s9 +; GCN-NEXT: s_add_i32 s13, s13, s2 +; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_or_b32 s2, s8, s9 +; GCN-NEXT: s_cmp_lg_u32 s2, 0 +; GCN-NEXT: s_addc_u32 s8, s11, s10 +; GCN-NEXT: v_mul_hi_u32 v1, s13, 24 +; GCN-NEXT: v_mul_hi_u32 v0, s8, 24 +; GCN-NEXT: s_mul_i32 s8, s8, 24 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_readfirstlane_b32 s10, v1 +; GCN-NEXT: v_readfirstlane_b32 s9, v0 +; GCN-NEXT: s_add_u32 s8, s10, s8 +; GCN-NEXT: s_addc_u32 s10, 0, s9 +; GCN-NEXT: v_mov_b32_e32 v0, s10 +; GCN-NEXT: v_mul_hi_u32 v0, s6, v0 +; GCN-NEXT: s_mul_i32 s8, s7, s10 +; GCN-NEXT: v_readfirstlane_b32 s9, v0 +; GCN-NEXT: s_add_i32 s11, s9, s8 +; GCN-NEXT: s_sub_i32 s12, 0, s11 +; GCN-NEXT: s_mul_i32 s8, s6, s10 +; GCN-NEXT: s_sub_i32 s13, 24, s8 +; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_or_b32 s14, s8, s9 +; GCN-NEXT: s_cmp_lg_u32 s14, 0 +; GCN-NEXT: s_subb_u32 s12, s12, s7 +; GCN-NEXT: s_sub_i32 s15, s13, s6 +; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_or_b32 s8, s8, s9 +; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_subb_u32 s8, s12, 0 +; GCN-NEXT: s_cmp_ge_u32 s8, s7 +; GCN-NEXT: s_cselect_b32 s9, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s15, s6 +; GCN-NEXT: s_cselect_b32 s12, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s8, s7 +; GCN-NEXT: s_cselect_b32 s8, s12, s9 +; GCN-NEXT: s_add_u32 s9, s10, 1 +; GCN-NEXT: s_addc_u32 s12, 0, 0 +; GCN-NEXT: s_add_u32 s15, s10, 2 +; GCN-NEXT: s_addc_u32 s16, 0, 0 +; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_cselect_b32 s8, s15, s9 +; GCN-NEXT: s_cselect_b32 s9, s16, s12 +; GCN-NEXT: s_cmp_lg_u32 s14, 0 +; GCN-NEXT: s_subb_u32 s11, 0, s11 +; GCN-NEXT: s_cmp_ge_u32 s11, s7 +; GCN-NEXT: s_cselect_b32 s12, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s13, s6 +; GCN-NEXT: s_cselect_b32 s6, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s11, s7 +; GCN-NEXT: s_cselect_b32 s6, s6, s12 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_cselect_b32 s7, s9, 0 +; GCN-NEXT: s_cselect_b32 s6, s8, s10 +; GCN-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5] +; GCN-NEXT: s_sub_u32 s6, s6, s4 +; GCN-NEXT: s_subb_u32 s7, s7, s4 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s7 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv_k_num_i64: diff --git a/llvm/test/CodeGen/AMDGPU/srem.ll b/llvm/test/CodeGen/AMDGPU/srem.ll index f614f58d8e1dc..fce960038444a 100644 --- a/llvm/test/CodeGen/AMDGPU/srem.ll +++ b/llvm/test/CodeGen/AMDGPU/srem.ll @@ -1491,29 +1491,29 @@ define amdgpu_kernel void @srem_v4i32_4(ptr addrspace(1) %out, ptr addrspace(1) define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) { ; GCN-LABEL: srem_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[10:11] +; GCN-NEXT: global_load_dwordx4 v[0:3], v0, s[2:3] ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_readfirstlane_b32 s7, v1 -; GCN-NEXT: v_readfirstlane_b32 s6, v0 -; GCN-NEXT: v_readfirstlane_b32 s5, v3 -; GCN-NEXT: v_readfirstlane_b32 s4, v2 -; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[4:5] -; GCN-NEXT: s_mov_b32 s0, 0 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GCN-NEXT: v_readfirstlane_b32 s5, v1 +; GCN-NEXT: v_readfirstlane_b32 s4, v0 +; GCN-NEXT: v_readfirstlane_b32 s3, v3 +; GCN-NEXT: v_readfirstlane_b32 s2, v2 +; GCN-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3] +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GCN-NEXT: s_cbranch_scc0 .LBB8_4 ; GCN-NEXT: ; %bb.1: -; GCN-NEXT: s_ashr_i32 s0, s5, 31 -; GCN-NEXT: s_add_u32 s2, s4, s0 -; GCN-NEXT: s_mov_b32 s1, s0 -; GCN-NEXT: s_addc_u32 s3, s5, s0 -; GCN-NEXT: s_xor_b64 s[12:13], s[2:3], s[0:1] -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 -; GCN-NEXT: s_sub_u32 s0, 0, s12 -; GCN-NEXT: s_subb_u32 s1, 0, s13 +; GCN-NEXT: s_ashr_i32 s6, s3, 31 +; GCN-NEXT: s_add_u32 s8, s2, s6 +; GCN-NEXT: s_mov_b32 s7, s6 +; GCN-NEXT: s_addc_u32 s9, s3, s6 +; GCN-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9 +; GCN-NEXT: s_sub_u32 s3, 0, s8 +; GCN-NEXT: s_subb_u32 s12, 0, s9 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -1522,155 +1522,148 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_readfirstlane_b32 s2, v1 -; GCN-NEXT: v_readfirstlane_b32 s3, v0 -; GCN-NEXT: s_mul_i32 s5, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s15, s0, s3 -; GCN-NEXT: s_mul_i32 s14, s1, s3 -; GCN-NEXT: s_add_i32 s5, s15, s5 -; GCN-NEXT: s_add_i32 s5, s5, s14 -; GCN-NEXT: s_mul_i32 s16, s0, s3 -; GCN-NEXT: s_mul_hi_u32 s14, s3, s5 -; GCN-NEXT: s_mul_i32 s15, s3, s5 -; GCN-NEXT: s_mul_hi_u32 s3, s3, s16 -; GCN-NEXT: s_add_u32 s3, s3, s15 +; GCN-NEXT: v_readfirstlane_b32 s13, v1 +; GCN-NEXT: v_readfirstlane_b32 s10, v0 +; GCN-NEXT: s_mul_i32 s11, s3, s13 +; GCN-NEXT: s_mul_hi_u32 s15, s3, s10 +; GCN-NEXT: s_mul_i32 s14, s12, s10 +; GCN-NEXT: s_add_i32 s11, s15, s11 +; GCN-NEXT: s_add_i32 s11, s11, s14 +; GCN-NEXT: s_mul_i32 s16, s3, s10 +; GCN-NEXT: s_mul_i32 s15, s10, s11 +; GCN-NEXT: s_mul_hi_u32 s17, s10, s16 +; GCN-NEXT: s_mul_hi_u32 s14, s10, s11 +; GCN-NEXT: s_add_u32 s15, s17, s15 ; GCN-NEXT: s_addc_u32 s14, 0, s14 -; GCN-NEXT: s_mul_hi_u32 s17, s2, s16 -; GCN-NEXT: s_mul_i32 s16, s2, s16 -; GCN-NEXT: s_add_u32 s3, s3, s16 -; GCN-NEXT: s_mul_hi_u32 s15, s2, s5 -; GCN-NEXT: s_addc_u32 s3, s14, s17 -; GCN-NEXT: s_addc_u32 s14, s15, 0 -; GCN-NEXT: s_mul_i32 s5, s2, s5 -; GCN-NEXT: s_add_u32 s3, s3, s5 +; GCN-NEXT: s_mul_hi_u32 s18, s13, s16 +; GCN-NEXT: s_mul_i32 s16, s13, s16 +; GCN-NEXT: s_add_u32 s15, s15, s16 +; GCN-NEXT: s_mul_hi_u32 s17, s13, s11 +; GCN-NEXT: s_addc_u32 s14, s14, s18 +; GCN-NEXT: s_addc_u32 s15, s17, 0 +; GCN-NEXT: s_mul_i32 s11, s13, s11 +; GCN-NEXT: s_add_u32 s11, s14, s11 +; GCN-NEXT: s_addc_u32 s14, 0, s15 +; GCN-NEXT: s_add_i32 s15, s10, s11 +; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GCN-NEXT: s_addc_u32 s13, s13, s14 +; GCN-NEXT: s_mul_i32 s10, s3, s13 +; GCN-NEXT: s_mul_hi_u32 s11, s3, s15 +; GCN-NEXT: s_add_i32 s10, s11, s10 +; GCN-NEXT: s_mul_i32 s12, s12, s15 +; GCN-NEXT: s_add_i32 s10, s10, s12 +; GCN-NEXT: s_mul_i32 s3, s3, s15 +; GCN-NEXT: s_mul_hi_u32 s12, s13, s3 +; GCN-NEXT: s_mul_i32 s14, s13, s3 +; GCN-NEXT: s_mul_i32 s17, s15, s10 +; GCN-NEXT: s_mul_hi_u32 s3, s15, s3 +; GCN-NEXT: s_mul_hi_u32 s16, s15, s10 +; GCN-NEXT: s_add_u32 s3, s3, s17 +; GCN-NEXT: s_addc_u32 s16, 0, s16 +; GCN-NEXT: s_add_u32 s3, s3, s14 +; GCN-NEXT: s_mul_hi_u32 s11, s13, s10 +; GCN-NEXT: s_addc_u32 s3, s16, s12 +; GCN-NEXT: s_addc_u32 s11, s11, 0 +; GCN-NEXT: s_mul_i32 s10, s13, s10 +; GCN-NEXT: s_add_u32 s3, s3, s10 +; GCN-NEXT: s_addc_u32 s12, 0, s11 +; GCN-NEXT: s_add_i32 s15, s15, s3 +; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[10:11], 0 +; GCN-NEXT: s_addc_u32 s3, s13, s12 +; GCN-NEXT: s_ashr_i32 s10, s5, 31 +; GCN-NEXT: s_add_u32 s12, s4, s10 +; GCN-NEXT: s_mov_b32 s11, s10 +; GCN-NEXT: s_addc_u32 s13, s5, s10 +; GCN-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11] +; GCN-NEXT: s_mul_i32 s14, s12, s3 +; GCN-NEXT: s_mul_hi_u32 s16, s12, s15 +; GCN-NEXT: s_mul_hi_u32 s5, s12, s3 +; GCN-NEXT: s_add_u32 s14, s16, s14 +; GCN-NEXT: s_addc_u32 s5, 0, s5 +; GCN-NEXT: s_mul_hi_u32 s17, s13, s15 +; GCN-NEXT: s_mul_i32 s15, s13, s15 +; GCN-NEXT: s_add_u32 s14, s14, s15 +; GCN-NEXT: s_mul_hi_u32 s16, s13, s3 +; GCN-NEXT: s_addc_u32 s5, s5, s17 +; GCN-NEXT: s_addc_u32 s14, s16, 0 +; GCN-NEXT: s_mul_i32 s3, s13, s3 +; GCN-NEXT: s_add_u32 s3, s5, s3 ; GCN-NEXT: s_addc_u32 s5, 0, s14 -; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s3, v0 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_addc_u32 s2, s2, s5 -; GCN-NEXT: v_readfirstlane_b32 s5, v0 -; GCN-NEXT: s_mul_i32 s3, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s14, s0, s5 -; GCN-NEXT: s_add_i32 s3, s14, s3 -; GCN-NEXT: s_mul_i32 s1, s1, s5 -; GCN-NEXT: s_add_i32 s3, s3, s1 -; GCN-NEXT: s_mul_i32 s0, s0, s5 -; GCN-NEXT: s_mul_hi_u32 s14, s2, s0 -; GCN-NEXT: s_mul_i32 s15, s2, s0 -; GCN-NEXT: s_mul_i32 s17, s5, s3 -; GCN-NEXT: s_mul_hi_u32 s0, s5, s0 -; GCN-NEXT: s_mul_hi_u32 s16, s5, s3 -; GCN-NEXT: s_add_u32 s0, s0, s17 -; GCN-NEXT: s_addc_u32 s5, 0, s16 -; GCN-NEXT: s_add_u32 s0, s0, s15 -; GCN-NEXT: s_mul_hi_u32 s1, s2, s3 -; GCN-NEXT: s_addc_u32 s0, s5, s14 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_mul_i32 s3, s2, s3 -; GCN-NEXT: s_add_u32 s0, s0, s3 -; GCN-NEXT: s_addc_u32 s1, 0, s1 -; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_addc_u32 s2, s2, s1 -; GCN-NEXT: s_ashr_i32 s14, s7, 31 -; GCN-NEXT: s_add_u32 s0, s6, s14 -; GCN-NEXT: s_mov_b32 s15, s14 -; GCN-NEXT: s_addc_u32 s1, s7, s14 -; GCN-NEXT: s_xor_b64 s[16:17], s[0:1], s[14:15] -; GCN-NEXT: v_readfirstlane_b32 s3, v0 -; GCN-NEXT: s_mul_i32 s1, s16, s2 -; GCN-NEXT: s_mul_hi_u32 s5, s16, s3 -; GCN-NEXT: s_mul_hi_u32 s0, s16, s2 -; GCN-NEXT: s_add_u32 s1, s5, s1 -; GCN-NEXT: s_addc_u32 s0, 0, s0 -; GCN-NEXT: s_mul_hi_u32 s7, s17, s3 -; GCN-NEXT: s_mul_i32 s3, s17, s3 -; GCN-NEXT: s_add_u32 s1, s1, s3 -; GCN-NEXT: s_mul_hi_u32 s5, s17, s2 -; GCN-NEXT: s_addc_u32 s0, s0, s7 -; GCN-NEXT: s_addc_u32 s1, s5, 0 -; GCN-NEXT: s_mul_i32 s2, s17, s2 -; GCN-NEXT: s_add_u32 s0, s0, s2 -; GCN-NEXT: s_addc_u32 s1, 0, s1 -; GCN-NEXT: s_mul_i32 s1, s12, s1 -; GCN-NEXT: s_mul_hi_u32 s2, s12, s0 -; GCN-NEXT: s_add_i32 s1, s2, s1 -; GCN-NEXT: s_mul_i32 s2, s13, s0 -; GCN-NEXT: s_mul_i32 s0, s12, s0 -; GCN-NEXT: s_add_i32 s5, s1, s2 -; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: s_sub_i32 s1, s17, s5 -; GCN-NEXT: v_sub_co_u32_e32 v0, vcc, s16, v0 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_subb_u32 s7, s1, s13 -; GCN-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s12, v0 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_subb_u32 s15, s7, 0 -; GCN-NEXT: s_cmp_ge_u32 s15, s13 -; GCN-NEXT: s_cselect_b32 s16, -1, 0 -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v1 -; GCN-NEXT: s_cmp_eq_u32 s15, s13 -; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[2:3] -; GCN-NEXT: v_mov_b32_e32 v3, s16 -; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[2:3] -; GCN-NEXT: s_subb_u32 s2, s7, s13 -; GCN-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s12, v1 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_subb_u32 s2, s2, 0 -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GCN-NEXT: v_mov_b32_e32 v2, s15 -; GCN-NEXT: v_mov_b32_e32 v3, s2 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; GCN-NEXT: s_subb_u32 s0, s17, s5 -; GCN-NEXT: s_cmp_ge_u32 s0, s13 -; GCN-NEXT: s_cselect_b32 s1, -1, 0 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 -; GCN-NEXT: s_cmp_eq_u32 s0, s13 -; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc -; GCN-NEXT: v_mov_b32_e32 v4, s1 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GCN-NEXT: v_mov_b32_e32 v4, s0 -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GCN-NEXT: v_xor_b32_e32 v0, s14, v0 -; GCN-NEXT: v_xor_b32_e32 v1, s14, v2 -; GCN-NEXT: v_mov_b32_e32 v2, s14 -; GCN-NEXT: v_subrev_co_u32_e32 v0, vcc, s14, v0 -; GCN-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc +; GCN-NEXT: s_mul_i32 s5, s8, s5 +; GCN-NEXT: s_mul_hi_u32 s14, s8, s3 +; GCN-NEXT: s_add_i32 s5, s14, s5 +; GCN-NEXT: s_mul_i32 s14, s9, s3 +; GCN-NEXT: s_add_i32 s5, s5, s14 +; GCN-NEXT: s_sub_i32 s16, s13, s5 +; GCN-NEXT: s_mul_i32 s3, s8, s3 +; GCN-NEXT: s_sub_i32 s3, s12, s3 +; GCN-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 +; GCN-NEXT: s_subb_u32 s12, s16, s9 +; GCN-NEXT: s_sub_i32 s18, s3, s8 +; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_subb_u32 s19, s12, 0 +; GCN-NEXT: s_cmp_ge_u32 s19, s9 +; GCN-NEXT: s_cselect_b32 s20, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s18, s8 +; GCN-NEXT: s_cselect_b32 s21, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s19, s9 +; GCN-NEXT: s_cselect_b32 s20, s21, s20 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_subb_u32 s12, s12, s9 +; GCN-NEXT: s_sub_i32 s21, s18, s8 +; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_subb_u32 s12, s12, 0 +; GCN-NEXT: s_cmp_lg_u32 s20, 0 +; GCN-NEXT: s_cselect_b32 s16, s21, s18 +; GCN-NEXT: s_cselect_b32 s12, s12, s19 +; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 +; GCN-NEXT: s_subb_u32 s5, s13, s5 +; GCN-NEXT: s_cmp_ge_u32 s5, s9 +; GCN-NEXT: s_cselect_b32 s13, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s3, s8 +; GCN-NEXT: s_cselect_b32 s8, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s5, s9 +; GCN-NEXT: s_cselect_b32 s8, s8, s13 +; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_cselect_b32 s9, s12, s5 +; GCN-NEXT: s_cselect_b32 s8, s16, s3 +; GCN-NEXT: s_xor_b64 s[8:9], s[8:9], s[10:11] +; GCN-NEXT: s_sub_u32 s8, s8, s10 +; GCN-NEXT: s_subb_u32 s9, s9, s10 ; GCN-NEXT: s_cbranch_execnz .LBB8_3 ; GCN-NEXT: .LBB8_2: -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: s_sub_i32 s0, 0, s4 -; GCN-NEXT: s_mov_b32 s1, 0 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_sub_i32 s3, 0, s2 +; GCN-NEXT: s_mov_b32 s9, 0 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_readfirstlane_b32 s2, v0 -; GCN-NEXT: s_mul_i32 s0, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s0, s2, s0 -; GCN-NEXT: s_add_i32 s2, s2, s0 -; GCN-NEXT: s_mul_hi_u32 s0, s6, s2 -; GCN-NEXT: s_mul_i32 s0, s0, s4 -; GCN-NEXT: s_sub_i32 s0, s6, s0 -; GCN-NEXT: s_sub_i32 s2, s0, s4 -; GCN-NEXT: s_cmp_ge_u32 s0, s4 -; GCN-NEXT: s_cselect_b32 s0, s2, s0 -; GCN-NEXT: s_sub_i32 s2, s0, s4 -; GCN-NEXT: s_cmp_ge_u32 s0, s4 -; GCN-NEXT: s_cselect_b32 s0, s2, s0 -; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: v_readfirstlane_b32 s5, v0 +; GCN-NEXT: s_mul_i32 s3, s3, s5 +; GCN-NEXT: s_mul_hi_u32 s3, s5, s3 +; GCN-NEXT: s_add_i32 s5, s5, s3 +; GCN-NEXT: s_mul_hi_u32 s3, s4, s5 +; GCN-NEXT: s_mul_i32 s3, s3, s2 +; GCN-NEXT: s_sub_i32 s3, s4, s3 +; GCN-NEXT: s_sub_i32 s4, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s3, s4, s3 +; GCN-NEXT: s_sub_i32 s4, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s8, s4, s3 ; GCN-NEXT: .LBB8_3: +; GCN-NEXT: v_mov_b32_e32 v0, s8 ; GCN-NEXT: v_mov_b32_e32 v2, 0 -; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] +; GCN-NEXT: v_mov_b32_e32 v1, s9 +; GCN-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GCN-NEXT: s_endpgm ; GCN-NEXT: .LBB8_4: -; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GCN-NEXT: ; implicit-def: $sgpr8_sgpr9 ; GCN-NEXT: s_branch .LBB8_2 ; ; TAHITI-LABEL: srem_i64: @@ -1732,7 +1725,7 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; TAHITI-NEXT: v_mul_lo_u32 v8, v8, v5 ; TAHITI-NEXT: v_mul_lo_u32 v7, v7, v5 ; TAHITI-NEXT: v_add_i32_e32 v9, vcc, v9, v10 -; TAHITI-NEXT: v_add_i32_e32 v8, vcc, v9, v8 +; TAHITI-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; TAHITI-NEXT: v_mul_lo_u32 v11, v5, v8 ; TAHITI-NEXT: v_mul_hi_u32 v12, v5, v7 ; TAHITI-NEXT: v_mul_hi_u32 v13, v5, v8 @@ -1819,7 +1812,7 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; TAHITI-NEXT: v_mul_hi_u32 v1, v0, v1 ; TAHITI-NEXT: v_mul_lo_u32 v1, v1, v2 ; TAHITI-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 -; TAHITI-NEXT: v_subrev_i32_e32 v1, vcc, v2, v0 +; TAHITI-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 ; TAHITI-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; TAHITI-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; TAHITI-NEXT: v_sub_i32_e32 v1, vcc, v0, v2 @@ -1836,150 +1829,175 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; ; TONGA-LABEL: srem_i64: ; TONGA: ; %bb.0: -; TONGA-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24 -; TONGA-NEXT: v_mov_b32_e32 v4, 0 +; TONGA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; TONGA-NEXT: s_waitcnt lgkmcnt(0) -; TONGA-NEXT: v_mov_b32_e32 v0, s6 -; TONGA-NEXT: v_mov_b32_e32 v1, s7 +; TONGA-NEXT: v_mov_b32_e32 v0, s2 +; TONGA-NEXT: v_mov_b32_e32 v1, s3 ; TONGA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] ; TONGA-NEXT: s_waitcnt vmcnt(0) -; TONGA-NEXT: v_or_b32_e32 v5, v1, v3 -; TONGA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5] -; TONGA-NEXT: s_cbranch_vccz .LBB8_4 +; TONGA-NEXT: v_readfirstlane_b32 s5, v1 +; TONGA-NEXT: v_readfirstlane_b32 s4, v0 +; TONGA-NEXT: v_readfirstlane_b32 s3, v3 +; TONGA-NEXT: v_readfirstlane_b32 s2, v2 +; TONGA-NEXT: s_or_b64 s[6:7], s[4:5], s[2:3] +; TONGA-NEXT: s_mov_b32 s6, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[6:7], 0 +; TONGA-NEXT: s_cbranch_scc0 .LBB8_3 ; TONGA-NEXT: ; %bb.1: -; TONGA-NEXT: v_ashrrev_i32_e32 v4, 31, v3 -; TONGA-NEXT: v_add_u32_e32 v5, vcc, v2, v4 -; TONGA-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc -; TONGA-NEXT: v_xor_b32_e32 v9, v5, v4 -; TONGA-NEXT: v_xor_b32_e32 v10, v3, v4 -; TONGA-NEXT: v_cvt_f32_u32_e32 v3, v9 -; TONGA-NEXT: v_cvt_f32_u32_e32 v4, v10 -; TONGA-NEXT: v_sub_u32_e32 v11, vcc, 0, v9 -; TONGA-NEXT: v_subb_u32_e32 v12, vcc, 0, v10, vcc -; TONGA-NEXT: v_madmk_f32 v3, v4, 0x4f800000, v3 -; TONGA-NEXT: v_rcp_f32_e32 v3, v3 -; TONGA-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 -; TONGA-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 -; TONGA-NEXT: v_trunc_f32_e32 v4, v4 -; TONGA-NEXT: v_madmk_f32 v3, v4, 0xcf800000, v3 -; TONGA-NEXT: v_cvt_u32_f32_e32 v7, v4 -; TONGA-NEXT: v_cvt_u32_f32_e32 v8, v3 -; TONGA-NEXT: v_mul_lo_u32 v5, v11, v7 -; TONGA-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v11, v8, 0 -; TONGA-NEXT: v_mul_lo_u32 v6, v12, v8 -; TONGA-NEXT: v_add_u32_e32 v4, vcc, v4, v5 -; TONGA-NEXT: v_add_u32_e32 v6, vcc, v4, v6 -; TONGA-NEXT: v_mad_u64_u32 v[4:5], s[0:1], v8, v6, 0 -; TONGA-NEXT: v_mul_hi_u32 v13, v8, v3 -; TONGA-NEXT: v_add_u32_e32 v13, vcc, v13, v4 -; TONGA-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v7, v3, 0 -; TONGA-NEXT: v_addc_u32_e32 v14, vcc, 0, v5, vcc -; TONGA-NEXT: v_mad_u64_u32 v[5:6], s[0:1], v7, v6, 0 -; TONGA-NEXT: v_add_u32_e32 v3, vcc, v13, v3 -; TONGA-NEXT: v_addc_u32_e32 v3, vcc, v14, v4, vcc -; TONGA-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc -; TONGA-NEXT: v_add_u32_e32 v3, vcc, v3, v5 -; TONGA-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; TONGA-NEXT: v_add_u32_e32 v13, vcc, v8, v3 -; TONGA-NEXT: v_addc_u32_e32 v14, vcc, v7, v4, vcc -; TONGA-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v11, v13, 0 -; TONGA-NEXT: v_mul_lo_u32 v7, v11, v14 -; TONGA-NEXT: v_mul_lo_u32 v8, v12, v13 -; TONGA-NEXT: v_mul_hi_u32 v11, v13, v3 -; TONGA-NEXT: v_mad_u64_u32 v[5:6], s[0:1], v14, v3, 0 -; TONGA-NEXT: v_add_u32_e32 v4, vcc, v7, v4 -; TONGA-NEXT: v_add_u32_e32 v4, vcc, v4, v8 -; TONGA-NEXT: v_mad_u64_u32 v[7:8], s[0:1], v13, v4, 0 -; TONGA-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v14, v4, 0 -; TONGA-NEXT: v_add_u32_e32 v7, vcc, v11, v7 -; TONGA-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc -; TONGA-NEXT: v_add_u32_e32 v5, vcc, v7, v5 -; TONGA-NEXT: v_addc_u32_e32 v5, vcc, v8, v6, vcc -; TONGA-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; TONGA-NEXT: v_add_u32_e32 v3, vcc, v5, v3 -; TONGA-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; TONGA-NEXT: v_add_u32_e32 v5, vcc, v13, v3 -; TONGA-NEXT: v_addc_u32_e32 v6, vcc, v14, v4, vcc -; TONGA-NEXT: v_ashrrev_i32_e32 v7, 31, v1 -; TONGA-NEXT: v_add_u32_e32 v3, vcc, v0, v7 -; TONGA-NEXT: v_xor_b32_e32 v8, v3, v7 -; TONGA-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v8, v6, 0 -; TONGA-NEXT: v_mul_hi_u32 v11, v8, v5 -; TONGA-NEXT: v_addc_u32_e32 v1, vcc, v1, v7, vcc -; TONGA-NEXT: v_xor_b32_e32 v1, v1, v7 -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v11, v3 -; TONGA-NEXT: v_addc_u32_e32 v12, vcc, 0, v4, vcc -; TONGA-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v1, v5, 0 -; TONGA-NEXT: v_mad_u64_u32 v[5:6], s[0:1], v1, v6, 0 -; TONGA-NEXT: v_add_u32_e32 v3, vcc, v11, v3 -; TONGA-NEXT: v_addc_u32_e32 v3, vcc, v12, v4, vcc -; TONGA-NEXT: v_addc_u32_e32 v4, vcc, 0, v6, vcc -; TONGA-NEXT: v_add_u32_e32 v5, vcc, v3, v5 -; TONGA-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; TONGA-NEXT: v_mul_lo_u32 v6, v9, v3 -; TONGA-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v9, v5, 0 -; TONGA-NEXT: v_mul_lo_u32 v5, v10, v5 -; TONGA-NEXT: v_add_u32_e32 v4, vcc, v6, v4 -; TONGA-NEXT: v_add_u32_e32 v4, vcc, v5, v4 -; TONGA-NEXT: v_sub_u32_e32 v5, vcc, v1, v4 -; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v8, v3 -; TONGA-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v10, vcc -; TONGA-NEXT: v_sub_u32_e64 v6, s[0:1], v3, v9 -; TONGA-NEXT: v_subbrev_u32_e64 v8, s[2:3], 0, v5, s[0:1] -; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v8, v10 -; TONGA-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[2:3] -; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v6, v9 -; TONGA-NEXT: v_cndmask_b32_e64 v12, 0, -1, s[2:3] -; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v8, v10 -; TONGA-NEXT: v_subb_u32_e64 v5, s[0:1], v5, v10, s[0:1] -; TONGA-NEXT: v_cndmask_b32_e64 v11, v11, v12, s[2:3] -; TONGA-NEXT: v_sub_u32_e64 v12, s[0:1], v6, v9 -; TONGA-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc -; TONGA-NEXT: v_subbrev_u32_e64 v5, s[0:1], 0, v5, s[0:1] -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v10 -; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v11 -; TONGA-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v3, v9 -; TONGA-NEXT: v_cndmask_b32_e64 v5, v8, v5, s[0:1] -; TONGA-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc -; TONGA-NEXT: v_cmp_eq_u32_e32 vcc, v1, v10 -; TONGA-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc -; TONGA-NEXT: v_cndmask_b32_e64 v6, v6, v12, s[0:1] -; TONGA-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; TONGA-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc -; TONGA-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; TONGA-NEXT: v_xor_b32_e32 v3, v3, v7 -; TONGA-NEXT: v_xor_b32_e32 v1, v1, v7 -; TONGA-NEXT: v_sub_u32_e32 v3, vcc, v3, v7 -; TONGA-NEXT: v_subb_u32_e32 v4, vcc, v1, v7, vcc -; TONGA-NEXT: s_cbranch_execnz .LBB8_3 +; TONGA-NEXT: s_ashr_i32 s6, s3, 31 +; TONGA-NEXT: s_add_u32 s8, s2, s6 +; TONGA-NEXT: s_mov_b32 s7, s6 +; TONGA-NEXT: s_addc_u32 s9, s3, s6 +; TONGA-NEXT: s_xor_b64 s[6:7], s[8:9], s[6:7] +; TONGA-NEXT: v_cvt_f32_u32_e32 v0, s6 +; TONGA-NEXT: v_cvt_f32_u32_e32 v1, s7 +; TONGA-NEXT: s_sub_u32 s3, 0, s6 +; TONGA-NEXT: s_subb_u32 s10, 0, s7 +; TONGA-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 +; TONGA-NEXT: v_rcp_f32_e32 v0, v0 +; TONGA-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; TONGA-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; TONGA-NEXT: v_trunc_f32_e32 v1, v1 +; TONGA-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 +; TONGA-NEXT: v_cvt_u32_f32_e32 v4, v1 +; TONGA-NEXT: v_cvt_u32_f32_e32 v5, v0 +; TONGA-NEXT: v_mul_lo_u32 v2, s3, v4 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s3, v5, 0 +; TONGA-NEXT: v_mul_lo_u32 v3, s10, v5 +; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v2 +; TONGA-NEXT: v_add_u32_e32 v3, vcc, v1, v3 +; TONGA-NEXT: v_mul_hi_u32 v6, v5, v0 +; TONGA-NEXT: v_mad_u64_u32 v[1:2], s[8:9], v5, v3, 0 +; TONGA-NEXT: v_add_u32_e32 v6, vcc, v6, v1 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v4, v0, 0 +; TONGA-NEXT: v_addc_u32_e32 v7, vcc, 0, v2, vcc +; TONGA-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v4, v3, 0 +; TONGA-NEXT: v_add_u32_e32 v0, vcc, v6, v0 +; TONGA-NEXT: v_addc_u32_e32 v0, vcc, v7, v1, vcc +; TONGA-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc +; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; TONGA-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; TONGA-NEXT: v_add_u32_e32 v6, vcc, v5, v0 +; TONGA-NEXT: v_addc_u32_e32 v7, vcc, v4, v1, vcc +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s3, v6, 0 +; TONGA-NEXT: v_mul_lo_u32 v4, s3, v7 +; TONGA-NEXT: v_mul_lo_u32 v5, s10, v6 +; TONGA-NEXT: v_mul_hi_u32 v8, v6, v0 +; TONGA-NEXT: v_mad_u64_u32 v[2:3], s[8:9], v7, v0, 0 +; TONGA-NEXT: v_add_u32_e32 v1, vcc, v4, v1 +; TONGA-NEXT: v_add_u32_e32 v1, vcc, v5, v1 +; TONGA-NEXT: v_mad_u64_u32 v[4:5], s[8:9], v6, v1, 0 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v7, v1, 0 +; TONGA-NEXT: v_add_u32_e32 v4, vcc, v8, v4 +; TONGA-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc +; TONGA-NEXT: v_add_u32_e32 v2, vcc, v4, v2 +; TONGA-NEXT: v_addc_u32_e32 v2, vcc, v5, v3, vcc +; TONGA-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; TONGA-NEXT: v_add_u32_e32 v0, vcc, v2, v0 +; TONGA-NEXT: s_ashr_i32 s10, s5, 31 +; TONGA-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; TONGA-NEXT: s_add_u32 s8, s4, s10 +; TONGA-NEXT: v_add_u32_e32 v2, vcc, v6, v0 +; TONGA-NEXT: s_mov_b32 s11, s10 +; TONGA-NEXT: s_addc_u32 s9, s5, s10 +; TONGA-NEXT: v_addc_u32_e32 v3, vcc, v7, v1, vcc +; TONGA-NEXT: s_xor_b64 s[12:13], s[8:9], s[10:11] +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s12, v3, 0 +; TONGA-NEXT: v_mul_hi_u32 v4, s12, v2 +; TONGA-NEXT: v_readfirstlane_b32 s3, v1 +; TONGA-NEXT: v_readfirstlane_b32 s5, v0 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s13, v3, 0 +; TONGA-NEXT: v_mad_u64_u32 v[2:3], s[8:9], s13, v2, 0 +; TONGA-NEXT: v_readfirstlane_b32 s14, v4 +; TONGA-NEXT: s_add_u32 s5, s14, s5 +; TONGA-NEXT: s_addc_u32 s3, 0, s3 +; TONGA-NEXT: v_readfirstlane_b32 s14, v2 +; TONGA-NEXT: v_readfirstlane_b32 s9, v3 +; TONGA-NEXT: s_add_u32 s5, s5, s14 +; TONGA-NEXT: v_readfirstlane_b32 s8, v1 +; TONGA-NEXT: s_addc_u32 s3, s3, s9 +; TONGA-NEXT: s_addc_u32 s5, s8, 0 +; TONGA-NEXT: v_readfirstlane_b32 s8, v0 +; TONGA-NEXT: s_add_u32 s3, s3, s8 +; TONGA-NEXT: v_mov_b32_e32 v0, s3 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s6, v0, 0 +; TONGA-NEXT: s_addc_u32 s5, 0, s5 +; TONGA-NEXT: s_mul_i32 s5, s6, s5 +; TONGA-NEXT: v_readfirstlane_b32 s14, v1 +; TONGA-NEXT: s_add_i32 s5, s14, s5 +; TONGA-NEXT: s_mul_i32 s3, s7, s3 +; TONGA-NEXT: s_add_i32 s5, s5, s3 +; TONGA-NEXT: s_sub_i32 s3, s13, s5 +; TONGA-NEXT: v_readfirstlane_b32 s14, v0 +; TONGA-NEXT: s_sub_i32 s12, s12, s14 +; TONGA-NEXT: s_cselect_b64 s[14:15], 1, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 +; TONGA-NEXT: s_subb_u32 s3, s3, s7 +; TONGA-NEXT: s_sub_i32 s18, s12, s6 +; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 +; TONGA-NEXT: s_subb_u32 s19, s3, 0 +; TONGA-NEXT: s_cmp_ge_u32 s19, s7 +; TONGA-NEXT: s_cselect_b32 s20, -1, 0 +; TONGA-NEXT: s_cmp_ge_u32 s18, s6 +; TONGA-NEXT: s_cselect_b32 s21, -1, 0 +; TONGA-NEXT: s_cmp_eq_u32 s19, s7 +; TONGA-NEXT: s_cselect_b32 s20, s21, s20 +; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 +; TONGA-NEXT: s_subb_u32 s3, s3, s7 +; TONGA-NEXT: s_sub_i32 s21, s18, s6 +; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 +; TONGA-NEXT: s_subb_u32 s3, s3, 0 +; TONGA-NEXT: s_cmp_lg_u32 s20, 0 +; TONGA-NEXT: s_cselect_b32 s16, s21, s18 +; TONGA-NEXT: s_cselect_b32 s3, s3, s19 +; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 +; TONGA-NEXT: s_subb_u32 s5, s13, s5 +; TONGA-NEXT: s_cmp_ge_u32 s5, s7 +; TONGA-NEXT: s_cselect_b32 s13, -1, 0 +; TONGA-NEXT: s_cmp_ge_u32 s12, s6 +; TONGA-NEXT: s_cselect_b32 s6, -1, 0 +; TONGA-NEXT: s_cmp_eq_u32 s5, s7 +; TONGA-NEXT: s_cselect_b32 s6, s6, s13 +; TONGA-NEXT: s_cmp_lg_u32 s6, 0 +; TONGA-NEXT: s_cselect_b32 s7, s3, s5 +; TONGA-NEXT: s_cselect_b32 s6, s16, s12 +; TONGA-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11] +; TONGA-NEXT: s_sub_u32 s6, s6, s10 +; TONGA-NEXT: s_subb_u32 s7, s7, s10 +; TONGA-NEXT: s_cbranch_execnz .LBB8_4 ; TONGA-NEXT: .LBB8_2: -; TONGA-NEXT: v_cvt_f32_u32_e32 v1, v2 -; TONGA-NEXT: v_sub_u32_e32 v3, vcc, 0, v2 -; TONGA-NEXT: v_mov_b32_e32 v4, 0 -; TONGA-NEXT: v_rcp_iflag_f32_e32 v1, v1 -; TONGA-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; TONGA-NEXT: v_cvt_u32_f32_e32 v1, v1 -; TONGA-NEXT: v_mul_lo_u32 v3, v3, v1 -; TONGA-NEXT: v_mul_hi_u32 v3, v1, v3 -; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v3 +; TONGA-NEXT: v_cvt_f32_u32_e32 v0, s2 +; TONGA-NEXT: s_sub_i32 s3, 0, s2 +; TONGA-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; TONGA-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; TONGA-NEXT: v_cvt_u32_f32_e32 v0, v0 +; TONGA-NEXT: v_mul_lo_u32 v1, s3, v0 ; TONGA-NEXT: v_mul_hi_u32 v1, v0, v1 -; TONGA-NEXT: v_mul_lo_u32 v1, v1, v2 -; TONGA-NEXT: v_sub_u32_e32 v0, vcc, v0, v1 -; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v2, v0 -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v1 +; TONGA-NEXT: v_mul_hi_u32 v0, s4, v0 +; TONGA-NEXT: v_mul_lo_u32 v0, v0, s2 +; TONGA-NEXT: v_sub_u32_e32 v0, vcc, s4, v0 +; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, s2, v0 +; TONGA-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 ; TONGA-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v0, v2 -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; TONGA-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc +; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, s2, v0 +; TONGA-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 +; TONGA-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; TONGA-NEXT: v_mov_b32_e32 v1, 0 +; TONGA-NEXT: s_branch .LBB8_5 ; TONGA-NEXT: .LBB8_3: -; TONGA-NEXT: v_mov_b32_e32 v0, s4 -; TONGA-NEXT: v_mov_b32_e32 v1, s5 -; TONGA-NEXT: flat_store_dwordx2 v[0:1], v[3:4] -; TONGA-NEXT: s_endpgm -; TONGA-NEXT: .LBB8_4: -; TONGA-NEXT: ; implicit-def: $vgpr3_vgpr4 +; TONGA-NEXT: ; implicit-def: $sgpr6_sgpr7 ; TONGA-NEXT: s_branch .LBB8_2 +; TONGA-NEXT: .LBB8_4: +; TONGA-NEXT: v_mov_b32_e32 v0, s6 +; TONGA-NEXT: v_mov_b32_e32 v1, s7 +; TONGA-NEXT: .LBB8_5: +; TONGA-NEXT: v_mov_b32_e32 v2, s0 +; TONGA-NEXT: v_mov_b32_e32 v3, s1 +; TONGA-NEXT: flat_store_dwordx2 v[2:3], v[0:1] +; TONGA-NEXT: s_endpgm ; ; EG-LABEL: srem_i64: ; EG: ; %bb.0: @@ -2684,35 +2702,35 @@ define amdgpu_kernel void @srem_i64_4(ptr addrspace(1) %out, ptr addrspace(1) %i define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in) { ; GCN-LABEL: srem_v2i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 ; GCN-NEXT: v_mov_b32_e32 v8, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: global_load_dwordx4 v[0:3], v8, s[10:11] offset:16 -; GCN-NEXT: global_load_dwordx4 v[4:7], v8, s[10:11] +; GCN-NEXT: global_load_dwordx4 v[0:3], v8, s[2:3] offset:16 +; GCN-NEXT: global_load_dwordx4 v[4:7], v8, s[2:3] ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_readfirstlane_b32 s11, v1 -; GCN-NEXT: v_readfirstlane_b32 s10, v0 +; GCN-NEXT: v_readfirstlane_b32 s9, v1 +; GCN-NEXT: v_readfirstlane_b32 s8, v0 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_readfirstlane_b32 s13, v5 -; GCN-NEXT: v_readfirstlane_b32 s12, v4 -; GCN-NEXT: s_or_b64 s[0:1], s[12:13], s[10:11] -; GCN-NEXT: s_mov_b32 s0, 0 -; GCN-NEXT: v_readfirstlane_b32 s5, v3 -; GCN-NEXT: v_readfirstlane_b32 s4, v2 -; GCN-NEXT: v_readfirstlane_b32 s7, v7 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: v_readfirstlane_b32 s6, v6 -; GCN-NEXT: s_cbranch_scc0 .LBB10_7 +; GCN-NEXT: v_readfirstlane_b32 s11, v5 +; GCN-NEXT: v_readfirstlane_b32 s10, v4 +; GCN-NEXT: s_or_b64 s[6:7], s[10:11], s[8:9] +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_readfirstlane_b32 s3, v3 +; GCN-NEXT: v_readfirstlane_b32 s2, v2 +; GCN-NEXT: v_readfirstlane_b32 s5, v7 +; GCN-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GCN-NEXT: v_readfirstlane_b32 s4, v6 +; GCN-NEXT: s_cbranch_scc0 .LBB10_6 ; GCN-NEXT: ; %bb.1: -; GCN-NEXT: s_ashr_i32 s0, s11, 31 -; GCN-NEXT: s_add_u32 s2, s10, s0 -; GCN-NEXT: s_mov_b32 s1, s0 -; GCN-NEXT: s_addc_u32 s3, s11, s0 -; GCN-NEXT: s_xor_b64 s[16:17], s[2:3], s[0:1] -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s16 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s17 -; GCN-NEXT: s_sub_u32 s0, 0, s16 -; GCN-NEXT: s_subb_u32 s1, 0, s17 +; GCN-NEXT: s_ashr_i32 s6, s9, 31 +; GCN-NEXT: s_add_u32 s12, s8, s6 +; GCN-NEXT: s_mov_b32 s7, s6 +; GCN-NEXT: s_addc_u32 s13, s9, s6 +; GCN-NEXT: s_xor_b64 s[6:7], s[12:13], s[6:7] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GCN-NEXT: s_sub_u32 s9, 0, s6 +; GCN-NEXT: s_subb_u32 s16, 0, s7 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -2721,321 +2739,312 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_readfirstlane_b32 s2, v1 -; GCN-NEXT: v_readfirstlane_b32 s3, v0 -; GCN-NEXT: s_mul_i32 s11, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s19, s0, s3 -; GCN-NEXT: s_mul_i32 s18, s1, s3 -; GCN-NEXT: s_add_i32 s11, s19, s11 -; GCN-NEXT: s_add_i32 s11, s11, s18 -; GCN-NEXT: s_mul_i32 s20, s0, s3 -; GCN-NEXT: s_mul_hi_u32 s18, s3, s11 -; GCN-NEXT: s_mul_i32 s19, s3, s11 -; GCN-NEXT: s_mul_hi_u32 s3, s3, s20 -; GCN-NEXT: s_add_u32 s3, s3, s19 +; GCN-NEXT: v_readfirstlane_b32 s17, v1 +; GCN-NEXT: v_readfirstlane_b32 s14, v0 +; GCN-NEXT: s_mul_i32 s15, s9, s17 +; GCN-NEXT: s_mul_hi_u32 s19, s9, s14 +; GCN-NEXT: s_mul_i32 s18, s16, s14 +; GCN-NEXT: s_add_i32 s15, s19, s15 +; GCN-NEXT: s_add_i32 s15, s15, s18 +; GCN-NEXT: s_mul_i32 s20, s9, s14 +; GCN-NEXT: s_mul_i32 s19, s14, s15 +; GCN-NEXT: s_mul_hi_u32 s21, s14, s20 +; GCN-NEXT: s_mul_hi_u32 s18, s14, s15 +; GCN-NEXT: s_add_u32 s19, s21, s19 ; GCN-NEXT: s_addc_u32 s18, 0, s18 -; GCN-NEXT: s_mul_hi_u32 s21, s2, s20 -; GCN-NEXT: s_mul_i32 s20, s2, s20 -; GCN-NEXT: s_add_u32 s3, s3, s20 -; GCN-NEXT: s_mul_hi_u32 s19, s2, s11 -; GCN-NEXT: s_addc_u32 s3, s18, s21 -; GCN-NEXT: s_addc_u32 s18, s19, 0 -; GCN-NEXT: s_mul_i32 s11, s2, s11 -; GCN-NEXT: s_add_u32 s3, s3, s11 +; GCN-NEXT: s_mul_hi_u32 s22, s17, s20 +; GCN-NEXT: s_mul_i32 s20, s17, s20 +; GCN-NEXT: s_add_u32 s19, s19, s20 +; GCN-NEXT: s_mul_hi_u32 s21, s17, s15 +; GCN-NEXT: s_addc_u32 s18, s18, s22 +; GCN-NEXT: s_addc_u32 s19, s21, 0 +; GCN-NEXT: s_mul_i32 s15, s17, s15 +; GCN-NEXT: s_add_u32 s15, s18, s15 +; GCN-NEXT: s_addc_u32 s18, 0, s19 +; GCN-NEXT: s_add_i32 s19, s14, s15 +; GCN-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 +; GCN-NEXT: s_addc_u32 s17, s17, s18 +; GCN-NEXT: s_mul_i32 s14, s9, s17 +; GCN-NEXT: s_mul_hi_u32 s15, s9, s19 +; GCN-NEXT: s_add_i32 s14, s15, s14 +; GCN-NEXT: s_mul_i32 s16, s16, s19 +; GCN-NEXT: s_add_i32 s14, s14, s16 +; GCN-NEXT: s_mul_i32 s9, s9, s19 +; GCN-NEXT: s_mul_hi_u32 s16, s17, s9 +; GCN-NEXT: s_mul_i32 s18, s17, s9 +; GCN-NEXT: s_mul_i32 s21, s19, s14 +; GCN-NEXT: s_mul_hi_u32 s9, s19, s9 +; GCN-NEXT: s_mul_hi_u32 s20, s19, s14 +; GCN-NEXT: s_add_u32 s9, s9, s21 +; GCN-NEXT: s_addc_u32 s20, 0, s20 +; GCN-NEXT: s_add_u32 s9, s9, s18 +; GCN-NEXT: s_mul_hi_u32 s15, s17, s14 +; GCN-NEXT: s_addc_u32 s9, s20, s16 +; GCN-NEXT: s_addc_u32 s15, s15, 0 +; GCN-NEXT: s_mul_i32 s14, s17, s14 +; GCN-NEXT: s_add_u32 s9, s9, s14 +; GCN-NEXT: s_addc_u32 s16, 0, s15 +; GCN-NEXT: s_add_i32 s19, s19, s9 +; GCN-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 +; GCN-NEXT: s_addc_u32 s9, s17, s16 +; GCN-NEXT: s_ashr_i32 s14, s11, 31 +; GCN-NEXT: s_add_u32 s16, s10, s14 +; GCN-NEXT: s_mov_b32 s15, s14 +; GCN-NEXT: s_addc_u32 s17, s11, s14 +; GCN-NEXT: s_xor_b64 s[16:17], s[16:17], s[14:15] +; GCN-NEXT: s_mul_i32 s18, s16, s9 +; GCN-NEXT: s_mul_hi_u32 s20, s16, s19 +; GCN-NEXT: s_mul_hi_u32 s11, s16, s9 +; GCN-NEXT: s_add_u32 s18, s20, s18 +; GCN-NEXT: s_addc_u32 s11, 0, s11 +; GCN-NEXT: s_mul_hi_u32 s21, s17, s19 +; GCN-NEXT: s_mul_i32 s19, s17, s19 +; GCN-NEXT: s_add_u32 s18, s18, s19 +; GCN-NEXT: s_mul_hi_u32 s20, s17, s9 +; GCN-NEXT: s_addc_u32 s11, s11, s21 +; GCN-NEXT: s_addc_u32 s18, s20, 0 +; GCN-NEXT: s_mul_i32 s9, s17, s9 +; GCN-NEXT: s_add_u32 s9, s11, s9 ; GCN-NEXT: s_addc_u32 s11, 0, s18 -; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s3, v0 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_addc_u32 s2, s2, s11 -; GCN-NEXT: v_readfirstlane_b32 s11, v0 -; GCN-NEXT: s_mul_i32 s3, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s18, s0, s11 -; GCN-NEXT: s_add_i32 s3, s18, s3 -; GCN-NEXT: s_mul_i32 s1, s1, s11 -; GCN-NEXT: s_add_i32 s3, s3, s1 -; GCN-NEXT: s_mul_i32 s0, s0, s11 -; GCN-NEXT: s_mul_hi_u32 s18, s2, s0 -; GCN-NEXT: s_mul_i32 s19, s2, s0 -; GCN-NEXT: s_mul_i32 s21, s11, s3 -; GCN-NEXT: s_mul_hi_u32 s0, s11, s0 -; GCN-NEXT: s_mul_hi_u32 s20, s11, s3 -; GCN-NEXT: s_add_u32 s0, s0, s21 -; GCN-NEXT: s_addc_u32 s11, 0, s20 -; GCN-NEXT: s_add_u32 s0, s0, s19 -; GCN-NEXT: s_mul_hi_u32 s1, s2, s3 -; GCN-NEXT: s_addc_u32 s0, s11, s18 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_mul_i32 s3, s2, s3 -; GCN-NEXT: s_add_u32 s0, s0, s3 -; GCN-NEXT: s_addc_u32 s1, 0, s1 -; GCN-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_addc_u32 s2, s2, s1 -; GCN-NEXT: s_ashr_i32 s18, s13, 31 -; GCN-NEXT: s_add_u32 s0, s12, s18 -; GCN-NEXT: s_mov_b32 s19, s18 -; GCN-NEXT: s_addc_u32 s1, s13, s18 -; GCN-NEXT: s_xor_b64 s[20:21], s[0:1], s[18:19] -; GCN-NEXT: v_readfirstlane_b32 s3, v0 -; GCN-NEXT: s_mul_i32 s1, s20, s2 -; GCN-NEXT: s_mul_hi_u32 s11, s20, s3 -; GCN-NEXT: s_mul_hi_u32 s0, s20, s2 -; GCN-NEXT: s_add_u32 s1, s11, s1 -; GCN-NEXT: s_addc_u32 s0, 0, s0 -; GCN-NEXT: s_mul_hi_u32 s13, s21, s3 -; GCN-NEXT: s_mul_i32 s3, s21, s3 -; GCN-NEXT: s_add_u32 s1, s1, s3 -; GCN-NEXT: s_mul_hi_u32 s11, s21, s2 -; GCN-NEXT: s_addc_u32 s0, s0, s13 -; GCN-NEXT: s_addc_u32 s1, s11, 0 -; GCN-NEXT: s_mul_i32 s2, s21, s2 -; GCN-NEXT: s_add_u32 s0, s0, s2 -; GCN-NEXT: s_addc_u32 s1, 0, s1 -; GCN-NEXT: s_mul_i32 s1, s16, s1 -; GCN-NEXT: s_mul_hi_u32 s2, s16, s0 -; GCN-NEXT: s_add_i32 s1, s2, s1 -; GCN-NEXT: s_mul_i32 s2, s17, s0 -; GCN-NEXT: s_mul_i32 s0, s16, s0 -; GCN-NEXT: s_add_i32 s11, s1, s2 -; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: s_sub_i32 s1, s21, s11 -; GCN-NEXT: v_sub_co_u32_e32 v0, vcc, s20, v0 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_subb_u32 s13, s1, s17 -; GCN-NEXT: v_subrev_co_u32_e64 v1, s[0:1], s16, v0 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_subb_u32 s19, s13, 0 -; GCN-NEXT: s_cmp_ge_u32 s19, s17 -; GCN-NEXT: s_cselect_b32 s20, -1, 0 -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s16, v1 -; GCN-NEXT: s_cmp_eq_u32 s19, s17 -; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[2:3] -; GCN-NEXT: v_mov_b32_e32 v3, s20 -; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v3, v2, s[2:3] -; GCN-NEXT: s_subb_u32 s2, s13, s17 -; GCN-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s16, v1 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_subb_u32 s2, s2, 0 -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 -; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] -; GCN-NEXT: v_mov_b32_e32 v2, s19 -; GCN-NEXT: v_mov_b32_e32 v3, s2 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v3, s[0:1] -; GCN-NEXT: s_subb_u32 s0, s21, s11 -; GCN-NEXT: s_cmp_ge_u32 s0, s17 -; GCN-NEXT: s_cselect_b32 s1, -1, 0 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s16, v0 -; GCN-NEXT: s_cmp_eq_u32 s0, s17 -; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc -; GCN-NEXT: v_mov_b32_e32 v4, s1 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 -; GCN-NEXT: v_mov_b32_e32 v4, s0 -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc -; GCN-NEXT: v_xor_b32_e32 v0, s18, v0 -; GCN-NEXT: v_xor_b32_e32 v1, s18, v2 -; GCN-NEXT: v_mov_b32_e32 v2, s18 -; GCN-NEXT: v_subrev_co_u32_e32 v0, vcc, s18, v0 -; GCN-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc +; GCN-NEXT: s_mul_i32 s11, s6, s11 +; GCN-NEXT: s_mul_hi_u32 s18, s6, s9 +; GCN-NEXT: s_add_i32 s11, s18, s11 +; GCN-NEXT: s_mul_i32 s18, s7, s9 +; GCN-NEXT: s_add_i32 s11, s11, s18 +; GCN-NEXT: s_sub_i32 s20, s17, s11 +; GCN-NEXT: s_mul_i32 s9, s6, s9 +; GCN-NEXT: s_sub_i32 s9, s16, s9 +; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 +; GCN-NEXT: s_subb_u32 s16, s20, s7 +; GCN-NEXT: s_sub_i32 s22, s9, s6 +; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 +; GCN-NEXT: s_subb_u32 s23, s16, 0 +; GCN-NEXT: s_cmp_ge_u32 s23, s7 +; GCN-NEXT: s_cselect_b32 s24, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s22, s6 +; GCN-NEXT: s_cselect_b32 s25, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s23, s7 +; GCN-NEXT: s_cselect_b32 s24, s25, s24 +; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 +; GCN-NEXT: s_subb_u32 s16, s16, s7 +; GCN-NEXT: s_sub_i32 s25, s22, s6 +; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 +; GCN-NEXT: s_subb_u32 s16, s16, 0 +; GCN-NEXT: s_cmp_lg_u32 s24, 0 +; GCN-NEXT: s_cselect_b32 s20, s25, s22 +; GCN-NEXT: s_cselect_b32 s16, s16, s23 +; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 +; GCN-NEXT: s_subb_u32 s11, s17, s11 +; GCN-NEXT: s_cmp_ge_u32 s11, s7 +; GCN-NEXT: s_cselect_b32 s17, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s9, s6 +; GCN-NEXT: s_cselect_b32 s6, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s11, s7 +; GCN-NEXT: s_cselect_b32 s6, s6, s17 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_cselect_b32 s7, s16, s11 +; GCN-NEXT: s_cselect_b32 s6, s20, s9 +; GCN-NEXT: s_xor_b64 s[6:7], s[6:7], s[14:15] +; GCN-NEXT: s_sub_u32 s6, s6, s14 +; GCN-NEXT: s_subb_u32 s7, s7, s14 ; GCN-NEXT: s_cbranch_execnz .LBB10_3 ; GCN-NEXT: .LBB10_2: -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10 -; GCN-NEXT: s_sub_i32 s0, 0, s10 -; GCN-NEXT: s_mov_b32 s1, 0 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_sub_i32 s6, 0, s8 +; GCN-NEXT: s_mov_b32 s7, 0 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_readfirstlane_b32 s2, v0 -; GCN-NEXT: s_mul_i32 s0, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s0, s2, s0 -; GCN-NEXT: s_add_i32 s2, s2, s0 -; GCN-NEXT: s_mul_hi_u32 s0, s12, s2 -; GCN-NEXT: s_mul_i32 s0, s0, s10 -; GCN-NEXT: s_sub_i32 s0, s12, s0 -; GCN-NEXT: s_sub_i32 s2, s0, s10 -; GCN-NEXT: s_cmp_ge_u32 s0, s10 -; GCN-NEXT: s_cselect_b32 s0, s2, s0 -; GCN-NEXT: s_sub_i32 s2, s0, s10 -; GCN-NEXT: s_cmp_ge_u32 s0, s10 -; GCN-NEXT: s_cselect_b32 s0, s2, s0 -; GCN-NEXT: v_mov_b32_e32 v0, s0 -; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: v_readfirstlane_b32 s9, v0 +; GCN-NEXT: s_mul_i32 s6, s6, s9 +; GCN-NEXT: s_mul_hi_u32 s6, s9, s6 +; GCN-NEXT: s_add_i32 s9, s9, s6 +; GCN-NEXT: s_mul_hi_u32 s6, s10, s9 +; GCN-NEXT: s_mul_i32 s6, s6, s8 +; GCN-NEXT: s_sub_i32 s6, s10, s6 +; GCN-NEXT: s_sub_i32 s9, s6, s8 +; GCN-NEXT: s_cmp_ge_u32 s6, s8 +; GCN-NEXT: s_cselect_b32 s6, s9, s6 +; GCN-NEXT: s_sub_i32 s9, s6, s8 +; GCN-NEXT: s_cmp_ge_u32 s6, s8 +; GCN-NEXT: s_cselect_b32 s6, s9, s6 ; GCN-NEXT: .LBB10_3: -; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[4:5] -; GCN-NEXT: s_mov_b32 s0, 0 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_cbranch_scc0 .LBB10_8 +; GCN-NEXT: s_or_b64 s[8:9], s[4:5], s[2:3] +; GCN-NEXT: s_mov_b32 s8, 0 +; GCN-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GCN-NEXT: s_cbranch_scc0 .LBB10_7 ; GCN-NEXT: ; %bb.4: -; GCN-NEXT: s_ashr_i32 s0, s5, 31 -; GCN-NEXT: s_add_u32 s2, s4, s0 -; GCN-NEXT: s_mov_b32 s1, s0 -; GCN-NEXT: s_addc_u32 s3, s5, s0 -; GCN-NEXT: s_xor_b64 s[12:13], s[2:3], s[0:1] -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s12 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, s13 -; GCN-NEXT: s_sub_u32 s0, 0, s12 -; GCN-NEXT: s_subb_u32 s1, 0, s13 -; GCN-NEXT: v_madmk_f32 v2, v3, 0x4f800000, v2 -; GCN-NEXT: v_rcp_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 -; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_madmk_f32 v2, v3, 0xcf800000, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_readfirstlane_b32 s2, v3 -; GCN-NEXT: v_readfirstlane_b32 s3, v2 -; GCN-NEXT: s_mul_i32 s5, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s15, s0, s3 -; GCN-NEXT: s_mul_i32 s14, s1, s3 -; GCN-NEXT: s_add_i32 s5, s15, s5 -; GCN-NEXT: s_add_i32 s5, s5, s14 -; GCN-NEXT: s_mul_i32 s16, s0, s3 -; GCN-NEXT: s_mul_hi_u32 s14, s3, s5 -; GCN-NEXT: s_mul_i32 s15, s3, s5 -; GCN-NEXT: s_mul_hi_u32 s3, s3, s16 -; GCN-NEXT: s_add_u32 s3, s3, s15 -; GCN-NEXT: s_addc_u32 s14, 0, s14 -; GCN-NEXT: s_mul_hi_u32 s17, s2, s16 -; GCN-NEXT: s_mul_i32 s16, s2, s16 +; GCN-NEXT: s_ashr_i32 s8, s3, 31 +; GCN-NEXT: s_add_u32 s10, s2, s8 +; GCN-NEXT: s_mov_b32 s9, s8 +; GCN-NEXT: s_addc_u32 s11, s3, s8 +; GCN-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s11 +; GCN-NEXT: s_sub_u32 s3, 0, s10 +; GCN-NEXT: s_subb_u32 s14, 0, s11 +; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_readfirstlane_b32 s15, v1 +; GCN-NEXT: v_readfirstlane_b32 s12, v0 +; GCN-NEXT: s_mul_i32 s13, s3, s15 +; GCN-NEXT: s_mul_hi_u32 s17, s3, s12 +; GCN-NEXT: s_mul_i32 s16, s14, s12 +; GCN-NEXT: s_add_i32 s13, s17, s13 +; GCN-NEXT: s_add_i32 s13, s13, s16 +; GCN-NEXT: s_mul_i32 s18, s3, s12 +; GCN-NEXT: s_mul_i32 s17, s12, s13 +; GCN-NEXT: s_mul_hi_u32 s19, s12, s18 +; GCN-NEXT: s_mul_hi_u32 s16, s12, s13 +; GCN-NEXT: s_add_u32 s17, s19, s17 +; GCN-NEXT: s_addc_u32 s16, 0, s16 +; GCN-NEXT: s_mul_hi_u32 s20, s15, s18 +; GCN-NEXT: s_mul_i32 s18, s15, s18 +; GCN-NEXT: s_add_u32 s17, s17, s18 +; GCN-NEXT: s_mul_hi_u32 s19, s15, s13 +; GCN-NEXT: s_addc_u32 s16, s16, s20 +; GCN-NEXT: s_addc_u32 s17, s19, 0 +; GCN-NEXT: s_mul_i32 s13, s15, s13 +; GCN-NEXT: s_add_u32 s13, s16, s13 +; GCN-NEXT: s_addc_u32 s16, 0, s17 +; GCN-NEXT: s_add_i32 s17, s12, s13 +; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GCN-NEXT: s_addc_u32 s15, s15, s16 +; GCN-NEXT: s_mul_i32 s12, s3, s15 +; GCN-NEXT: s_mul_hi_u32 s13, s3, s17 +; GCN-NEXT: s_add_i32 s12, s13, s12 +; GCN-NEXT: s_mul_i32 s14, s14, s17 +; GCN-NEXT: s_add_i32 s12, s12, s14 +; GCN-NEXT: s_mul_i32 s3, s3, s17 +; GCN-NEXT: s_mul_hi_u32 s14, s15, s3 +; GCN-NEXT: s_mul_i32 s16, s15, s3 +; GCN-NEXT: s_mul_i32 s19, s17, s12 +; GCN-NEXT: s_mul_hi_u32 s3, s17, s3 +; GCN-NEXT: s_mul_hi_u32 s18, s17, s12 +; GCN-NEXT: s_add_u32 s3, s3, s19 +; GCN-NEXT: s_addc_u32 s18, 0, s18 ; GCN-NEXT: s_add_u32 s3, s3, s16 -; GCN-NEXT: s_mul_hi_u32 s15, s2, s5 -; GCN-NEXT: s_addc_u32 s3, s14, s17 -; GCN-NEXT: s_addc_u32 s14, s15, 0 -; GCN-NEXT: s_mul_i32 s5, s2, s5 -; GCN-NEXT: s_add_u32 s3, s3, s5 -; GCN-NEXT: s_addc_u32 s5, 0, s14 -; GCN-NEXT: v_add_co_u32_e32 v2, vcc, s3, v2 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_addc_u32 s2, s2, s5 -; GCN-NEXT: v_readfirstlane_b32 s5, v2 -; GCN-NEXT: s_mul_i32 s3, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s14, s0, s5 -; GCN-NEXT: s_add_i32 s3, s14, s3 -; GCN-NEXT: s_mul_i32 s1, s1, s5 -; GCN-NEXT: s_add_i32 s3, s3, s1 -; GCN-NEXT: s_mul_i32 s0, s0, s5 -; GCN-NEXT: s_mul_hi_u32 s14, s2, s0 -; GCN-NEXT: s_mul_i32 s15, s2, s0 -; GCN-NEXT: s_mul_i32 s17, s5, s3 -; GCN-NEXT: s_mul_hi_u32 s0, s5, s0 -; GCN-NEXT: s_mul_hi_u32 s16, s5, s3 -; GCN-NEXT: s_add_u32 s0, s0, s17 +; GCN-NEXT: s_mul_hi_u32 s13, s15, s12 +; GCN-NEXT: s_addc_u32 s3, s18, s14 +; GCN-NEXT: s_addc_u32 s13, s13, 0 +; GCN-NEXT: s_mul_i32 s12, s15, s12 +; GCN-NEXT: s_add_u32 s3, s3, s12 +; GCN-NEXT: s_addc_u32 s14, 0, s13 +; GCN-NEXT: s_add_i32 s17, s17, s3 +; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GCN-NEXT: s_addc_u32 s3, s15, s14 +; GCN-NEXT: s_ashr_i32 s12, s5, 31 +; GCN-NEXT: s_add_u32 s14, s4, s12 +; GCN-NEXT: s_mov_b32 s13, s12 +; GCN-NEXT: s_addc_u32 s15, s5, s12 +; GCN-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13] +; GCN-NEXT: s_mul_i32 s16, s14, s3 +; GCN-NEXT: s_mul_hi_u32 s18, s14, s17 +; GCN-NEXT: s_mul_hi_u32 s5, s14, s3 +; GCN-NEXT: s_add_u32 s16, s18, s16 +; GCN-NEXT: s_addc_u32 s5, 0, s5 +; GCN-NEXT: s_mul_hi_u32 s19, s15, s17 +; GCN-NEXT: s_mul_i32 s17, s15, s17 +; GCN-NEXT: s_add_u32 s16, s16, s17 +; GCN-NEXT: s_mul_hi_u32 s18, s15, s3 +; GCN-NEXT: s_addc_u32 s5, s5, s19 +; GCN-NEXT: s_addc_u32 s16, s18, 0 +; GCN-NEXT: s_mul_i32 s3, s15, s3 +; GCN-NEXT: s_add_u32 s3, s5, s3 ; GCN-NEXT: s_addc_u32 s5, 0, s16 -; GCN-NEXT: s_add_u32 s0, s0, s15 -; GCN-NEXT: s_mul_hi_u32 s1, s2, s3 -; GCN-NEXT: s_addc_u32 s0, s5, s14 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_mul_i32 s3, s2, s3 -; GCN-NEXT: s_add_u32 s0, s0, s3 -; GCN-NEXT: s_addc_u32 s1, 0, s1 -; GCN-NEXT: v_add_co_u32_e32 v2, vcc, s0, v2 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_addc_u32 s2, s2, s1 -; GCN-NEXT: s_ashr_i32 s14, s7, 31 -; GCN-NEXT: s_add_u32 s0, s6, s14 -; GCN-NEXT: s_mov_b32 s15, s14 -; GCN-NEXT: s_addc_u32 s1, s7, s14 -; GCN-NEXT: s_xor_b64 s[16:17], s[0:1], s[14:15] -; GCN-NEXT: v_readfirstlane_b32 s3, v2 -; GCN-NEXT: s_mul_i32 s1, s16, s2 -; GCN-NEXT: s_mul_hi_u32 s5, s16, s3 -; GCN-NEXT: s_mul_hi_u32 s0, s16, s2 -; GCN-NEXT: s_add_u32 s1, s5, s1 -; GCN-NEXT: s_addc_u32 s0, 0, s0 -; GCN-NEXT: s_mul_hi_u32 s7, s17, s3 -; GCN-NEXT: s_mul_i32 s3, s17, s3 -; GCN-NEXT: s_add_u32 s1, s1, s3 -; GCN-NEXT: s_mul_hi_u32 s5, s17, s2 -; GCN-NEXT: s_addc_u32 s0, s0, s7 -; GCN-NEXT: s_addc_u32 s1, s5, 0 -; GCN-NEXT: s_mul_i32 s2, s17, s2 -; GCN-NEXT: s_add_u32 s0, s0, s2 -; GCN-NEXT: s_addc_u32 s1, 0, s1 -; GCN-NEXT: s_mul_i32 s1, s12, s1 -; GCN-NEXT: s_mul_hi_u32 s2, s12, s0 -; GCN-NEXT: s_add_i32 s1, s2, s1 -; GCN-NEXT: s_mul_i32 s2, s13, s0 -; GCN-NEXT: s_mul_i32 s0, s12, s0 -; GCN-NEXT: s_add_i32 s5, s1, s2 -; GCN-NEXT: v_mov_b32_e32 v2, s0 -; GCN-NEXT: s_sub_i32 s1, s17, s5 -; GCN-NEXT: v_sub_co_u32_e32 v2, vcc, s16, v2 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_subb_u32 s7, s1, s13 -; GCN-NEXT: v_subrev_co_u32_e64 v3, s[0:1], s12, v2 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_subb_u32 s15, s7, 0 -; GCN-NEXT: s_cmp_ge_u32 s15, s13 -; GCN-NEXT: s_cselect_b32 s16, -1, 0 -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v3 -; GCN-NEXT: s_cmp_eq_u32 s15, s13 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[2:3] -; GCN-NEXT: v_mov_b32_e32 v5, s16 -; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[2:3] -; GCN-NEXT: s_subb_u32 s2, s7, s13 -; GCN-NEXT: v_subrev_co_u32_e64 v5, s[0:1], s12, v3 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_subb_u32 s2, s2, 0 -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 -; GCN-NEXT: v_cndmask_b32_e64 v3, v3, v5, s[0:1] -; GCN-NEXT: v_mov_b32_e32 v4, s15 -; GCN-NEXT: v_mov_b32_e32 v5, s2 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: v_cndmask_b32_e64 v4, v4, v5, s[0:1] -; GCN-NEXT: s_subb_u32 s0, s17, s5 -; GCN-NEXT: s_cmp_ge_u32 s0, s13 -; GCN-NEXT: s_cselect_b32 s1, -1, 0 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v2 -; GCN-NEXT: s_cmp_eq_u32 s0, s13 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_mov_b32_e32 v6, s1 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 -; GCN-NEXT: v_mov_b32_e32 v6, s0 -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GCN-NEXT: v_cndmask_b32_e32 v4, v6, v4, vcc -; GCN-NEXT: v_xor_b32_e32 v2, s14, v2 -; GCN-NEXT: v_xor_b32_e32 v3, s14, v4 -; GCN-NEXT: v_mov_b32_e32 v4, s14 -; GCN-NEXT: v_subrev_co_u32_e32 v2, vcc, s14, v2 -; GCN-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc -; GCN-NEXT: s_cbranch_execnz .LBB10_6 +; GCN-NEXT: s_mul_i32 s5, s10, s5 +; GCN-NEXT: s_mul_hi_u32 s16, s10, s3 +; GCN-NEXT: s_add_i32 s5, s16, s5 +; GCN-NEXT: s_mul_i32 s16, s11, s3 +; GCN-NEXT: s_add_i32 s5, s5, s16 +; GCN-NEXT: s_sub_i32 s18, s15, s5 +; GCN-NEXT: s_mul_i32 s3, s10, s3 +; GCN-NEXT: s_sub_i32 s3, s14, s3 +; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_subb_u32 s14, s18, s11 +; GCN-NEXT: s_sub_i32 s20, s3, s10 +; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 +; GCN-NEXT: s_subb_u32 s21, s14, 0 +; GCN-NEXT: s_cmp_ge_u32 s21, s11 +; GCN-NEXT: s_cselect_b32 s22, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s20, s10 +; GCN-NEXT: s_cselect_b32 s23, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s21, s11 +; GCN-NEXT: s_cselect_b32 s22, s23, s22 +; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 +; GCN-NEXT: s_subb_u32 s14, s14, s11 +; GCN-NEXT: s_sub_i32 s23, s20, s10 +; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 +; GCN-NEXT: s_subb_u32 s14, s14, 0 +; GCN-NEXT: s_cmp_lg_u32 s22, 0 +; GCN-NEXT: s_cselect_b32 s18, s23, s20 +; GCN-NEXT: s_cselect_b32 s14, s14, s21 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_subb_u32 s5, s15, s5 +; GCN-NEXT: s_cmp_ge_u32 s5, s11 +; GCN-NEXT: s_cselect_b32 s15, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s3, s10 +; GCN-NEXT: s_cselect_b32 s10, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s5, s11 +; GCN-NEXT: s_cselect_b32 s10, s10, s15 +; GCN-NEXT: s_cmp_lg_u32 s10, 0 +; GCN-NEXT: s_cselect_b32 s11, s14, s5 +; GCN-NEXT: s_cselect_b32 s10, s18, s3 +; GCN-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13] +; GCN-NEXT: s_sub_u32 s10, s10, s12 +; GCN-NEXT: s_subb_u32 s11, s11, s12 +; GCN-NEXT: s_cbranch_execnz .LBB10_8 ; GCN-NEXT: .LBB10_5: -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4 -; GCN-NEXT: s_sub_i32 s0, 0, s4 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 -; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 -; GCN-NEXT: v_mul_lo_u32 v3, s0, v2 -; GCN-NEXT: v_mul_hi_u32 v3, v2, v3 -; GCN-NEXT: v_add_u32_e32 v2, v2, v3 -; GCN-NEXT: v_mul_hi_u32 v2, s6, v2 -; GCN-NEXT: v_mul_lo_u32 v2, v2, s4 -; GCN-NEXT: v_sub_u32_e32 v2, s6, v2 -; GCN-NEXT: v_subrev_u32_e32 v3, s4, v2 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s4, v2 -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; GCN-NEXT: v_subrev_u32_e32 v3, s4, v2 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s4, v2 -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_sub_i32 s3, 0, s2 ; GCN-NEXT: v_mov_b32_e32 v3, 0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: v_add_u32_e32 v0, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 +; GCN-NEXT: v_sub_u32_e32 v0, s4, v0 +; GCN-NEXT: v_subrev_u32_e32 v1, s2, v0 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-NEXT: v_subrev_u32_e32 v1, s2, v0 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 +; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-NEXT: s_branch .LBB10_9 ; GCN-NEXT: .LBB10_6: -; GCN-NEXT: v_mov_b32_e32 v4, 0 -; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] -; GCN-NEXT: s_endpgm -; GCN-NEXT: .LBB10_7: -; GCN-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GCN-NEXT: ; implicit-def: $sgpr6_sgpr7 ; GCN-NEXT: s_branch .LBB10_2 -; GCN-NEXT: .LBB10_8: +; GCN-NEXT: .LBB10_7: +; GCN-NEXT: ; implicit-def: $sgpr10_sgpr11 ; GCN-NEXT: s_branch .LBB10_5 +; GCN-NEXT: .LBB10_8: +; GCN-NEXT: v_mov_b32_e32 v2, s10 +; GCN-NEXT: v_mov_b32_e32 v3, s11 +; GCN-NEXT: .LBB10_9: +; GCN-NEXT: v_mov_b32_e32 v4, 0 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s7 +; GCN-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] +; GCN-NEXT: s_endpgm ; ; TAHITI-LABEL: srem_v2i64: ; TAHITI: ; %bb.0: @@ -3097,7 +3106,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TAHITI-NEXT: v_mul_lo_u32 v12, v12, v9 ; TAHITI-NEXT: v_mul_lo_u32 v11, v11, v9 ; TAHITI-NEXT: v_add_i32_e32 v13, vcc, v13, v14 -; TAHITI-NEXT: v_add_i32_e32 v12, vcc, v13, v12 +; TAHITI-NEXT: v_add_i32_e32 v12, vcc, v12, v13 ; TAHITI-NEXT: v_mul_lo_u32 v15, v9, v12 ; TAHITI-NEXT: v_mul_hi_u32 v16, v9, v11 ; TAHITI-NEXT: v_mul_hi_u32 v17, v9, v12 @@ -3240,7 +3249,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TAHITI-NEXT: v_mul_lo_u32 v10, v10, v3 ; TAHITI-NEXT: v_mul_lo_u32 v5, v5, v3 ; TAHITI-NEXT: v_add_i32_e32 v11, vcc, v11, v12 -; TAHITI-NEXT: v_add_i32_e32 v10, vcc, v11, v10 +; TAHITI-NEXT: v_add_i32_e32 v10, vcc, v10, v11 ; TAHITI-NEXT: v_mul_lo_u32 v13, v3, v10 ; TAHITI-NEXT: v_mul_hi_u32 v14, v3, v5 ; TAHITI-NEXT: v_mul_hi_u32 v15, v3, v10 @@ -3347,152 +3356,181 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-LABEL: srem_v2i64: ; TONGA: ; %bb.0: ; TONGA-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24 -; TONGA-NEXT: v_mov_b32_e32 v8, 0 ; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_add_u32 s0, s6, 16 -; TONGA-NEXT: v_mov_b32_e32 v4, s6 ; TONGA-NEXT: s_addc_u32 s1, s7, 0 ; TONGA-NEXT: v_mov_b32_e32 v0, s0 -; TONGA-NEXT: v_mov_b32_e32 v5, s7 +; TONGA-NEXT: v_mov_b32_e32 v4, s6 ; TONGA-NEXT: v_mov_b32_e32 v1, s1 +; TONGA-NEXT: v_mov_b32_e32 v5, s7 ; TONGA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] ; TONGA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; TONGA-NEXT: s_waitcnt vmcnt(1) +; TONGA-NEXT: v_readfirstlane_b32 s1, v1 +; TONGA-NEXT: v_readfirstlane_b32 s0, v0 ; TONGA-NEXT: s_waitcnt vmcnt(0) -; TONGA-NEXT: v_or_b32_e32 v9, v5, v1 -; TONGA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] -; TONGA-NEXT: s_cbranch_vccz .LBB10_7 +; TONGA-NEXT: v_readfirstlane_b32 s3, v5 +; TONGA-NEXT: v_readfirstlane_b32 s2, v4 +; TONGA-NEXT: s_or_b64 s[6:7], s[2:3], s[0:1] +; TONGA-NEXT: s_mov_b32 s6, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[6:7], 0 +; TONGA-NEXT: s_cbranch_scc0 .LBB10_3 ; TONGA-NEXT: ; %bb.1: -; TONGA-NEXT: v_ashrrev_i32_e32 v8, 31, v1 -; TONGA-NEXT: v_add_u32_e32 v9, vcc, v0, v8 -; TONGA-NEXT: v_addc_u32_e32 v1, vcc, v1, v8, vcc -; TONGA-NEXT: v_xor_b32_e32 v14, v9, v8 -; TONGA-NEXT: v_xor_b32_e32 v1, v1, v8 -; TONGA-NEXT: v_cvt_f32_u32_e32 v8, v14 -; TONGA-NEXT: v_cvt_f32_u32_e32 v9, v1 -; TONGA-NEXT: v_sub_u32_e32 v15, vcc, 0, v14 -; TONGA-NEXT: v_subb_u32_e32 v16, vcc, 0, v1, vcc -; TONGA-NEXT: v_madmk_f32 v8, v9, 0x4f800000, v8 -; TONGA-NEXT: v_rcp_f32_e32 v8, v8 -; TONGA-NEXT: v_mul_f32_e32 v8, 0x5f7ffffc, v8 -; TONGA-NEXT: v_mul_f32_e32 v9, 0x2f800000, v8 -; TONGA-NEXT: v_trunc_f32_e32 v9, v9 -; TONGA-NEXT: v_madmk_f32 v8, v9, 0xcf800000, v8 -; TONGA-NEXT: v_cvt_u32_f32_e32 v12, v9 -; TONGA-NEXT: v_cvt_u32_f32_e32 v13, v8 -; TONGA-NEXT: v_mul_lo_u32 v10, v15, v12 -; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v15, v13, 0 -; TONGA-NEXT: v_mul_lo_u32 v11, v16, v13 -; TONGA-NEXT: v_add_u32_e32 v9, vcc, v9, v10 -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v9, v11 -; TONGA-NEXT: v_mad_u64_u32 v[9:10], s[0:1], v13, v11, 0 -; TONGA-NEXT: v_mul_hi_u32 v17, v13, v8 -; TONGA-NEXT: v_add_u32_e32 v17, vcc, v17, v9 -; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v12, v8, 0 -; TONGA-NEXT: v_addc_u32_e32 v18, vcc, 0, v10, vcc -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v12, v11, 0 -; TONGA-NEXT: v_add_u32_e32 v8, vcc, v17, v8 -; TONGA-NEXT: v_addc_u32_e32 v8, vcc, v18, v9, vcc -; TONGA-NEXT: v_addc_u32_e32 v9, vcc, 0, v11, vcc -; TONGA-NEXT: v_add_u32_e32 v8, vcc, v8, v10 -; TONGA-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc -; TONGA-NEXT: v_add_u32_e32 v17, vcc, v13, v8 -; TONGA-NEXT: v_addc_u32_e32 v18, vcc, v12, v9, vcc -; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v15, v17, 0 -; TONGA-NEXT: v_mul_lo_u32 v12, v15, v18 -; TONGA-NEXT: v_mul_lo_u32 v13, v16, v17 -; TONGA-NEXT: v_mul_hi_u32 v15, v17, v8 -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v18, v8, 0 -; TONGA-NEXT: v_add_u32_e32 v9, vcc, v12, v9 -; TONGA-NEXT: v_add_u32_e32 v9, vcc, v9, v13 -; TONGA-NEXT: v_mad_u64_u32 v[12:13], s[0:1], v17, v9, 0 -; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v18, v9, 0 -; TONGA-NEXT: v_add_u32_e32 v12, vcc, v15, v12 -; TONGA-NEXT: v_addc_u32_e32 v13, vcc, 0, v13, vcc -; TONGA-NEXT: v_add_u32_e32 v10, vcc, v12, v10 -; TONGA-NEXT: v_addc_u32_e32 v10, vcc, v13, v11, vcc -; TONGA-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc -; TONGA-NEXT: v_add_u32_e32 v8, vcc, v10, v8 +; TONGA-NEXT: s_ashr_i32 s6, s1, 31 +; TONGA-NEXT: s_add_u32 s8, s0, s6 +; TONGA-NEXT: s_mov_b32 s7, s6 +; TONGA-NEXT: s_addc_u32 s9, s1, s6 +; TONGA-NEXT: s_xor_b64 s[6:7], s[8:9], s[6:7] +; TONGA-NEXT: v_cvt_f32_u32_e32 v0, s6 +; TONGA-NEXT: v_cvt_f32_u32_e32 v1, s7 +; TONGA-NEXT: s_sub_u32 s1, 0, s6 +; TONGA-NEXT: s_subb_u32 s10, 0, s7 +; TONGA-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 +; TONGA-NEXT: v_rcp_f32_e32 v0, v0 +; TONGA-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; TONGA-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; TONGA-NEXT: v_trunc_f32_e32 v1, v1 +; TONGA-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 +; TONGA-NEXT: v_cvt_u32_f32_e32 v8, v1 +; TONGA-NEXT: v_cvt_u32_f32_e32 v9, v0 +; TONGA-NEXT: v_mul_lo_u32 v4, s1, v8 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s1, v9, 0 +; TONGA-NEXT: v_mul_lo_u32 v5, s10, v9 +; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v4 +; TONGA-NEXT: v_add_u32_e32 v11, vcc, v1, v5 +; TONGA-NEXT: v_mul_hi_u32 v10, v9, v0 +; TONGA-NEXT: v_mad_u64_u32 v[4:5], s[8:9], v9, v11, 0 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v8, v0, 0 +; TONGA-NEXT: v_add_u32_e32 v10, vcc, v10, v4 +; TONGA-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc +; TONGA-NEXT: v_mad_u64_u32 v[4:5], s[8:9], v8, v11, 0 +; TONGA-NEXT: v_add_u32_e32 v0, vcc, v10, v0 +; TONGA-NEXT: v_addc_u32_e32 v0, vcc, v12, v1, vcc +; TONGA-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc +; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v4 +; TONGA-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; TONGA-NEXT: v_add_u32_e32 v10, vcc, v9, v0 +; TONGA-NEXT: v_addc_u32_e32 v11, vcc, v8, v1, vcc +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s1, v10, 0 +; TONGA-NEXT: v_mul_lo_u32 v8, s1, v11 +; TONGA-NEXT: v_mul_lo_u32 v9, s10, v10 +; TONGA-NEXT: v_mul_hi_u32 v12, v10, v0 +; TONGA-NEXT: v_mad_u64_u32 v[4:5], s[8:9], v11, v0, 0 +; TONGA-NEXT: v_add_u32_e32 v1, vcc, v8, v1 +; TONGA-NEXT: v_add_u32_e32 v1, vcc, v9, v1 +; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[8:9], v10, v1, 0 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], v11, v1, 0 +; TONGA-NEXT: v_add_u32_e32 v8, vcc, v12, v8 ; TONGA-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc -; TONGA-NEXT: v_add_u32_e32 v10, vcc, v17, v8 -; TONGA-NEXT: v_addc_u32_e32 v11, vcc, v18, v9, vcc -; TONGA-NEXT: v_ashrrev_i32_e32 v12, 31, v5 -; TONGA-NEXT: v_add_u32_e32 v8, vcc, v4, v12 -; TONGA-NEXT: v_xor_b32_e32 v13, v8, v12 -; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v13, v11, 0 -; TONGA-NEXT: v_mul_hi_u32 v15, v13, v10 -; TONGA-NEXT: v_addc_u32_e32 v5, vcc, v5, v12, vcc -; TONGA-NEXT: v_xor_b32_e32 v5, v5, v12 -; TONGA-NEXT: v_add_u32_e32 v15, vcc, v15, v8 -; TONGA-NEXT: v_addc_u32_e32 v16, vcc, 0, v9, vcc -; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v5, v10, 0 -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v5, v11, 0 -; TONGA-NEXT: v_add_u32_e32 v8, vcc, v15, v8 -; TONGA-NEXT: v_addc_u32_e32 v8, vcc, v16, v9, vcc -; TONGA-NEXT: v_addc_u32_e32 v9, vcc, 0, v11, vcc -; TONGA-NEXT: v_add_u32_e32 v10, vcc, v8, v10 -; TONGA-NEXT: v_addc_u32_e32 v8, vcc, 0, v9, vcc -; TONGA-NEXT: v_mul_lo_u32 v11, v14, v8 -; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[0:1], v14, v10, 0 -; TONGA-NEXT: v_mul_lo_u32 v10, v1, v10 -; TONGA-NEXT: v_add_u32_e32 v9, vcc, v11, v9 -; TONGA-NEXT: v_add_u32_e32 v9, vcc, v10, v9 -; TONGA-NEXT: v_sub_u32_e32 v10, vcc, v5, v9 -; TONGA-NEXT: v_sub_u32_e32 v8, vcc, v13, v8 -; TONGA-NEXT: v_subb_u32_e64 v10, s[0:1], v10, v1, vcc -; TONGA-NEXT: v_sub_u32_e64 v11, s[0:1], v8, v14 -; TONGA-NEXT: v_subbrev_u32_e64 v13, s[2:3], 0, v10, s[0:1] -; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v13, v1 -; TONGA-NEXT: v_cndmask_b32_e64 v15, 0, -1, s[2:3] -; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v11, v14 -; TONGA-NEXT: v_cndmask_b32_e64 v16, 0, -1, s[2:3] -; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v13, v1 -; TONGA-NEXT: v_subb_u32_e64 v10, s[0:1], v10, v1, s[0:1] -; TONGA-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[2:3] -; TONGA-NEXT: v_sub_u32_e64 v16, s[0:1], v11, v14 -; TONGA-NEXT: v_subb_u32_e32 v5, vcc, v5, v9, vcc -; TONGA-NEXT: v_subbrev_u32_e64 v10, s[0:1], 0, v10, s[0:1] -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 -; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v15 -; TONGA-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v8, v14 -; TONGA-NEXT: v_cndmask_b32_e64 v10, v13, v10, s[0:1] -; TONGA-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc -; TONGA-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1 -; TONGA-NEXT: v_cndmask_b32_e32 v1, v9, v13, vcc -; TONGA-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[0:1] -; TONGA-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; TONGA-NEXT: v_cndmask_b32_e32 v1, v5, v10, vcc -; TONGA-NEXT: v_cndmask_b32_e32 v5, v8, v11, vcc -; TONGA-NEXT: v_xor_b32_e32 v5, v5, v12 -; TONGA-NEXT: v_xor_b32_e32 v1, v1, v12 -; TONGA-NEXT: v_sub_u32_e32 v8, vcc, v5, v12 -; TONGA-NEXT: v_subb_u32_e32 v9, vcc, v1, v12, vcc -; TONGA-NEXT: s_cbranch_execnz .LBB10_3 +; TONGA-NEXT: v_add_u32_e32 v4, vcc, v8, v4 +; TONGA-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc +; TONGA-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; TONGA-NEXT: v_add_u32_e32 v0, vcc, v4, v0 +; TONGA-NEXT: s_ashr_i32 s10, s3, 31 +; TONGA-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; TONGA-NEXT: s_add_u32 s8, s2, s10 +; TONGA-NEXT: v_add_u32_e32 v4, vcc, v10, v0 +; TONGA-NEXT: s_mov_b32 s11, s10 +; TONGA-NEXT: s_addc_u32 s9, s3, s10 +; TONGA-NEXT: v_addc_u32_e32 v5, vcc, v11, v1, vcc +; TONGA-NEXT: s_xor_b64 s[12:13], s[8:9], s[10:11] +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s12, v5, 0 +; TONGA-NEXT: v_mul_hi_u32 v8, s12, v4 +; TONGA-NEXT: v_readfirstlane_b32 s1, v1 +; TONGA-NEXT: v_readfirstlane_b32 s3, v0 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s13, v5, 0 +; TONGA-NEXT: v_mad_u64_u32 v[4:5], s[8:9], s13, v4, 0 +; TONGA-NEXT: v_readfirstlane_b32 s14, v8 +; TONGA-NEXT: s_add_u32 s3, s14, s3 +; TONGA-NEXT: s_addc_u32 s1, 0, s1 +; TONGA-NEXT: v_readfirstlane_b32 s14, v4 +; TONGA-NEXT: v_readfirstlane_b32 s9, v5 +; TONGA-NEXT: s_add_u32 s3, s3, s14 +; TONGA-NEXT: v_readfirstlane_b32 s8, v1 +; TONGA-NEXT: s_addc_u32 s1, s1, s9 +; TONGA-NEXT: s_addc_u32 s3, s8, 0 +; TONGA-NEXT: v_readfirstlane_b32 s8, v0 +; TONGA-NEXT: s_add_u32 s1, s1, s8 +; TONGA-NEXT: v_mov_b32_e32 v0, s1 +; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[8:9], s6, v0, 0 +; TONGA-NEXT: s_addc_u32 s3, 0, s3 +; TONGA-NEXT: s_mul_i32 s3, s6, s3 +; TONGA-NEXT: v_readfirstlane_b32 s14, v1 +; TONGA-NEXT: s_add_i32 s3, s14, s3 +; TONGA-NEXT: s_mul_i32 s1, s7, s1 +; TONGA-NEXT: s_add_i32 s3, s3, s1 +; TONGA-NEXT: s_sub_i32 s1, s13, s3 +; TONGA-NEXT: v_readfirstlane_b32 s14, v0 +; TONGA-NEXT: s_sub_i32 s12, s12, s14 +; TONGA-NEXT: s_cselect_b64 s[14:15], 1, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 +; TONGA-NEXT: s_subb_u32 s1, s1, s7 +; TONGA-NEXT: s_sub_i32 s18, s12, s6 +; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 +; TONGA-NEXT: s_subb_u32 s19, s1, 0 +; TONGA-NEXT: s_cmp_ge_u32 s19, s7 +; TONGA-NEXT: s_cselect_b32 s20, -1, 0 +; TONGA-NEXT: s_cmp_ge_u32 s18, s6 +; TONGA-NEXT: s_cselect_b32 s21, -1, 0 +; TONGA-NEXT: s_cmp_eq_u32 s19, s7 +; TONGA-NEXT: s_cselect_b32 s20, s21, s20 +; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 +; TONGA-NEXT: s_subb_u32 s1, s1, s7 +; TONGA-NEXT: s_sub_i32 s21, s18, s6 +; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 +; TONGA-NEXT: s_subb_u32 s1, s1, 0 +; TONGA-NEXT: s_cmp_lg_u32 s20, 0 +; TONGA-NEXT: s_cselect_b32 s16, s21, s18 +; TONGA-NEXT: s_cselect_b32 s1, s1, s19 +; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 +; TONGA-NEXT: s_subb_u32 s3, s13, s3 +; TONGA-NEXT: s_cmp_ge_u32 s3, s7 +; TONGA-NEXT: s_cselect_b32 s13, -1, 0 +; TONGA-NEXT: s_cmp_ge_u32 s12, s6 +; TONGA-NEXT: s_cselect_b32 s6, -1, 0 +; TONGA-NEXT: s_cmp_eq_u32 s3, s7 +; TONGA-NEXT: s_cselect_b32 s6, s6, s13 +; TONGA-NEXT: s_cmp_lg_u32 s6, 0 +; TONGA-NEXT: s_cselect_b32 s7, s1, s3 +; TONGA-NEXT: s_cselect_b32 s6, s16, s12 +; TONGA-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11] +; TONGA-NEXT: s_sub_u32 s6, s6, s10 +; TONGA-NEXT: s_subb_u32 s7, s7, s10 +; TONGA-NEXT: s_cbranch_execnz .LBB10_4 ; TONGA-NEXT: .LBB10_2: -; TONGA-NEXT: v_cvt_f32_u32_e32 v1, v0 -; TONGA-NEXT: v_sub_u32_e32 v5, vcc, 0, v0 +; TONGA-NEXT: v_cvt_f32_u32_e32 v0, s0 +; TONGA-NEXT: s_sub_i32 s1, 0, s0 ; TONGA-NEXT: v_mov_b32_e32 v9, 0 -; TONGA-NEXT: v_rcp_iflag_f32_e32 v1, v1 -; TONGA-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; TONGA-NEXT: v_cvt_u32_f32_e32 v1, v1 -; TONGA-NEXT: v_mul_lo_u32 v5, v5, v1 -; TONGA-NEXT: v_mul_hi_u32 v5, v1, v5 -; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v5 -; TONGA-NEXT: v_mul_hi_u32 v1, v4, v1 -; TONGA-NEXT: v_mul_lo_u32 v1, v1, v0 -; TONGA-NEXT: v_sub_u32_e32 v1, vcc, v4, v1 -; TONGA-NEXT: v_subrev_u32_e32 v4, vcc, v0, v1 -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 -; TONGA-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; TONGA-NEXT: v_sub_u32_e32 v4, vcc, v1, v0 -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 -; TONGA-NEXT: v_cndmask_b32_e32 v8, v1, v4, vcc +; TONGA-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; TONGA-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; TONGA-NEXT: v_cvt_u32_f32_e32 v0, v0 +; TONGA-NEXT: v_mul_lo_u32 v1, s1, v0 +; TONGA-NEXT: v_mul_hi_u32 v1, v0, v1 +; TONGA-NEXT: v_add_u32_e32 v0, vcc, v0, v1 +; TONGA-NEXT: v_mul_hi_u32 v0, s2, v0 +; TONGA-NEXT: v_mul_lo_u32 v0, v0, s0 +; TONGA-NEXT: v_sub_u32_e32 v0, vcc, s2, v0 +; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, s0, v0 +; TONGA-NEXT: v_cmp_le_u32_e32 vcc, s0, v0 +; TONGA-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, s0, v0 +; TONGA-NEXT: v_cmp_le_u32_e32 vcc, s0, v0 +; TONGA-NEXT: v_cndmask_b32_e32 v8, v0, v1, vcc +; TONGA-NEXT: s_branch .LBB10_5 ; TONGA-NEXT: .LBB10_3: +; TONGA-NEXT: ; implicit-def: $sgpr6_sgpr7 +; TONGA-NEXT: s_branch .LBB10_2 +; TONGA-NEXT: .LBB10_4: +; TONGA-NEXT: v_mov_b32_e32 v9, s7 +; TONGA-NEXT: v_mov_b32_e32 v8, s6 +; TONGA-NEXT: .LBB10_5: ; TONGA-NEXT: v_or_b32_e32 v1, v7, v3 ; TONGA-NEXT: v_mov_b32_e32 v0, 0 ; TONGA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] -; TONGA-NEXT: s_cbranch_vccz .LBB10_8 -; TONGA-NEXT: ; %bb.4: +; TONGA-NEXT: s_cbranch_vccz .LBB10_9 +; TONGA-NEXT: ; %bb.6: ; TONGA-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; TONGA-NEXT: v_add_u32_e32 v1, vcc, v2, v0 ; TONGA-NEXT: v_addc_u32_e32 v3, vcc, v3, v0, vcc @@ -3534,7 +3572,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_mul_hi_u32 v13, v15, v0 ; TONGA-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v16, v0, 0 ; TONGA-NEXT: v_add_u32_e32 v1, vcc, v10, v1 -; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v11 +; TONGA-NEXT: v_add_u32_e32 v1, vcc, v11, v1 ; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v15, v1, 0 ; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v16, v1, 0 ; TONGA-NEXT: v_add_u32_e32 v10, vcc, v13, v10 @@ -3598,8 +3636,8 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_xor_b32_e32 v1, v1, v11 ; TONGA-NEXT: v_sub_u32_e32 v10, vcc, v0, v11 ; TONGA-NEXT: v_subb_u32_e32 v11, vcc, v1, v11, vcc -; TONGA-NEXT: s_cbranch_execnz .LBB10_6 -; TONGA-NEXT: .LBB10_5: +; TONGA-NEXT: s_cbranch_execnz .LBB10_8 +; TONGA-NEXT: .LBB10_7: ; TONGA-NEXT: v_cvt_f32_u32_e32 v0, v2 ; TONGA-NEXT: v_sub_u32_e32 v1, vcc, 0, v2 ; TONGA-NEXT: v_mov_b32_e32 v11, 0 @@ -3618,16 +3656,13 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v2, v0 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; TONGA-NEXT: v_cndmask_b32_e32 v10, v0, v1, vcc -; TONGA-NEXT: .LBB10_6: +; TONGA-NEXT: .LBB10_8: ; TONGA-NEXT: v_mov_b32_e32 v0, s4 ; TONGA-NEXT: v_mov_b32_e32 v1, s5 ; TONGA-NEXT: flat_store_dwordx4 v[0:1], v[8:11] ; TONGA-NEXT: s_endpgm -; TONGA-NEXT: .LBB10_7: -; TONGA-NEXT: ; implicit-def: $vgpr8_vgpr9 -; TONGA-NEXT: s_branch .LBB10_2 -; TONGA-NEXT: .LBB10_8: -; TONGA-NEXT: s_branch .LBB10_5 +; TONGA-NEXT: .LBB10_9: +; TONGA-NEXT: s_branch .LBB10_7 ; ; EG-LABEL: srem_v2i64: ; EG: ; %bb.0: @@ -4860,629 +4895,687 @@ define amdgpu_kernel void @srem_v2i64_4(ptr addrspace(1) %out, ptr addrspace(1) define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %in) { ; GCN-LABEL: srem_v4i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24 -; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24 +; GCN-NEXT: v_mov_b32_e32 v16, 0 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: global_load_dwordx4 v[10:13], v8, s[10:11] offset:32 -; GCN-NEXT: global_load_dwordx4 v[14:17], v8, s[10:11] -; GCN-NEXT: global_load_dwordx4 v[0:3], v8, s[10:11] offset:48 -; GCN-NEXT: global_load_dwordx4 v[4:7], v8, s[10:11] offset:16 +; GCN-NEXT: global_load_dwordx4 v[0:3], v16, s[2:3] offset:48 +; GCN-NEXT: global_load_dwordx4 v[4:7], v16, s[2:3] offset:32 +; GCN-NEXT: global_load_dwordx4 v[8:11], v16, s[2:3] offset:16 +; GCN-NEXT: global_load_dwordx4 v[12:15], v16, s[2:3] ; GCN-NEXT: s_waitcnt vmcnt(3) +; GCN-NEXT: v_readfirstlane_b32 s3, v3 +; GCN-NEXT: s_waitcnt vmcnt(2) +; GCN-NEXT: v_readfirstlane_b32 s17, v5 +; GCN-NEXT: v_readfirstlane_b32 s16, v4 +; GCN-NEXT: s_waitcnt vmcnt(0) +; GCN-NEXT: v_readfirstlane_b32 s19, v13 +; GCN-NEXT: v_readfirstlane_b32 s18, v12 +; GCN-NEXT: s_or_b64 s[6:7], s[18:19], s[16:17] +; GCN-NEXT: s_mov_b32 s6, 0 +; GCN-NEXT: v_readfirstlane_b32 s2, v2 +; GCN-NEXT: v_readfirstlane_b32 s9, v1 +; GCN-NEXT: v_readfirstlane_b32 s8, v0 +; GCN-NEXT: v_readfirstlane_b32 s13, v7 +; GCN-NEXT: v_readfirstlane_b32 s12, v6 ; GCN-NEXT: v_readfirstlane_b32 s5, v11 ; GCN-NEXT: v_readfirstlane_b32 s4, v10 -; GCN-NEXT: s_waitcnt vmcnt(2) -; GCN-NEXT: v_readfirstlane_b32 s7, v15 -; GCN-NEXT: v_readfirstlane_b32 s6, v14 -; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[4:5] -; GCN-NEXT: s_mov_b32 s0, 0 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_cbranch_scc0 .LBB12_13 +; GCN-NEXT: v_readfirstlane_b32 s11, v9 +; GCN-NEXT: v_readfirstlane_b32 s10, v8 +; GCN-NEXT: v_readfirstlane_b32 s15, v15 +; GCN-NEXT: s_cmp_lg_u64 s[6:7], 0 +; GCN-NEXT: v_readfirstlane_b32 s14, v14 +; GCN-NEXT: s_cbranch_scc0 .LBB12_6 ; GCN-NEXT: ; %bb.1: -; GCN-NEXT: s_ashr_i32 s0, s5, 31 -; GCN-NEXT: s_add_u32 s2, s4, s0 -; GCN-NEXT: s_mov_b32 s1, s0 -; GCN-NEXT: s_addc_u32 s3, s5, s0 -; GCN-NEXT: s_xor_b64 s[12:13], s[2:3], s[0:1] -; GCN-NEXT: v_cvt_f32_u32_e32 v8, s12 -; GCN-NEXT: v_cvt_f32_u32_e32 v9, s13 -; GCN-NEXT: s_sub_u32 s0, 0, s12 -; GCN-NEXT: s_subb_u32 s1, 0, s13 -; GCN-NEXT: v_madmk_f32 v8, v9, 0x4f800000, v8 -; GCN-NEXT: v_rcp_f32_e32 v8, v8 -; GCN-NEXT: v_mul_f32_e32 v8, 0x5f7ffffc, v8 -; GCN-NEXT: v_mul_f32_e32 v9, 0x2f800000, v8 -; GCN-NEXT: v_trunc_f32_e32 v9, v9 -; GCN-NEXT: v_madmk_f32 v8, v9, 0xcf800000, v8 -; GCN-NEXT: v_cvt_u32_f32_e32 v9, v9 -; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8 -; GCN-NEXT: v_readfirstlane_b32 s2, v9 -; GCN-NEXT: v_readfirstlane_b32 s3, v8 -; GCN-NEXT: s_mul_i32 s5, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s15, s0, s3 -; GCN-NEXT: s_mul_i32 s14, s1, s3 -; GCN-NEXT: s_add_i32 s5, s15, s5 -; GCN-NEXT: s_add_i32 s5, s5, s14 -; GCN-NEXT: s_mul_i32 s16, s0, s3 -; GCN-NEXT: s_mul_hi_u32 s14, s3, s5 -; GCN-NEXT: s_mul_i32 s15, s3, s5 -; GCN-NEXT: s_mul_hi_u32 s3, s3, s16 -; GCN-NEXT: s_add_u32 s3, s3, s15 -; GCN-NEXT: s_addc_u32 s14, 0, s14 -; GCN-NEXT: s_mul_hi_u32 s17, s2, s16 -; GCN-NEXT: s_mul_i32 s16, s2, s16 -; GCN-NEXT: s_add_u32 s3, s3, s16 -; GCN-NEXT: s_mul_hi_u32 s15, s2, s5 -; GCN-NEXT: s_addc_u32 s3, s14, s17 -; GCN-NEXT: s_addc_u32 s14, s15, 0 -; GCN-NEXT: s_mul_i32 s5, s2, s5 -; GCN-NEXT: s_add_u32 s3, s3, s5 -; GCN-NEXT: s_addc_u32 s5, 0, s14 -; GCN-NEXT: v_add_co_u32_e32 v8, vcc, s3, v8 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_addc_u32 s2, s2, s5 -; GCN-NEXT: v_readfirstlane_b32 s5, v8 -; GCN-NEXT: s_mul_i32 s3, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s14, s0, s5 -; GCN-NEXT: s_add_i32 s3, s14, s3 -; GCN-NEXT: s_mul_i32 s1, s1, s5 -; GCN-NEXT: s_add_i32 s3, s3, s1 -; GCN-NEXT: s_mul_i32 s0, s0, s5 -; GCN-NEXT: s_mul_hi_u32 s14, s2, s0 -; GCN-NEXT: s_mul_i32 s15, s2, s0 -; GCN-NEXT: s_mul_i32 s17, s5, s3 -; GCN-NEXT: s_mul_hi_u32 s0, s5, s0 -; GCN-NEXT: s_mul_hi_u32 s16, s5, s3 -; GCN-NEXT: s_add_u32 s0, s0, s17 -; GCN-NEXT: s_addc_u32 s5, 0, s16 -; GCN-NEXT: s_add_u32 s0, s0, s15 -; GCN-NEXT: s_mul_hi_u32 s1, s2, s3 -; GCN-NEXT: s_addc_u32 s0, s5, s14 -; GCN-NEXT: s_addc_u32 s1, s1, 0 -; GCN-NEXT: s_mul_i32 s3, s2, s3 -; GCN-NEXT: s_add_u32 s0, s0, s3 -; GCN-NEXT: s_addc_u32 s1, 0, s1 -; GCN-NEXT: v_add_co_u32_e32 v8, vcc, s0, v8 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_addc_u32 s2, s2, s1 -; GCN-NEXT: s_ashr_i32 s14, s7, 31 -; GCN-NEXT: s_add_u32 s0, s6, s14 -; GCN-NEXT: s_mov_b32 s15, s14 -; GCN-NEXT: s_addc_u32 s1, s7, s14 -; GCN-NEXT: s_xor_b64 s[16:17], s[0:1], s[14:15] -; GCN-NEXT: v_readfirstlane_b32 s3, v8 -; GCN-NEXT: s_mul_i32 s1, s16, s2 -; GCN-NEXT: s_mul_hi_u32 s5, s16, s3 -; GCN-NEXT: s_mul_hi_u32 s0, s16, s2 -; GCN-NEXT: s_add_u32 s1, s5, s1 -; GCN-NEXT: s_addc_u32 s0, 0, s0 -; GCN-NEXT: s_mul_hi_u32 s7, s17, s3 -; GCN-NEXT: s_mul_i32 s3, s17, s3 -; GCN-NEXT: s_add_u32 s1, s1, s3 -; GCN-NEXT: s_mul_hi_u32 s5, s17, s2 -; GCN-NEXT: s_addc_u32 s0, s0, s7 -; GCN-NEXT: s_addc_u32 s1, s5, 0 -; GCN-NEXT: s_mul_i32 s2, s17, s2 -; GCN-NEXT: s_add_u32 s0, s0, s2 -; GCN-NEXT: s_addc_u32 s1, 0, s1 -; GCN-NEXT: s_mul_i32 s1, s12, s1 -; GCN-NEXT: s_mul_hi_u32 s2, s12, s0 -; GCN-NEXT: s_add_i32 s1, s2, s1 -; GCN-NEXT: s_mul_i32 s2, s13, s0 -; GCN-NEXT: s_mul_i32 s0, s12, s0 -; GCN-NEXT: s_add_i32 s5, s1, s2 -; GCN-NEXT: v_mov_b32_e32 v8, s0 -; GCN-NEXT: s_sub_i32 s1, s17, s5 -; GCN-NEXT: v_sub_co_u32_e32 v8, vcc, s16, v8 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: s_subb_u32 s7, s1, s13 -; GCN-NEXT: v_subrev_co_u32_e64 v9, s[0:1], s12, v8 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_subb_u32 s15, s7, 0 -; GCN-NEXT: s_cmp_ge_u32 s15, s13 -; GCN-NEXT: s_cselect_b32 s16, -1, 0 -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v9 -; GCN-NEXT: s_cmp_eq_u32 s15, s13 -; GCN-NEXT: v_cndmask_b32_e64 v10, 0, -1, s[2:3] -; GCN-NEXT: v_mov_b32_e32 v11, s16 -; GCN-NEXT: s_cselect_b64 s[2:3], -1, 0 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: v_cndmask_b32_e64 v10, v11, v10, s[2:3] -; GCN-NEXT: s_subb_u32 s2, s7, s13 -; GCN-NEXT: v_subrev_co_u32_e64 v11, s[0:1], s12, v9 -; GCN-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GCN-NEXT: s_subb_u32 s2, s2, 0 -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v10 -; GCN-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[0:1] -; GCN-NEXT: v_mov_b32_e32 v10, s15 -; GCN-NEXT: v_mov_b32_e32 v11, s2 -; GCN-NEXT: s_cmp_lg_u64 vcc, 0 -; GCN-NEXT: v_cndmask_b32_e64 v10, v10, v11, s[0:1] -; GCN-NEXT: s_subb_u32 s0, s17, s5 -; GCN-NEXT: s_cmp_ge_u32 s0, s13 -; GCN-NEXT: s_cselect_b32 s1, -1, 0 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v8 -; GCN-NEXT: s_cmp_eq_u32 s0, s13 -; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc -; GCN-NEXT: v_mov_b32_e32 v14, s1 -; GCN-NEXT: s_cselect_b64 vcc, -1, 0 -; GCN-NEXT: v_cndmask_b32_e32 v11, v14, v11, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11 -; GCN-NEXT: v_mov_b32_e32 v14, s0 -; GCN-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; GCN-NEXT: v_cndmask_b32_e32 v10, v14, v10, vcc -; GCN-NEXT: v_xor_b32_e32 v8, s14, v8 -; GCN-NEXT: v_xor_b32_e32 v9, s14, v10 -; GCN-NEXT: v_mov_b32_e32 v10, s14 -; GCN-NEXT: v_subrev_co_u32_e32 v8, vcc, s14, v8 -; GCN-NEXT: v_subb_co_u32_e32 v9, vcc, v9, v10, vcc +; GCN-NEXT: s_ashr_i32 s6, s17, 31 +; GCN-NEXT: s_add_u32 s20, s16, s6 +; GCN-NEXT: s_mov_b32 s7, s6 +; GCN-NEXT: s_addc_u32 s21, s17, s6 +; GCN-NEXT: s_xor_b64 s[6:7], s[20:21], s[6:7] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7 +; GCN-NEXT: s_sub_u32 s17, 0, s6 +; GCN-NEXT: s_subb_u32 s24, 0, s7 +; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_readfirstlane_b32 s25, v1 +; GCN-NEXT: v_readfirstlane_b32 s22, v0 +; GCN-NEXT: s_mul_i32 s23, s17, s25 +; GCN-NEXT: s_mul_hi_u32 s27, s17, s22 +; GCN-NEXT: s_mul_i32 s26, s24, s22 +; GCN-NEXT: s_add_i32 s23, s27, s23 +; GCN-NEXT: s_add_i32 s23, s23, s26 +; GCN-NEXT: s_mul_i32 s28, s17, s22 +; GCN-NEXT: s_mul_i32 s27, s22, s23 +; GCN-NEXT: s_mul_hi_u32 s29, s22, s28 +; GCN-NEXT: s_mul_hi_u32 s26, s22, s23 +; GCN-NEXT: s_add_u32 s27, s29, s27 +; GCN-NEXT: s_addc_u32 s26, 0, s26 +; GCN-NEXT: s_mul_hi_u32 s30, s25, s28 +; GCN-NEXT: s_mul_i32 s28, s25, s28 +; GCN-NEXT: s_add_u32 s27, s27, s28 +; GCN-NEXT: s_mul_hi_u32 s29, s25, s23 +; GCN-NEXT: s_addc_u32 s26, s26, s30 +; GCN-NEXT: s_addc_u32 s27, s29, 0 +; GCN-NEXT: s_mul_i32 s23, s25, s23 +; GCN-NEXT: s_add_u32 s23, s26, s23 +; GCN-NEXT: s_addc_u32 s26, 0, s27 +; GCN-NEXT: s_add_i32 s27, s22, s23 +; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 +; GCN-NEXT: s_addc_u32 s25, s25, s26 +; GCN-NEXT: s_mul_i32 s22, s17, s25 +; GCN-NEXT: s_mul_hi_u32 s23, s17, s27 +; GCN-NEXT: s_add_i32 s22, s23, s22 +; GCN-NEXT: s_mul_i32 s24, s24, s27 +; GCN-NEXT: s_add_i32 s22, s22, s24 +; GCN-NEXT: s_mul_i32 s17, s17, s27 +; GCN-NEXT: s_mul_hi_u32 s24, s25, s17 +; GCN-NEXT: s_mul_i32 s26, s25, s17 +; GCN-NEXT: s_mul_i32 s29, s27, s22 +; GCN-NEXT: s_mul_hi_u32 s17, s27, s17 +; GCN-NEXT: s_mul_hi_u32 s28, s27, s22 +; GCN-NEXT: s_add_u32 s17, s17, s29 +; GCN-NEXT: s_addc_u32 s28, 0, s28 +; GCN-NEXT: s_add_u32 s17, s17, s26 +; GCN-NEXT: s_mul_hi_u32 s23, s25, s22 +; GCN-NEXT: s_addc_u32 s17, s28, s24 +; GCN-NEXT: s_addc_u32 s23, s23, 0 +; GCN-NEXT: s_mul_i32 s22, s25, s22 +; GCN-NEXT: s_add_u32 s17, s17, s22 +; GCN-NEXT: s_addc_u32 s24, 0, s23 +; GCN-NEXT: s_add_i32 s27, s27, s17 +; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 +; GCN-NEXT: s_addc_u32 s17, s25, s24 +; GCN-NEXT: s_ashr_i32 s22, s19, 31 +; GCN-NEXT: s_add_u32 s24, s18, s22 +; GCN-NEXT: s_mov_b32 s23, s22 +; GCN-NEXT: s_addc_u32 s25, s19, s22 +; GCN-NEXT: s_xor_b64 s[24:25], s[24:25], s[22:23] +; GCN-NEXT: s_mul_i32 s26, s24, s17 +; GCN-NEXT: s_mul_hi_u32 s28, s24, s27 +; GCN-NEXT: s_mul_hi_u32 s19, s24, s17 +; GCN-NEXT: s_add_u32 s26, s28, s26 +; GCN-NEXT: s_addc_u32 s19, 0, s19 +; GCN-NEXT: s_mul_hi_u32 s29, s25, s27 +; GCN-NEXT: s_mul_i32 s27, s25, s27 +; GCN-NEXT: s_add_u32 s26, s26, s27 +; GCN-NEXT: s_mul_hi_u32 s28, s25, s17 +; GCN-NEXT: s_addc_u32 s19, s19, s29 +; GCN-NEXT: s_addc_u32 s26, s28, 0 +; GCN-NEXT: s_mul_i32 s17, s25, s17 +; GCN-NEXT: s_add_u32 s17, s19, s17 +; GCN-NEXT: s_addc_u32 s19, 0, s26 +; GCN-NEXT: s_mul_i32 s19, s6, s19 +; GCN-NEXT: s_mul_hi_u32 s26, s6, s17 +; GCN-NEXT: s_add_i32 s19, s26, s19 +; GCN-NEXT: s_mul_i32 s26, s7, s17 +; GCN-NEXT: s_add_i32 s19, s19, s26 +; GCN-NEXT: s_sub_i32 s28, s25, s19 +; GCN-NEXT: s_mul_i32 s17, s6, s17 +; GCN-NEXT: s_sub_i32 s17, s24, s17 +; GCN-NEXT: s_cselect_b64 s[26:27], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 +; GCN-NEXT: s_subb_u32 s24, s28, s7 +; GCN-NEXT: s_sub_i32 s30, s17, s6 +; GCN-NEXT: s_cselect_b64 s[28:29], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[28:29], 0 +; GCN-NEXT: s_subb_u32 s31, s24, 0 +; GCN-NEXT: s_cmp_ge_u32 s31, s7 +; GCN-NEXT: s_cselect_b32 s33, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s30, s6 +; GCN-NEXT: s_cselect_b32 s34, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s31, s7 +; GCN-NEXT: s_cselect_b32 s33, s34, s33 +; GCN-NEXT: s_cmp_lg_u64 s[28:29], 0 +; GCN-NEXT: s_subb_u32 s24, s24, s7 +; GCN-NEXT: s_sub_i32 s34, s30, s6 +; GCN-NEXT: s_cselect_b64 s[28:29], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[28:29], 0 +; GCN-NEXT: s_subb_u32 s24, s24, 0 +; GCN-NEXT: s_cmp_lg_u32 s33, 0 +; GCN-NEXT: s_cselect_b32 s28, s34, s30 +; GCN-NEXT: s_cselect_b32 s24, s24, s31 +; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 +; GCN-NEXT: s_subb_u32 s19, s25, s19 +; GCN-NEXT: s_cmp_ge_u32 s19, s7 +; GCN-NEXT: s_cselect_b32 s25, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s17, s6 +; GCN-NEXT: s_cselect_b32 s6, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s19, s7 +; GCN-NEXT: s_cselect_b32 s6, s6, s25 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_cselect_b32 s7, s24, s19 +; GCN-NEXT: s_cselect_b32 s6, s28, s17 +; GCN-NEXT: s_xor_b64 s[6:7], s[6:7], s[22:23] +; GCN-NEXT: s_sub_u32 s6, s6, s22 +; GCN-NEXT: s_subb_u32 s7, s7, s22 ; GCN-NEXT: s_cbranch_execnz .LBB12_3 ; GCN-NEXT: .LBB12_2: -; GCN-NEXT: v_cvt_f32_u32_e32 v8, s4 -; GCN-NEXT: s_sub_i32 s0, 0, s4 -; GCN-NEXT: s_mov_b32 s1, 0 -; GCN-NEXT: v_rcp_iflag_f32_e32 v8, v8 -; GCN-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8 -; GCN-NEXT: v_cvt_u32_f32_e32 v8, v8 -; GCN-NEXT: v_readfirstlane_b32 s2, v8 -; GCN-NEXT: s_mul_i32 s0, s0, s2 -; GCN-NEXT: s_mul_hi_u32 s0, s2, s0 -; GCN-NEXT: s_add_i32 s2, s2, s0 -; GCN-NEXT: s_mul_hi_u32 s0, s6, s2 -; GCN-NEXT: s_mul_i32 s0, s0, s4 -; GCN-NEXT: s_sub_i32 s0, s6, s0 -; GCN-NEXT: s_sub_i32 s2, s0, s4 -; GCN-NEXT: s_cmp_ge_u32 s0, s4 -; GCN-NEXT: s_cselect_b32 s0, s2, s0 -; GCN-NEXT: s_sub_i32 s2, s0, s4 -; GCN-NEXT: s_cmp_ge_u32 s0, s4 -; GCN-NEXT: s_cselect_b32 s0, s2, s0 -; GCN-NEXT: v_mov_b32_e32 v9, s1 -; GCN-NEXT: v_mov_b32_e32 v8, s0 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s16 +; GCN-NEXT: s_sub_i32 s6, 0, s16 +; GCN-NEXT: s_mov_b32 s7, 0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_readfirstlane_b32 s17, v0 +; GCN-NEXT: s_mul_i32 s6, s6, s17 +; GCN-NEXT: s_mul_hi_u32 s6, s17, s6 +; GCN-NEXT: s_add_i32 s17, s17, s6 +; GCN-NEXT: s_mul_hi_u32 s6, s18, s17 +; GCN-NEXT: s_mul_i32 s6, s6, s16 +; GCN-NEXT: s_sub_i32 s6, s18, s6 +; GCN-NEXT: s_sub_i32 s17, s6, s16 +; GCN-NEXT: s_cmp_ge_u32 s6, s16 +; GCN-NEXT: s_cselect_b32 s6, s17, s6 +; GCN-NEXT: s_sub_i32 s17, s6, s16 +; GCN-NEXT: s_cmp_ge_u32 s6, s16 +; GCN-NEXT: s_cselect_b32 s6, s17, s6 ; GCN-NEXT: .LBB12_3: -; GCN-NEXT: v_or_b32_e32 v11, v17, v13 -; GCN-NEXT: v_mov_b32_e32 v10, 0 -; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] -; GCN-NEXT: s_cbranch_vccz .LBB12_14 +; GCN-NEXT: s_or_b64 s[16:17], s[14:15], s[12:13] +; GCN-NEXT: s_mov_b32 s16, 0 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_cbranch_scc0 .LBB12_7 ; GCN-NEXT: ; %bb.4: -; GCN-NEXT: v_ashrrev_i32_e32 v10, 31, v13 -; GCN-NEXT: v_add_co_u32_e32 v11, vcc, v12, v10 -; GCN-NEXT: v_addc_co_u32_e32 v13, vcc, v13, v10, vcc -; GCN-NEXT: v_xor_b32_e32 v11, v11, v10 -; GCN-NEXT: v_xor_b32_e32 v10, v13, v10 -; GCN-NEXT: v_cvt_f32_u32_e32 v13, v11 -; GCN-NEXT: v_cvt_f32_u32_e32 v14, v10 -; GCN-NEXT: v_sub_co_u32_e32 v15, vcc, 0, v11 -; GCN-NEXT: v_subb_co_u32_e32 v18, vcc, 0, v10, vcc -; GCN-NEXT: v_madmk_f32 v13, v14, 0x4f800000, v13 -; GCN-NEXT: v_rcp_f32_e32 v13, v13 -; GCN-NEXT: v_mul_f32_e32 v13, 0x5f7ffffc, v13 -; GCN-NEXT: v_mul_f32_e32 v14, 0x2f800000, v13 -; GCN-NEXT: v_trunc_f32_e32 v14, v14 -; GCN-NEXT: v_madmk_f32 v13, v14, 0xcf800000, v13 -; GCN-NEXT: v_cvt_u32_f32_e32 v14, v14 -; GCN-NEXT: v_cvt_u32_f32_e32 v13, v13 -; GCN-NEXT: v_mul_lo_u32 v20, v15, v14 -; GCN-NEXT: v_mul_hi_u32 v19, v15, v13 -; GCN-NEXT: v_mul_lo_u32 v21, v18, v13 -; GCN-NEXT: v_mul_lo_u32 v22, v15, v13 -; GCN-NEXT: v_add_u32_e32 v19, v19, v20 -; GCN-NEXT: v_add_u32_e32 v19, v19, v21 -; GCN-NEXT: v_mul_lo_u32 v20, v13, v19 -; GCN-NEXT: v_mul_hi_u32 v21, v13, v22 -; GCN-NEXT: v_mul_hi_u32 v23, v13, v19 -; GCN-NEXT: v_mul_hi_u32 v24, v14, v19 -; GCN-NEXT: v_mul_lo_u32 v19, v14, v19 -; GCN-NEXT: v_add_co_u32_e32 v20, vcc, v21, v20 -; GCN-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v23, vcc -; GCN-NEXT: v_mul_lo_u32 v23, v14, v22 -; GCN-NEXT: v_mul_hi_u32 v22, v14, v22 -; GCN-NEXT: v_add_co_u32_e32 v20, vcc, v20, v23 -; GCN-NEXT: v_addc_co_u32_e32 v20, vcc, v21, v22, vcc -; GCN-NEXT: v_addc_co_u32_e32 v21, vcc, 0, v24, vcc -; GCN-NEXT: v_add_co_u32_e32 v19, vcc, v20, v19 -; GCN-NEXT: v_addc_co_u32_e32 v20, vcc, 0, v21, vcc -; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v13, v19 -; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, v14, v20, vcc -; GCN-NEXT: v_mul_lo_u32 v19, v15, v14 -; GCN-NEXT: v_mul_hi_u32 v20, v15, v13 -; GCN-NEXT: v_mul_lo_u32 v18, v18, v13 -; GCN-NEXT: v_mul_lo_u32 v15, v15, v13 -; GCN-NEXT: v_add_u32_e32 v19, v20, v19 -; GCN-NEXT: v_add_u32_e32 v18, v19, v18 -; GCN-NEXT: v_mul_lo_u32 v21, v13, v18 -; GCN-NEXT: v_mul_hi_u32 v22, v13, v15 -; GCN-NEXT: v_mul_hi_u32 v23, v13, v18 -; GCN-NEXT: v_mul_hi_u32 v20, v14, v15 -; GCN-NEXT: v_mul_lo_u32 v15, v14, v15 -; GCN-NEXT: v_mul_hi_u32 v19, v14, v18 -; GCN-NEXT: v_add_co_u32_e32 v21, vcc, v22, v21 -; GCN-NEXT: v_addc_co_u32_e32 v22, vcc, 0, v23, vcc -; GCN-NEXT: v_mul_lo_u32 v18, v14, v18 -; GCN-NEXT: v_add_co_u32_e32 v15, vcc, v21, v15 -; GCN-NEXT: v_addc_co_u32_e32 v15, vcc, v22, v20, vcc -; GCN-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v19, vcc -; GCN-NEXT: v_add_co_u32_e32 v15, vcc, v15, v18 -; GCN-NEXT: v_addc_co_u32_e32 v18, vcc, 0, v19, vcc -; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v13, v15 -; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, v14, v18, vcc -; GCN-NEXT: v_ashrrev_i32_e32 v15, 31, v17 -; GCN-NEXT: v_add_co_u32_e32 v18, vcc, v16, v15 -; GCN-NEXT: v_xor_b32_e32 v18, v18, v15 -; GCN-NEXT: v_mul_lo_u32 v19, v18, v14 -; GCN-NEXT: v_mul_hi_u32 v20, v18, v13 -; GCN-NEXT: v_mul_hi_u32 v21, v18, v14 -; GCN-NEXT: v_addc_co_u32_e32 v17, vcc, v17, v15, vcc -; GCN-NEXT: v_xor_b32_e32 v17, v17, v15 -; GCN-NEXT: v_add_co_u32_e32 v19, vcc, v20, v19 -; GCN-NEXT: v_addc_co_u32_e32 v20, vcc, 0, v21, vcc -; GCN-NEXT: v_mul_lo_u32 v21, v17, v13 -; GCN-NEXT: v_mul_hi_u32 v13, v17, v13 -; GCN-NEXT: v_mul_hi_u32 v22, v17, v14 -; GCN-NEXT: v_mul_lo_u32 v14, v17, v14 -; GCN-NEXT: v_add_co_u32_e32 v19, vcc, v19, v21 -; GCN-NEXT: v_addc_co_u32_e32 v13, vcc, v20, v13, vcc -; GCN-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v22, vcc -; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v13, v14 -; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v19, vcc -; GCN-NEXT: v_mul_lo_u32 v14, v11, v14 -; GCN-NEXT: v_mul_hi_u32 v19, v11, v13 -; GCN-NEXT: v_mul_lo_u32 v20, v10, v13 -; GCN-NEXT: v_mul_lo_u32 v13, v11, v13 -; GCN-NEXT: v_add_u32_e32 v14, v19, v14 -; GCN-NEXT: v_add_u32_e32 v14, v14, v20 -; GCN-NEXT: v_sub_u32_e32 v19, v17, v14 -; GCN-NEXT: v_sub_co_u32_e32 v13, vcc, v18, v13 -; GCN-NEXT: v_subb_co_u32_e64 v18, s[0:1], v19, v10, vcc -; GCN-NEXT: v_sub_co_u32_e64 v19, s[0:1], v13, v11 -; GCN-NEXT: v_subbrev_co_u32_e64 v20, s[2:3], 0, v18, s[0:1] -; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v20, v10 -; GCN-NEXT: v_cndmask_b32_e64 v21, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v19, v11 -; GCN-NEXT: v_subb_co_u32_e32 v14, vcc, v17, v14, vcc -; GCN-NEXT: v_cndmask_b32_e64 v22, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], v20, v10 -; GCN-NEXT: v_subb_co_u32_e64 v18, s[0:1], v18, v10, s[0:1] -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v14, v10 -; GCN-NEXT: v_cndmask_b32_e64 v21, v21, v22, s[2:3] -; GCN-NEXT: v_sub_co_u32_e64 v22, s[0:1], v19, v11 -; GCN-NEXT: v_cndmask_b32_e64 v17, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v13, v11 -; GCN-NEXT: v_subbrev_co_u32_e64 v18, s[0:1], 0, v18, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v14, v10 -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v21 -; GCN-NEXT: v_cndmask_b32_e32 v10, v17, v11, vcc -; GCN-NEXT: v_cndmask_b32_e64 v19, v19, v22, s[0:1] -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 -; GCN-NEXT: v_cndmask_b32_e64 v18, v20, v18, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v11, v13, v19, vcc -; GCN-NEXT: v_cndmask_b32_e32 v10, v14, v18, vcc -; GCN-NEXT: v_xor_b32_e32 v11, v11, v15 -; GCN-NEXT: v_xor_b32_e32 v13, v10, v15 -; GCN-NEXT: v_sub_co_u32_e32 v10, vcc, v11, v15 -; GCN-NEXT: v_subb_co_u32_e32 v11, vcc, v13, v15, vcc -; GCN-NEXT: s_cbranch_execnz .LBB12_6 +; GCN-NEXT: s_ashr_i32 s16, s13, 31 +; GCN-NEXT: s_add_u32 s18, s12, s16 +; GCN-NEXT: s_mov_b32 s17, s16 +; GCN-NEXT: s_addc_u32 s19, s13, s16 +; GCN-NEXT: s_xor_b64 s[18:19], s[18:19], s[16:17] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s18 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s19 +; GCN-NEXT: s_sub_u32 s13, 0, s18 +; GCN-NEXT: s_subb_u32 s22, 0, s19 +; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_readfirstlane_b32 s23, v1 +; GCN-NEXT: v_readfirstlane_b32 s20, v0 +; GCN-NEXT: s_mul_i32 s21, s13, s23 +; GCN-NEXT: s_mul_hi_u32 s25, s13, s20 +; GCN-NEXT: s_mul_i32 s24, s22, s20 +; GCN-NEXT: s_add_i32 s21, s25, s21 +; GCN-NEXT: s_add_i32 s21, s21, s24 +; GCN-NEXT: s_mul_i32 s26, s13, s20 +; GCN-NEXT: s_mul_i32 s25, s20, s21 +; GCN-NEXT: s_mul_hi_u32 s27, s20, s26 +; GCN-NEXT: s_mul_hi_u32 s24, s20, s21 +; GCN-NEXT: s_add_u32 s25, s27, s25 +; GCN-NEXT: s_addc_u32 s24, 0, s24 +; GCN-NEXT: s_mul_hi_u32 s28, s23, s26 +; GCN-NEXT: s_mul_i32 s26, s23, s26 +; GCN-NEXT: s_add_u32 s25, s25, s26 +; GCN-NEXT: s_mul_hi_u32 s27, s23, s21 +; GCN-NEXT: s_addc_u32 s24, s24, s28 +; GCN-NEXT: s_addc_u32 s25, s27, 0 +; GCN-NEXT: s_mul_i32 s21, s23, s21 +; GCN-NEXT: s_add_u32 s21, s24, s21 +; GCN-NEXT: s_addc_u32 s24, 0, s25 +; GCN-NEXT: s_add_i32 s25, s20, s21 +; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 +; GCN-NEXT: s_addc_u32 s23, s23, s24 +; GCN-NEXT: s_mul_i32 s20, s13, s23 +; GCN-NEXT: s_mul_hi_u32 s21, s13, s25 +; GCN-NEXT: s_add_i32 s20, s21, s20 +; GCN-NEXT: s_mul_i32 s22, s22, s25 +; GCN-NEXT: s_add_i32 s20, s20, s22 +; GCN-NEXT: s_mul_i32 s13, s13, s25 +; GCN-NEXT: s_mul_hi_u32 s22, s23, s13 +; GCN-NEXT: s_mul_i32 s24, s23, s13 +; GCN-NEXT: s_mul_i32 s27, s25, s20 +; GCN-NEXT: s_mul_hi_u32 s13, s25, s13 +; GCN-NEXT: s_mul_hi_u32 s26, s25, s20 +; GCN-NEXT: s_add_u32 s13, s13, s27 +; GCN-NEXT: s_addc_u32 s26, 0, s26 +; GCN-NEXT: s_add_u32 s13, s13, s24 +; GCN-NEXT: s_mul_hi_u32 s21, s23, s20 +; GCN-NEXT: s_addc_u32 s13, s26, s22 +; GCN-NEXT: s_addc_u32 s21, s21, 0 +; GCN-NEXT: s_mul_i32 s20, s23, s20 +; GCN-NEXT: s_add_u32 s13, s13, s20 +; GCN-NEXT: s_addc_u32 s22, 0, s21 +; GCN-NEXT: s_add_i32 s25, s25, s13 +; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 +; GCN-NEXT: s_addc_u32 s13, s23, s22 +; GCN-NEXT: s_ashr_i32 s20, s15, 31 +; GCN-NEXT: s_add_u32 s22, s14, s20 +; GCN-NEXT: s_mov_b32 s21, s20 +; GCN-NEXT: s_addc_u32 s23, s15, s20 +; GCN-NEXT: s_xor_b64 s[22:23], s[22:23], s[20:21] +; GCN-NEXT: s_mul_i32 s24, s22, s13 +; GCN-NEXT: s_mul_hi_u32 s26, s22, s25 +; GCN-NEXT: s_mul_hi_u32 s15, s22, s13 +; GCN-NEXT: s_add_u32 s24, s26, s24 +; GCN-NEXT: s_addc_u32 s15, 0, s15 +; GCN-NEXT: s_mul_hi_u32 s27, s23, s25 +; GCN-NEXT: s_mul_i32 s25, s23, s25 +; GCN-NEXT: s_add_u32 s24, s24, s25 +; GCN-NEXT: s_mul_hi_u32 s26, s23, s13 +; GCN-NEXT: s_addc_u32 s15, s15, s27 +; GCN-NEXT: s_addc_u32 s24, s26, 0 +; GCN-NEXT: s_mul_i32 s13, s23, s13 +; GCN-NEXT: s_add_u32 s13, s15, s13 +; GCN-NEXT: s_addc_u32 s15, 0, s24 +; GCN-NEXT: s_mul_i32 s15, s18, s15 +; GCN-NEXT: s_mul_hi_u32 s24, s18, s13 +; GCN-NEXT: s_add_i32 s15, s24, s15 +; GCN-NEXT: s_mul_i32 s24, s19, s13 +; GCN-NEXT: s_add_i32 s15, s15, s24 +; GCN-NEXT: s_sub_i32 s26, s23, s15 +; GCN-NEXT: s_mul_i32 s13, s18, s13 +; GCN-NEXT: s_sub_i32 s13, s22, s13 +; GCN-NEXT: s_cselect_b64 s[24:25], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[24:25], 0 +; GCN-NEXT: s_subb_u32 s22, s26, s19 +; GCN-NEXT: s_sub_i32 s28, s13, s18 +; GCN-NEXT: s_cselect_b64 s[26:27], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 +; GCN-NEXT: s_subb_u32 s29, s22, 0 +; GCN-NEXT: s_cmp_ge_u32 s29, s19 +; GCN-NEXT: s_cselect_b32 s30, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s28, s18 +; GCN-NEXT: s_cselect_b32 s31, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s29, s19 +; GCN-NEXT: s_cselect_b32 s30, s31, s30 +; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 +; GCN-NEXT: s_subb_u32 s22, s22, s19 +; GCN-NEXT: s_sub_i32 s31, s28, s18 +; GCN-NEXT: s_cselect_b64 s[26:27], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 +; GCN-NEXT: s_subb_u32 s22, s22, 0 +; GCN-NEXT: s_cmp_lg_u32 s30, 0 +; GCN-NEXT: s_cselect_b32 s26, s31, s28 +; GCN-NEXT: s_cselect_b32 s22, s22, s29 +; GCN-NEXT: s_cmp_lg_u64 s[24:25], 0 +; GCN-NEXT: s_subb_u32 s15, s23, s15 +; GCN-NEXT: s_cmp_ge_u32 s15, s19 +; GCN-NEXT: s_cselect_b32 s23, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s13, s18 +; GCN-NEXT: s_cselect_b32 s18, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s15, s19 +; GCN-NEXT: s_cselect_b32 s18, s18, s23 +; GCN-NEXT: s_cmp_lg_u32 s18, 0 +; GCN-NEXT: s_cselect_b32 s19, s22, s15 +; GCN-NEXT: s_cselect_b32 s18, s26, s13 +; GCN-NEXT: s_xor_b64 s[18:19], s[18:19], s[20:21] +; GCN-NEXT: s_sub_u32 s18, s18, s20 +; GCN-NEXT: s_subb_u32 s19, s19, s20 +; GCN-NEXT: s_cbranch_execnz .LBB12_8 ; GCN-NEXT: .LBB12_5: -; GCN-NEXT: v_cvt_f32_u32_e32 v10, v12 -; GCN-NEXT: v_sub_u32_e32 v11, 0, v12 -; GCN-NEXT: v_rcp_iflag_f32_e32 v10, v10 -; GCN-NEXT: v_mul_f32_e32 v10, 0x4f7ffffe, v10 -; GCN-NEXT: v_cvt_u32_f32_e32 v10, v10 -; GCN-NEXT: v_mul_lo_u32 v11, v11, v10 -; GCN-NEXT: v_mul_hi_u32 v11, v10, v11 -; GCN-NEXT: v_add_u32_e32 v10, v10, v11 -; GCN-NEXT: v_mul_hi_u32 v10, v16, v10 -; GCN-NEXT: v_mul_lo_u32 v10, v10, v12 -; GCN-NEXT: v_sub_u32_e32 v10, v16, v10 -; GCN-NEXT: v_sub_u32_e32 v11, v10, v12 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v10, v12 -; GCN-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc -; GCN-NEXT: v_sub_u32_e32 v11, v10, v12 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v10, v12 -; GCN-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc -; GCN-NEXT: v_mov_b32_e32 v11, 0 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 +; GCN-NEXT: s_sub_i32 s13, 0, s12 +; GCN-NEXT: v_mov_b32_e32 v3, 0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s13, v0 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: v_add_u32_e32 v0, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s14, v0 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s12 +; GCN-NEXT: v_sub_u32_e32 v0, s14, v0 +; GCN-NEXT: v_subrev_u32_e32 v1, s12, v0 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-NEXT: v_subrev_u32_e32 v1, s12, v0 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 +; GCN-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc +; GCN-NEXT: s_branch .LBB12_9 ; GCN-NEXT: .LBB12_6: -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_or_b32_e32 v13, v5, v1 -; GCN-NEXT: v_mov_b32_e32 v12, 0 -; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] -; GCN-NEXT: s_cbranch_vccz .LBB12_15 -; GCN-NEXT: ; %bb.7: -; GCN-NEXT: v_ashrrev_i32_e32 v13, 31, v1 -; GCN-NEXT: v_add_co_u32_e32 v12, vcc, v0, v13 -; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v13, vcc -; GCN-NEXT: v_xor_b32_e32 v12, v12, v13 -; GCN-NEXT: v_xor_b32_e32 v1, v1, v13 -; GCN-NEXT: v_cvt_f32_u32_e32 v13, v12 -; GCN-NEXT: v_cvt_f32_u32_e32 v14, v1 -; GCN-NEXT: v_sub_co_u32_e32 v15, vcc, 0, v12 -; GCN-NEXT: v_subb_co_u32_e32 v16, vcc, 0, v1, vcc -; GCN-NEXT: v_madmk_f32 v13, v14, 0x4f800000, v13 -; GCN-NEXT: v_rcp_f32_e32 v13, v13 -; GCN-NEXT: v_mul_f32_e32 v13, 0x5f7ffffc, v13 -; GCN-NEXT: v_mul_f32_e32 v14, 0x2f800000, v13 -; GCN-NEXT: v_trunc_f32_e32 v14, v14 -; GCN-NEXT: v_madmk_f32 v13, v14, 0xcf800000, v13 -; GCN-NEXT: v_cvt_u32_f32_e32 v14, v14 -; GCN-NEXT: v_cvt_u32_f32_e32 v13, v13 -; GCN-NEXT: v_mul_lo_u32 v18, v15, v14 -; GCN-NEXT: v_mul_hi_u32 v17, v15, v13 -; GCN-NEXT: v_mul_lo_u32 v19, v16, v13 -; GCN-NEXT: v_mul_lo_u32 v20, v15, v13 -; GCN-NEXT: v_add_u32_e32 v17, v17, v18 -; GCN-NEXT: v_add_u32_e32 v17, v17, v19 -; GCN-NEXT: v_mul_lo_u32 v18, v13, v17 -; GCN-NEXT: v_mul_hi_u32 v19, v13, v20 -; GCN-NEXT: v_mul_hi_u32 v21, v13, v17 -; GCN-NEXT: v_mul_hi_u32 v22, v14, v17 -; GCN-NEXT: v_mul_lo_u32 v17, v14, v17 -; GCN-NEXT: v_add_co_u32_e32 v18, vcc, v19, v18 -; GCN-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v21, vcc -; GCN-NEXT: v_mul_lo_u32 v21, v14, v20 -; GCN-NEXT: v_mul_hi_u32 v20, v14, v20 -; GCN-NEXT: v_add_co_u32_e32 v18, vcc, v18, v21 -; GCN-NEXT: v_addc_co_u32_e32 v18, vcc, v19, v20, vcc -; GCN-NEXT: v_addc_co_u32_e32 v19, vcc, 0, v22, vcc -; GCN-NEXT: v_add_co_u32_e32 v17, vcc, v18, v17 -; GCN-NEXT: v_addc_co_u32_e32 v18, vcc, 0, v19, vcc -; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v13, v17 -; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, v14, v18, vcc -; GCN-NEXT: v_mul_lo_u32 v17, v15, v14 -; GCN-NEXT: v_mul_hi_u32 v18, v15, v13 -; GCN-NEXT: v_mul_lo_u32 v16, v16, v13 -; GCN-NEXT: v_mul_lo_u32 v15, v15, v13 -; GCN-NEXT: v_add_u32_e32 v17, v18, v17 -; GCN-NEXT: v_add_u32_e32 v16, v17, v16 -; GCN-NEXT: v_mul_lo_u32 v19, v13, v16 -; GCN-NEXT: v_mul_hi_u32 v20, v13, v15 -; GCN-NEXT: v_mul_hi_u32 v21, v13, v16 -; GCN-NEXT: v_mul_hi_u32 v18, v14, v15 -; GCN-NEXT: v_mul_lo_u32 v15, v14, v15 -; GCN-NEXT: v_mul_hi_u32 v17, v14, v16 -; GCN-NEXT: v_add_co_u32_e32 v19, vcc, v20, v19 -; GCN-NEXT: v_addc_co_u32_e32 v20, vcc, 0, v21, vcc -; GCN-NEXT: v_mul_lo_u32 v16, v14, v16 -; GCN-NEXT: v_add_co_u32_e32 v15, vcc, v19, v15 -; GCN-NEXT: v_addc_co_u32_e32 v15, vcc, v20, v18, vcc -; GCN-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v17, vcc -; GCN-NEXT: v_add_co_u32_e32 v15, vcc, v15, v16 -; GCN-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v17, vcc -; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v13, v15 -; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, v14, v16, vcc -; GCN-NEXT: v_ashrrev_i32_e32 v15, 31, v5 -; GCN-NEXT: v_add_co_u32_e32 v16, vcc, v4, v15 -; GCN-NEXT: v_xor_b32_e32 v16, v16, v15 -; GCN-NEXT: v_mul_lo_u32 v17, v16, v14 -; GCN-NEXT: v_mul_hi_u32 v18, v16, v13 -; GCN-NEXT: v_mul_hi_u32 v19, v16, v14 -; GCN-NEXT: v_addc_co_u32_e32 v5, vcc, v5, v15, vcc -; GCN-NEXT: v_xor_b32_e32 v5, v5, v15 -; GCN-NEXT: v_add_co_u32_e32 v17, vcc, v18, v17 -; GCN-NEXT: v_addc_co_u32_e32 v18, vcc, 0, v19, vcc -; GCN-NEXT: v_mul_lo_u32 v19, v5, v13 -; GCN-NEXT: v_mul_hi_u32 v13, v5, v13 -; GCN-NEXT: v_mul_hi_u32 v20, v5, v14 -; GCN-NEXT: v_mul_lo_u32 v14, v5, v14 -; GCN-NEXT: v_add_co_u32_e32 v17, vcc, v17, v19 -; GCN-NEXT: v_addc_co_u32_e32 v13, vcc, v18, v13, vcc -; GCN-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v20, vcc -; GCN-NEXT: v_add_co_u32_e32 v13, vcc, v13, v14 -; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v17, vcc -; GCN-NEXT: v_mul_lo_u32 v14, v12, v14 -; GCN-NEXT: v_mul_hi_u32 v17, v12, v13 -; GCN-NEXT: v_mul_lo_u32 v18, v1, v13 -; GCN-NEXT: v_mul_lo_u32 v13, v12, v13 -; GCN-NEXT: v_add_u32_e32 v14, v17, v14 -; GCN-NEXT: v_add_u32_e32 v14, v14, v18 -; GCN-NEXT: v_sub_u32_e32 v17, v5, v14 -; GCN-NEXT: v_sub_co_u32_e32 v13, vcc, v16, v13 -; GCN-NEXT: v_subb_co_u32_e64 v16, s[0:1], v17, v1, vcc -; GCN-NEXT: v_sub_co_u32_e64 v17, s[0:1], v13, v12 -; GCN-NEXT: v_subbrev_co_u32_e64 v18, s[2:3], 0, v16, s[0:1] -; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v18, v1 -; GCN-NEXT: v_cndmask_b32_e64 v19, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v17, v12 -; GCN-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v14, vcc -; GCN-NEXT: v_cndmask_b32_e64 v20, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], v18, v1 -; GCN-NEXT: v_subb_co_u32_e64 v16, s[0:1], v16, v1, s[0:1] -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v1 -; GCN-NEXT: v_cndmask_b32_e64 v19, v19, v20, s[2:3] -; GCN-NEXT: v_sub_co_u32_e64 v20, s[0:1], v17, v12 -; GCN-NEXT: v_cndmask_b32_e64 v14, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v13, v12 -; GCN-NEXT: v_subbrev_co_u32_e64 v16, s[0:1], 0, v16, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v5, v1 -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v19 -; GCN-NEXT: v_cndmask_b32_e32 v1, v14, v12, vcc -; GCN-NEXT: v_cndmask_b32_e64 v17, v17, v20, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v16, v18, v16, s[0:1] -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v16, vcc -; GCN-NEXT: v_cndmask_b32_e32 v5, v13, v17, vcc -; GCN-NEXT: v_xor_b32_e32 v5, v5, v15 -; GCN-NEXT: v_xor_b32_e32 v1, v1, v15 -; GCN-NEXT: v_sub_co_u32_e32 v12, vcc, v5, v15 -; GCN-NEXT: v_subb_co_u32_e32 v13, vcc, v1, v15, vcc -; GCN-NEXT: s_cbranch_execnz .LBB12_9 +; GCN-NEXT: ; implicit-def: $sgpr6_sgpr7 +; GCN-NEXT: s_branch .LBB12_2 +; GCN-NEXT: .LBB12_7: +; GCN-NEXT: ; implicit-def: $sgpr18_sgpr19 +; GCN-NEXT: s_branch .LBB12_5 ; GCN-NEXT: .LBB12_8: -; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0 -; GCN-NEXT: v_sub_u32_e32 v5, 0, v0 -; GCN-NEXT: v_mov_b32_e32 v13, 0 -; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1 -; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: v_mul_lo_u32 v5, v5, v1 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v5 -; GCN-NEXT: v_add_u32_e32 v1, v1, v5 -; GCN-NEXT: v_mul_hi_u32 v1, v4, v1 -; GCN-NEXT: v_mul_lo_u32 v1, v1, v0 -; GCN-NEXT: v_sub_u32_e32 v1, v4, v1 -; GCN-NEXT: v_sub_u32_e32 v4, v1, v0 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; GCN-NEXT: v_sub_u32_e32 v4, v1, v0 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 -; GCN-NEXT: v_cndmask_b32_e32 v12, v1, v4, vcc +; GCN-NEXT: v_mov_b32_e32 v2, s18 +; GCN-NEXT: v_mov_b32_e32 v3, s19 ; GCN-NEXT: .LBB12_9: -; GCN-NEXT: v_or_b32_e32 v1, v7, v3 -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] -; GCN-NEXT: s_cbranch_vccz .LBB12_16 +; GCN-NEXT: s_or_b64 s[12:13], s[10:11], s[8:9] +; GCN-NEXT: s_mov_b32 s12, 0 +; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GCN-NEXT: s_cbranch_scc0 .LBB12_12 ; GCN-NEXT: ; %bb.10: -; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v3 -; GCN-NEXT: v_add_co_u32_e32 v1, vcc, v2, v0 -; GCN-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v0, vcc -; GCN-NEXT: v_xor_b32_e32 v1, v1, v0 -; GCN-NEXT: v_xor_b32_e32 v0, v3, v0 -; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1 -; GCN-NEXT: v_cvt_f32_u32_e32 v4, v0 -; GCN-NEXT: v_sub_co_u32_e32 v5, vcc, 0, v1 -; GCN-NEXT: v_subb_co_u32_e32 v14, vcc, 0, v0, vcc -; GCN-NEXT: v_madmk_f32 v3, v4, 0x4f800000, v3 -; GCN-NEXT: v_rcp_f32_e32 v3, v3 -; GCN-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3 -; GCN-NEXT: v_mul_f32_e32 v4, 0x2f800000, v3 -; GCN-NEXT: v_trunc_f32_e32 v4, v4 -; GCN-NEXT: v_madmk_f32 v3, v4, 0xcf800000, v3 -; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_mul_lo_u32 v16, v5, v4 -; GCN-NEXT: v_mul_hi_u32 v15, v5, v3 -; GCN-NEXT: v_mul_lo_u32 v17, v14, v3 -; GCN-NEXT: v_mul_lo_u32 v18, v5, v3 -; GCN-NEXT: v_add_u32_e32 v15, v15, v16 -; GCN-NEXT: v_add_u32_e32 v15, v15, v17 -; GCN-NEXT: v_mul_lo_u32 v16, v3, v15 -; GCN-NEXT: v_mul_hi_u32 v17, v3, v18 -; GCN-NEXT: v_mul_hi_u32 v19, v3, v15 -; GCN-NEXT: v_mul_hi_u32 v20, v4, v15 -; GCN-NEXT: v_mul_lo_u32 v15, v4, v15 -; GCN-NEXT: v_add_co_u32_e32 v16, vcc, v17, v16 -; GCN-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v19, vcc -; GCN-NEXT: v_mul_lo_u32 v19, v4, v18 -; GCN-NEXT: v_mul_hi_u32 v18, v4, v18 -; GCN-NEXT: v_add_co_u32_e32 v16, vcc, v16, v19 -; GCN-NEXT: v_addc_co_u32_e32 v16, vcc, v17, v18, vcc -; GCN-NEXT: v_addc_co_u32_e32 v17, vcc, 0, v20, vcc -; GCN-NEXT: v_add_co_u32_e32 v15, vcc, v16, v15 -; GCN-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v17, vcc -; GCN-NEXT: v_add_co_u32_e32 v3, vcc, v3, v15 -; GCN-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v16, vcc -; GCN-NEXT: v_mul_lo_u32 v15, v5, v4 -; GCN-NEXT: v_mul_hi_u32 v16, v5, v3 -; GCN-NEXT: v_mul_lo_u32 v14, v14, v3 -; GCN-NEXT: v_mul_lo_u32 v5, v5, v3 -; GCN-NEXT: v_add_u32_e32 v15, v16, v15 -; GCN-NEXT: v_add_u32_e32 v14, v15, v14 -; GCN-NEXT: v_mul_lo_u32 v17, v3, v14 -; GCN-NEXT: v_mul_hi_u32 v18, v3, v5 -; GCN-NEXT: v_mul_hi_u32 v19, v3, v14 -; GCN-NEXT: v_mul_hi_u32 v16, v4, v5 -; GCN-NEXT: v_mul_lo_u32 v5, v4, v5 -; GCN-NEXT: v_mul_hi_u32 v15, v4, v14 -; GCN-NEXT: v_add_co_u32_e32 v17, vcc, v18, v17 -; GCN-NEXT: v_addc_co_u32_e32 v18, vcc, 0, v19, vcc -; GCN-NEXT: v_mul_lo_u32 v14, v4, v14 -; GCN-NEXT: v_add_co_u32_e32 v5, vcc, v17, v5 -; GCN-NEXT: v_addc_co_u32_e32 v5, vcc, v18, v16, vcc -; GCN-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v15, vcc -; GCN-NEXT: v_add_co_u32_e32 v5, vcc, v5, v14 -; GCN-NEXT: v_addc_co_u32_e32 v14, vcc, 0, v15, vcc -; GCN-NEXT: v_add_co_u32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_co_u32_e32 v4, vcc, v4, v14, vcc -; GCN-NEXT: v_ashrrev_i32_e32 v5, 31, v7 -; GCN-NEXT: v_add_co_u32_e32 v14, vcc, v6, v5 -; GCN-NEXT: v_xor_b32_e32 v14, v14, v5 -; GCN-NEXT: v_mul_lo_u32 v15, v14, v4 -; GCN-NEXT: v_mul_hi_u32 v16, v14, v3 -; GCN-NEXT: v_mul_hi_u32 v17, v14, v4 -; GCN-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v5, vcc -; GCN-NEXT: v_xor_b32_e32 v7, v7, v5 -; GCN-NEXT: v_add_co_u32_e32 v15, vcc, v16, v15 -; GCN-NEXT: v_addc_co_u32_e32 v16, vcc, 0, v17, vcc -; GCN-NEXT: v_mul_lo_u32 v17, v7, v3 -; GCN-NEXT: v_mul_hi_u32 v3, v7, v3 -; GCN-NEXT: v_mul_hi_u32 v18, v7, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v7, v4 -; GCN-NEXT: v_add_co_u32_e32 v15, vcc, v15, v17 -; GCN-NEXT: v_addc_co_u32_e32 v3, vcc, v16, v3, vcc -; GCN-NEXT: v_addc_co_u32_e32 v15, vcc, 0, v18, vcc -; GCN-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4 -; GCN-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v15, vcc -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v15, v1, v3 -; GCN-NEXT: v_mul_lo_u32 v16, v0, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 -; GCN-NEXT: v_add_u32_e32 v4, v15, v4 -; GCN-NEXT: v_add_u32_e32 v4, v4, v16 -; GCN-NEXT: v_sub_u32_e32 v15, v7, v4 -; GCN-NEXT: v_sub_co_u32_e32 v3, vcc, v14, v3 -; GCN-NEXT: v_subb_co_u32_e64 v14, s[0:1], v15, v0, vcc -; GCN-NEXT: v_sub_co_u32_e64 v15, s[0:1], v3, v1 -; GCN-NEXT: v_subbrev_co_u32_e64 v16, s[2:3], 0, v14, s[0:1] -; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v16, v0 -; GCN-NEXT: v_cndmask_b32_e64 v17, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_ge_u32_e64 s[2:3], v15, v1 -; GCN-NEXT: v_subb_co_u32_e32 v4, vcc, v7, v4, vcc -; GCN-NEXT: v_cndmask_b32_e64 v18, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], v16, v0 -; GCN-NEXT: v_subb_co_u32_e64 v14, s[0:1], v14, v0, s[0:1] -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0 -; GCN-NEXT: v_cndmask_b32_e64 v17, v17, v18, s[2:3] -; GCN-NEXT: v_sub_co_u32_e64 v18, s[0:1], v15, v1 -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1 -; GCN-NEXT: v_subbrev_co_u32_e64 v14, s[0:1], 0, v14, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v4, v0 -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v17 -; GCN-NEXT: v_cndmask_b32_e32 v0, v7, v1, vcc -; GCN-NEXT: v_cndmask_b32_e64 v15, v15, v18, s[0:1] -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GCN-NEXT: v_cndmask_b32_e64 v14, v16, v14, s[0:1] -; GCN-NEXT: v_cndmask_b32_e32 v1, v3, v15, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v14, vcc -; GCN-NEXT: v_xor_b32_e32 v1, v1, v5 -; GCN-NEXT: v_xor_b32_e32 v0, v0, v5 -; GCN-NEXT: v_sub_co_u32_e32 v14, vcc, v1, v5 -; GCN-NEXT: v_subb_co_u32_e32 v15, vcc, v0, v5, vcc -; GCN-NEXT: s_cbranch_execnz .LBB12_12 +; GCN-NEXT: s_ashr_i32 s12, s9, 31 +; GCN-NEXT: s_add_u32 s14, s8, s12 +; GCN-NEXT: s_mov_b32 s13, s12 +; GCN-NEXT: s_addc_u32 s15, s9, s12 +; GCN-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s14 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s15 +; GCN-NEXT: s_sub_u32 s9, 0, s14 +; GCN-NEXT: s_subb_u32 s18, 0, s15 +; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_readfirstlane_b32 s19, v1 +; GCN-NEXT: v_readfirstlane_b32 s16, v0 +; GCN-NEXT: s_mul_i32 s17, s9, s19 +; GCN-NEXT: s_mul_hi_u32 s21, s9, s16 +; GCN-NEXT: s_mul_i32 s20, s18, s16 +; GCN-NEXT: s_add_i32 s17, s21, s17 +; GCN-NEXT: s_add_i32 s17, s17, s20 +; GCN-NEXT: s_mul_i32 s22, s9, s16 +; GCN-NEXT: s_mul_i32 s21, s16, s17 +; GCN-NEXT: s_mul_hi_u32 s23, s16, s22 +; GCN-NEXT: s_mul_hi_u32 s20, s16, s17 +; GCN-NEXT: s_add_u32 s21, s23, s21 +; GCN-NEXT: s_addc_u32 s20, 0, s20 +; GCN-NEXT: s_mul_hi_u32 s24, s19, s22 +; GCN-NEXT: s_mul_i32 s22, s19, s22 +; GCN-NEXT: s_add_u32 s21, s21, s22 +; GCN-NEXT: s_mul_hi_u32 s23, s19, s17 +; GCN-NEXT: s_addc_u32 s20, s20, s24 +; GCN-NEXT: s_addc_u32 s21, s23, 0 +; GCN-NEXT: s_mul_i32 s17, s19, s17 +; GCN-NEXT: s_add_u32 s17, s20, s17 +; GCN-NEXT: s_addc_u32 s20, 0, s21 +; GCN-NEXT: s_add_i32 s21, s16, s17 +; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_addc_u32 s19, s19, s20 +; GCN-NEXT: s_mul_i32 s16, s9, s19 +; GCN-NEXT: s_mul_hi_u32 s17, s9, s21 +; GCN-NEXT: s_add_i32 s16, s17, s16 +; GCN-NEXT: s_mul_i32 s18, s18, s21 +; GCN-NEXT: s_add_i32 s16, s16, s18 +; GCN-NEXT: s_mul_i32 s9, s9, s21 +; GCN-NEXT: s_mul_hi_u32 s18, s19, s9 +; GCN-NEXT: s_mul_i32 s20, s19, s9 +; GCN-NEXT: s_mul_i32 s23, s21, s16 +; GCN-NEXT: s_mul_hi_u32 s9, s21, s9 +; GCN-NEXT: s_mul_hi_u32 s22, s21, s16 +; GCN-NEXT: s_add_u32 s9, s9, s23 +; GCN-NEXT: s_addc_u32 s22, 0, s22 +; GCN-NEXT: s_add_u32 s9, s9, s20 +; GCN-NEXT: s_mul_hi_u32 s17, s19, s16 +; GCN-NEXT: s_addc_u32 s9, s22, s18 +; GCN-NEXT: s_addc_u32 s17, s17, 0 +; GCN-NEXT: s_mul_i32 s16, s19, s16 +; GCN-NEXT: s_add_u32 s9, s9, s16 +; GCN-NEXT: s_addc_u32 s18, 0, s17 +; GCN-NEXT: s_add_i32 s21, s21, s9 +; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_addc_u32 s9, s19, s18 +; GCN-NEXT: s_ashr_i32 s16, s11, 31 +; GCN-NEXT: s_add_u32 s18, s10, s16 +; GCN-NEXT: s_mov_b32 s17, s16 +; GCN-NEXT: s_addc_u32 s19, s11, s16 +; GCN-NEXT: s_xor_b64 s[18:19], s[18:19], s[16:17] +; GCN-NEXT: s_mul_i32 s20, s18, s9 +; GCN-NEXT: s_mul_hi_u32 s22, s18, s21 +; GCN-NEXT: s_mul_hi_u32 s11, s18, s9 +; GCN-NEXT: s_add_u32 s20, s22, s20 +; GCN-NEXT: s_addc_u32 s11, 0, s11 +; GCN-NEXT: s_mul_hi_u32 s23, s19, s21 +; GCN-NEXT: s_mul_i32 s21, s19, s21 +; GCN-NEXT: s_add_u32 s20, s20, s21 +; GCN-NEXT: s_mul_hi_u32 s22, s19, s9 +; GCN-NEXT: s_addc_u32 s11, s11, s23 +; GCN-NEXT: s_addc_u32 s20, s22, 0 +; GCN-NEXT: s_mul_i32 s9, s19, s9 +; GCN-NEXT: s_add_u32 s9, s11, s9 +; GCN-NEXT: s_addc_u32 s11, 0, s20 +; GCN-NEXT: s_mul_i32 s11, s14, s11 +; GCN-NEXT: s_mul_hi_u32 s20, s14, s9 +; GCN-NEXT: s_add_i32 s11, s20, s11 +; GCN-NEXT: s_mul_i32 s20, s15, s9 +; GCN-NEXT: s_add_i32 s11, s11, s20 +; GCN-NEXT: s_sub_i32 s22, s19, s11 +; GCN-NEXT: s_mul_i32 s9, s14, s9 +; GCN-NEXT: s_sub_i32 s9, s18, s9 +; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 +; GCN-NEXT: s_subb_u32 s18, s22, s15 +; GCN-NEXT: s_sub_i32 s24, s9, s14 +; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 +; GCN-NEXT: s_subb_u32 s25, s18, 0 +; GCN-NEXT: s_cmp_ge_u32 s25, s15 +; GCN-NEXT: s_cselect_b32 s26, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s24, s14 +; GCN-NEXT: s_cselect_b32 s27, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s25, s15 +; GCN-NEXT: s_cselect_b32 s26, s27, s26 +; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 +; GCN-NEXT: s_subb_u32 s18, s18, s15 +; GCN-NEXT: s_sub_i32 s27, s24, s14 +; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 +; GCN-NEXT: s_subb_u32 s18, s18, 0 +; GCN-NEXT: s_cmp_lg_u32 s26, 0 +; GCN-NEXT: s_cselect_b32 s22, s27, s24 +; GCN-NEXT: s_cselect_b32 s18, s18, s25 +; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 +; GCN-NEXT: s_subb_u32 s11, s19, s11 +; GCN-NEXT: s_cmp_ge_u32 s11, s15 +; GCN-NEXT: s_cselect_b32 s19, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s9, s14 +; GCN-NEXT: s_cselect_b32 s14, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s11, s15 +; GCN-NEXT: s_cselect_b32 s14, s14, s19 +; GCN-NEXT: s_cmp_lg_u32 s14, 0 +; GCN-NEXT: s_cselect_b32 s15, s18, s11 +; GCN-NEXT: s_cselect_b32 s14, s22, s9 +; GCN-NEXT: s_xor_b64 s[14:15], s[14:15], s[16:17] +; GCN-NEXT: s_sub_u32 s14, s14, s16 +; GCN-NEXT: s_subb_u32 s15, s15, s16 +; GCN-NEXT: s_cbranch_execnz .LBB12_13 ; GCN-NEXT: .LBB12_11: -; GCN-NEXT: v_cvt_f32_u32_e32 v0, v2 -; GCN-NEXT: v_sub_u32_e32 v1, 0, v2 -; GCN-NEXT: v_mov_b32_e32 v15, 0 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_sub_i32 s9, 0, s8 +; GCN-NEXT: v_mov_b32_e32 v5, 0 ; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v1, v1, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s9, v0 ; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 ; GCN-NEXT: v_add_u32_e32 v0, v0, v1 -; GCN-NEXT: v_mul_hi_u32 v0, v6, v0 -; GCN-NEXT: v_mul_lo_u32 v0, v0, v2 -; GCN-NEXT: v_sub_u32_e32 v0, v6, v0 -; GCN-NEXT: v_sub_u32_e32 v1, v0, v2 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s8 +; GCN-NEXT: v_sub_u32_e32 v0, s10, v0 +; GCN-NEXT: v_subrev_u32_e32 v1, s8, v0 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc -; GCN-NEXT: v_sub_u32_e32 v1, v0, v2 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; GCN-NEXT: v_cndmask_b32_e32 v14, v0, v1, vcc +; GCN-NEXT: v_subrev_u32_e32 v1, s8, v0 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 +; GCN-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc +; GCN-NEXT: s_branch .LBB12_14 ; GCN-NEXT: .LBB12_12: -; GCN-NEXT: v_mov_b32_e32 v0, 0 -; GCN-NEXT: global_store_dwordx4 v0, v[12:15], s[8:9] offset:16 -; GCN-NEXT: global_store_dwordx4 v0, v[8:11], s[8:9] -; GCN-NEXT: s_endpgm +; GCN-NEXT: ; implicit-def: $sgpr14_sgpr15 +; GCN-NEXT: s_branch .LBB12_11 ; GCN-NEXT: .LBB12_13: -; GCN-NEXT: ; implicit-def: $vgpr8_vgpr9 -; GCN-NEXT: s_branch .LBB12_2 +; GCN-NEXT: v_mov_b32_e32 v4, s14 +; GCN-NEXT: v_mov_b32_e32 v5, s15 ; GCN-NEXT: .LBB12_14: -; GCN-NEXT: s_branch .LBB12_5 -; GCN-NEXT: .LBB12_15: -; GCN-NEXT: ; implicit-def: $vgpr12_vgpr13 -; GCN-NEXT: s_branch .LBB12_8 +; GCN-NEXT: s_or_b64 s[8:9], s[4:5], s[2:3] +; GCN-NEXT: s_mov_b32 s8, 0 +; GCN-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GCN-NEXT: s_cbranch_scc0 .LBB12_17 +; GCN-NEXT: ; %bb.15: +; GCN-NEXT: s_ashr_i32 s8, s3, 31 +; GCN-NEXT: s_add_u32 s10, s2, s8 +; GCN-NEXT: s_mov_b32 s9, s8 +; GCN-NEXT: s_addc_u32 s11, s3, s8 +; GCN-NEXT: s_xor_b64 s[10:11], s[10:11], s[8:9] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s10 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s11 +; GCN-NEXT: s_sub_u32 s3, 0, s10 +; GCN-NEXT: s_subb_u32 s14, 0, s11 +; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 +; GCN-NEXT: v_rcp_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 +; GCN-NEXT: v_trunc_f32_e32 v1, v1 +; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_readfirstlane_b32 s15, v1 +; GCN-NEXT: v_readfirstlane_b32 s12, v0 +; GCN-NEXT: s_mul_i32 s13, s3, s15 +; GCN-NEXT: s_mul_hi_u32 s17, s3, s12 +; GCN-NEXT: s_mul_i32 s16, s14, s12 +; GCN-NEXT: s_add_i32 s13, s17, s13 +; GCN-NEXT: s_add_i32 s13, s13, s16 +; GCN-NEXT: s_mul_i32 s18, s3, s12 +; GCN-NEXT: s_mul_i32 s17, s12, s13 +; GCN-NEXT: s_mul_hi_u32 s19, s12, s18 +; GCN-NEXT: s_mul_hi_u32 s16, s12, s13 +; GCN-NEXT: s_add_u32 s17, s19, s17 +; GCN-NEXT: s_addc_u32 s16, 0, s16 +; GCN-NEXT: s_mul_hi_u32 s20, s15, s18 +; GCN-NEXT: s_mul_i32 s18, s15, s18 +; GCN-NEXT: s_add_u32 s17, s17, s18 +; GCN-NEXT: s_mul_hi_u32 s19, s15, s13 +; GCN-NEXT: s_addc_u32 s16, s16, s20 +; GCN-NEXT: s_addc_u32 s17, s19, 0 +; GCN-NEXT: s_mul_i32 s13, s15, s13 +; GCN-NEXT: s_add_u32 s13, s16, s13 +; GCN-NEXT: s_addc_u32 s16, 0, s17 +; GCN-NEXT: s_add_i32 s17, s12, s13 +; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GCN-NEXT: s_addc_u32 s15, s15, s16 +; GCN-NEXT: s_mul_i32 s12, s3, s15 +; GCN-NEXT: s_mul_hi_u32 s13, s3, s17 +; GCN-NEXT: s_add_i32 s12, s13, s12 +; GCN-NEXT: s_mul_i32 s14, s14, s17 +; GCN-NEXT: s_add_i32 s12, s12, s14 +; GCN-NEXT: s_mul_i32 s3, s3, s17 +; GCN-NEXT: s_mul_hi_u32 s14, s15, s3 +; GCN-NEXT: s_mul_i32 s16, s15, s3 +; GCN-NEXT: s_mul_i32 s19, s17, s12 +; GCN-NEXT: s_mul_hi_u32 s3, s17, s3 +; GCN-NEXT: s_mul_hi_u32 s18, s17, s12 +; GCN-NEXT: s_add_u32 s3, s3, s19 +; GCN-NEXT: s_addc_u32 s18, 0, s18 +; GCN-NEXT: s_add_u32 s3, s3, s16 +; GCN-NEXT: s_mul_hi_u32 s13, s15, s12 +; GCN-NEXT: s_addc_u32 s3, s18, s14 +; GCN-NEXT: s_addc_u32 s13, s13, 0 +; GCN-NEXT: s_mul_i32 s12, s15, s12 +; GCN-NEXT: s_add_u32 s3, s3, s12 +; GCN-NEXT: s_addc_u32 s14, 0, s13 +; GCN-NEXT: s_add_i32 s17, s17, s3 +; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 +; GCN-NEXT: s_addc_u32 s3, s15, s14 +; GCN-NEXT: s_ashr_i32 s12, s5, 31 +; GCN-NEXT: s_add_u32 s14, s4, s12 +; GCN-NEXT: s_mov_b32 s13, s12 +; GCN-NEXT: s_addc_u32 s15, s5, s12 +; GCN-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13] +; GCN-NEXT: s_mul_i32 s16, s14, s3 +; GCN-NEXT: s_mul_hi_u32 s18, s14, s17 +; GCN-NEXT: s_mul_hi_u32 s5, s14, s3 +; GCN-NEXT: s_add_u32 s16, s18, s16 +; GCN-NEXT: s_addc_u32 s5, 0, s5 +; GCN-NEXT: s_mul_hi_u32 s19, s15, s17 +; GCN-NEXT: s_mul_i32 s17, s15, s17 +; GCN-NEXT: s_add_u32 s16, s16, s17 +; GCN-NEXT: s_mul_hi_u32 s18, s15, s3 +; GCN-NEXT: s_addc_u32 s5, s5, s19 +; GCN-NEXT: s_addc_u32 s16, s18, 0 +; GCN-NEXT: s_mul_i32 s3, s15, s3 +; GCN-NEXT: s_add_u32 s3, s5, s3 +; GCN-NEXT: s_addc_u32 s5, 0, s16 +; GCN-NEXT: s_mul_i32 s5, s10, s5 +; GCN-NEXT: s_mul_hi_u32 s16, s10, s3 +; GCN-NEXT: s_add_i32 s5, s16, s5 +; GCN-NEXT: s_mul_i32 s16, s11, s3 +; GCN-NEXT: s_add_i32 s5, s5, s16 +; GCN-NEXT: s_sub_i32 s18, s15, s5 +; GCN-NEXT: s_mul_i32 s3, s10, s3 +; GCN-NEXT: s_sub_i32 s3, s14, s3 +; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_subb_u32 s14, s18, s11 +; GCN-NEXT: s_sub_i32 s20, s3, s10 +; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 +; GCN-NEXT: s_subb_u32 s21, s14, 0 +; GCN-NEXT: s_cmp_ge_u32 s21, s11 +; GCN-NEXT: s_cselect_b32 s22, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s20, s10 +; GCN-NEXT: s_cselect_b32 s23, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s21, s11 +; GCN-NEXT: s_cselect_b32 s22, s23, s22 +; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 +; GCN-NEXT: s_subb_u32 s14, s14, s11 +; GCN-NEXT: s_sub_i32 s23, s20, s10 +; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 +; GCN-NEXT: s_subb_u32 s14, s14, 0 +; GCN-NEXT: s_cmp_lg_u32 s22, 0 +; GCN-NEXT: s_cselect_b32 s18, s23, s20 +; GCN-NEXT: s_cselect_b32 s14, s14, s21 +; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 +; GCN-NEXT: s_subb_u32 s5, s15, s5 +; GCN-NEXT: s_cmp_ge_u32 s5, s11 +; GCN-NEXT: s_cselect_b32 s15, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s3, s10 +; GCN-NEXT: s_cselect_b32 s10, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s5, s11 +; GCN-NEXT: s_cselect_b32 s10, s10, s15 +; GCN-NEXT: s_cmp_lg_u32 s10, 0 +; GCN-NEXT: s_cselect_b32 s11, s14, s5 +; GCN-NEXT: s_cselect_b32 s10, s18, s3 +; GCN-NEXT: s_xor_b64 s[10:11], s[10:11], s[12:13] +; GCN-NEXT: s_sub_u32 s10, s10, s12 +; GCN-NEXT: s_subb_u32 s11, s11, s12 +; GCN-NEXT: s_cbranch_execnz .LBB12_18 ; GCN-NEXT: .LBB12_16: -; GCN-NEXT: s_branch .LBB12_11 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_sub_i32 s3, 0, s2 +; GCN-NEXT: v_mov_b32_e32 v7, 0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: v_add_u32_e32 v0, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s4, v0 +; GCN-NEXT: v_mul_lo_u32 v0, v0, s2 +; GCN-NEXT: v_sub_u32_e32 v0, s4, v0 +; GCN-NEXT: v_subrev_u32_e32 v1, s2, v0 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-NEXT: v_subrev_u32_e32 v1, s2, v0 +; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v0 +; GCN-NEXT: v_cndmask_b32_e32 v6, v0, v1, vcc +; GCN-NEXT: s_branch .LBB12_19 +; GCN-NEXT: .LBB12_17: +; GCN-NEXT: ; implicit-def: $sgpr10_sgpr11 +; GCN-NEXT: s_branch .LBB12_16 +; GCN-NEXT: .LBB12_18: +; GCN-NEXT: v_mov_b32_e32 v6, s10 +; GCN-NEXT: v_mov_b32_e32 v7, s11 +; GCN-NEXT: .LBB12_19: +; GCN-NEXT: v_mov_b32_e32 v8, 0 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s7 +; GCN-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16 +; GCN-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] +; GCN-NEXT: s_endpgm ; ; TAHITI-LABEL: srem_v4i64: ; TAHITI: ; %bb.0: @@ -5546,7 +5639,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TAHITI-NEXT: v_mul_lo_u32 v20, v20, v11 ; TAHITI-NEXT: v_mul_lo_u32 v19, v19, v11 ; TAHITI-NEXT: v_add_i32_e32 v21, vcc, v21, v22 -; TAHITI-NEXT: v_add_i32_e32 v20, vcc, v21, v20 +; TAHITI-NEXT: v_add_i32_e32 v20, vcc, v20, v21 ; TAHITI-NEXT: v_mul_lo_u32 v23, v11, v20 ; TAHITI-NEXT: v_mul_hi_u32 v24, v11, v19 ; TAHITI-NEXT: v_mul_hi_u32 v25, v11, v20 @@ -5689,7 +5782,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TAHITI-NEXT: v_mul_lo_u32 v18, v18, v13 ; TAHITI-NEXT: v_mul_lo_u32 v15, v15, v13 ; TAHITI-NEXT: v_add_i32_e32 v19, vcc, v19, v20 -; TAHITI-NEXT: v_add_i32_e32 v18, vcc, v19, v18 +; TAHITI-NEXT: v_add_i32_e32 v18, vcc, v18, v19 ; TAHITI-NEXT: v_mul_lo_u32 v21, v13, v18 ; TAHITI-NEXT: v_mul_hi_u32 v22, v13, v15 ; TAHITI-NEXT: v_mul_hi_u32 v23, v13, v18 @@ -5833,7 +5926,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TAHITI-NEXT: v_mul_lo_u32 v16, v16, v13 ; TAHITI-NEXT: v_mul_lo_u32 v15, v15, v13 ; TAHITI-NEXT: v_add_i32_e32 v17, vcc, v17, v18 -; TAHITI-NEXT: v_add_i32_e32 v16, vcc, v17, v16 +; TAHITI-NEXT: v_add_i32_e32 v16, vcc, v16, v17 ; TAHITI-NEXT: v_mul_lo_u32 v19, v13, v16 ; TAHITI-NEXT: v_mul_hi_u32 v20, v13, v15 ; TAHITI-NEXT: v_mul_hi_u32 v21, v13, v16 @@ -5976,7 +6069,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TAHITI-NEXT: v_mul_lo_u32 v14, v14, v3 ; TAHITI-NEXT: v_mul_lo_u32 v5, v5, v3 ; TAHITI-NEXT: v_add_i32_e32 v15, vcc, v15, v16 -; TAHITI-NEXT: v_add_i32_e32 v14, vcc, v15, v14 +; TAHITI-NEXT: v_add_i32_e32 v14, vcc, v14, v15 ; TAHITI-NEXT: v_mul_lo_u32 v17, v3, v14 ; TAHITI-NEXT: v_mul_hi_u32 v18, v3, v5 ; TAHITI-NEXT: v_mul_hi_u32 v19, v3, v14 @@ -6089,7 +6182,6 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-LABEL: srem_v4i64: ; TONGA: ; %bb.0: ; TONGA-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x24 -; TONGA-NEXT: v_mov_b32_e32 v8, 0 ; TONGA-NEXT: s_waitcnt lgkmcnt(0) ; TONGA-NEXT: s_add_u32 s0, s6, 48 ; TONGA-NEXT: v_mov_b32_e32 v0, s6 @@ -6109,249 +6201,279 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_mov_b32_e32 v4, s0 ; TONGA-NEXT: flat_load_dwordx4 v[0:3], v[0:1] ; TONGA-NEXT: flat_load_dwordx4 v[4:7], v[4:5] +; TONGA-NEXT: s_waitcnt vmcnt(3) +; TONGA-NEXT: v_readfirstlane_b32 s3, v15 +; TONGA-NEXT: v_readfirstlane_b32 s2, v14 ; TONGA-NEXT: s_waitcnt vmcnt(2) -; TONGA-NEXT: v_or_b32_e32 v9, v15, v11 -; TONGA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[8:9] -; TONGA-NEXT: s_cbranch_vccz .LBB12_13 +; TONGA-NEXT: v_readfirstlane_b32 s1, v11 +; TONGA-NEXT: v_readfirstlane_b32 s0, v10 +; TONGA-NEXT: s_or_b64 s[6:7], s[2:3], s[0:1] +; TONGA-NEXT: s_mov_b32 s6, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[6:7], 0 +; TONGA-NEXT: s_cbranch_scc0 .LBB12_3 ; TONGA-NEXT: ; %bb.1: -; TONGA-NEXT: v_ashrrev_i32_e32 v8, 31, v11 -; TONGA-NEXT: v_add_u32_e32 v9, vcc, v10, v8 -; TONGA-NEXT: v_addc_u32_e32 v11, vcc, v11, v8, vcc -; TONGA-NEXT: v_xor_b32_e32 v9, v9, v8 -; TONGA-NEXT: v_xor_b32_e32 v8, v11, v8 -; TONGA-NEXT: v_cvt_f32_u32_e32 v11, v9 -; TONGA-NEXT: v_cvt_f32_u32_e32 v18, v8 -; TONGA-NEXT: v_sub_u32_e32 v23, vcc, 0, v9 -; TONGA-NEXT: v_subb_u32_e32 v24, vcc, 0, v8, vcc -; TONGA-NEXT: v_madmk_f32 v11, v18, 0x4f800000, v11 -; TONGA-NEXT: v_rcp_f32_e32 v11, v11 -; TONGA-NEXT: v_mul_f32_e32 v11, 0x5f7ffffc, v11 -; TONGA-NEXT: v_mul_f32_e32 v18, 0x2f800000, v11 -; TONGA-NEXT: v_trunc_f32_e32 v18, v18 -; TONGA-NEXT: v_madmk_f32 v11, v18, 0xcf800000, v11 -; TONGA-NEXT: v_cvt_u32_f32_e32 v22, v18 -; TONGA-NEXT: v_cvt_u32_f32_e32 v11, v11 -; TONGA-NEXT: v_mul_lo_u32 v20, v23, v22 -; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v23, v11, 0 -; TONGA-NEXT: v_mul_lo_u32 v21, v24, v11 -; TONGA-NEXT: v_add_u32_e32 v19, vcc, v19, v20 -; TONGA-NEXT: v_add_u32_e32 v21, vcc, v19, v21 -; TONGA-NEXT: v_mad_u64_u32 v[19:20], s[0:1], v11, v21, 0 -; TONGA-NEXT: v_mul_hi_u32 v25, v11, v18 -; TONGA-NEXT: v_add_u32_e32 v25, vcc, v25, v19 -; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v22, v18, 0 -; TONGA-NEXT: v_addc_u32_e32 v26, vcc, 0, v20, vcc -; TONGA-NEXT: v_mad_u64_u32 v[20:21], s[0:1], v22, v21, 0 -; TONGA-NEXT: v_add_u32_e32 v18, vcc, v25, v18 -; TONGA-NEXT: v_addc_u32_e32 v18, vcc, v26, v19, vcc -; TONGA-NEXT: v_addc_u32_e32 v19, vcc, 0, v21, vcc -; TONGA-NEXT: v_add_u32_e32 v18, vcc, v18, v20 -; TONGA-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v11, v18 -; TONGA-NEXT: v_addc_u32_e32 v25, vcc, v22, v19, vcc -; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v23, v11, 0 -; TONGA-NEXT: v_mul_lo_u32 v22, v23, v25 -; TONGA-NEXT: v_mul_lo_u32 v23, v24, v11 -; TONGA-NEXT: v_mul_hi_u32 v24, v11, v18 -; TONGA-NEXT: v_mad_u64_u32 v[20:21], s[0:1], v25, v18, 0 -; TONGA-NEXT: v_add_u32_e32 v19, vcc, v22, v19 -; TONGA-NEXT: v_add_u32_e32 v19, vcc, v19, v23 -; TONGA-NEXT: v_mad_u64_u32 v[22:23], s[0:1], v11, v19, 0 -; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v25, v19, 0 -; TONGA-NEXT: v_add_u32_e32 v22, vcc, v24, v22 -; TONGA-NEXT: v_addc_u32_e32 v23, vcc, 0, v23, vcc -; TONGA-NEXT: v_add_u32_e32 v20, vcc, v22, v20 -; TONGA-NEXT: v_addc_u32_e32 v20, vcc, v23, v21, vcc -; TONGA-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc -; TONGA-NEXT: v_add_u32_e32 v18, vcc, v20, v18 -; TONGA-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v11, v18 -; TONGA-NEXT: v_addc_u32_e32 v20, vcc, v25, v19, vcc -; TONGA-NEXT: v_ashrrev_i32_e32 v22, 31, v15 -; TONGA-NEXT: v_add_u32_e32 v18, vcc, v14, v22 -; TONGA-NEXT: v_xor_b32_e32 v23, v18, v22 -; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v23, v20, 0 -; TONGA-NEXT: v_mul_hi_u32 v21, v23, v11 -; TONGA-NEXT: v_addc_u32_e32 v15, vcc, v15, v22, vcc -; TONGA-NEXT: v_xor_b32_e32 v15, v15, v22 -; TONGA-NEXT: v_add_u32_e32 v24, vcc, v21, v18 -; TONGA-NEXT: v_addc_u32_e32 v25, vcc, 0, v19, vcc -; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v15, v11, 0 -; TONGA-NEXT: v_mad_u64_u32 v[20:21], s[0:1], v15, v20, 0 -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v24, v18 -; TONGA-NEXT: v_addc_u32_e32 v11, vcc, v25, v19, vcc -; TONGA-NEXT: v_addc_u32_e32 v18, vcc, 0, v21, vcc -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v11, v20 -; TONGA-NEXT: v_addc_u32_e32 v18, vcc, 0, v18, vcc -; TONGA-NEXT: v_mul_lo_u32 v20, v9, v18 -; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v9, v11, 0 -; TONGA-NEXT: v_mul_lo_u32 v11, v8, v11 -; TONGA-NEXT: v_add_u32_e32 v19, vcc, v20, v19 -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v11, v19 -; TONGA-NEXT: v_sub_u32_e32 v19, vcc, v15, v11 -; TONGA-NEXT: v_sub_u32_e32 v18, vcc, v23, v18 -; TONGA-NEXT: v_subb_u32_e64 v19, s[0:1], v19, v8, vcc -; TONGA-NEXT: v_sub_u32_e64 v20, s[0:1], v18, v9 -; TONGA-NEXT: v_subbrev_u32_e64 v21, s[2:3], 0, v19, s[0:1] -; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v21, v8 -; TONGA-NEXT: v_cndmask_b32_e64 v23, 0, -1, s[2:3] -; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v20, v9 -; TONGA-NEXT: v_subb_u32_e32 v11, vcc, v15, v11, vcc -; TONGA-NEXT: v_cndmask_b32_e64 v24, 0, -1, s[2:3] -; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v21, v8 -; TONGA-NEXT: v_subb_u32_e64 v19, s[0:1], v19, v8, s[0:1] -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v11, v8 -; TONGA-NEXT: v_cndmask_b32_e64 v23, v23, v24, s[2:3] -; TONGA-NEXT: v_sub_u32_e64 v24, s[0:1], v20, v9 -; TONGA-NEXT: v_cndmask_b32_e64 v15, 0, -1, vcc -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v18, v9 -; TONGA-NEXT: v_subbrev_u32_e64 v19, s[0:1], 0, v19, s[0:1] -; TONGA-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc -; TONGA-NEXT: v_cmp_eq_u32_e32 vcc, v11, v8 -; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v23 -; TONGA-NEXT: v_cndmask_b32_e32 v8, v15, v9, vcc -; TONGA-NEXT: v_cndmask_b32_e64 v20, v20, v24, s[0:1] -; TONGA-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 -; TONGA-NEXT: v_cndmask_b32_e64 v19, v21, v19, s[0:1] -; TONGA-NEXT: v_cndmask_b32_e32 v9, v18, v20, vcc -; TONGA-NEXT: v_cndmask_b32_e32 v8, v11, v19, vcc -; TONGA-NEXT: v_xor_b32_e32 v9, v9, v22 -; TONGA-NEXT: v_xor_b32_e32 v11, v8, v22 -; TONGA-NEXT: v_sub_u32_e32 v8, vcc, v9, v22 -; TONGA-NEXT: v_subb_u32_e32 v9, vcc, v11, v22, vcc -; TONGA-NEXT: s_cbranch_execnz .LBB12_3 +; TONGA-NEXT: s_ashr_i32 s6, s1, 31 +; TONGA-NEXT: s_add_u32 s8, s0, s6 +; TONGA-NEXT: s_mov_b32 s7, s6 +; TONGA-NEXT: s_addc_u32 s9, s1, s6 +; TONGA-NEXT: s_xor_b64 s[6:7], s[8:9], s[6:7] +; TONGA-NEXT: v_cvt_f32_u32_e32 v8, s6 +; TONGA-NEXT: v_cvt_f32_u32_e32 v9, s7 +; TONGA-NEXT: s_sub_u32 s1, 0, s6 +; TONGA-NEXT: s_subb_u32 s10, 0, s7 +; TONGA-NEXT: v_madmk_f32 v8, v9, 0x4f800000, v8 +; TONGA-NEXT: v_rcp_f32_e32 v8, v8 +; TONGA-NEXT: v_mul_f32_e32 v8, 0x5f7ffffc, v8 +; TONGA-NEXT: v_mul_f32_e32 v9, 0x2f800000, v8 +; TONGA-NEXT: v_trunc_f32_e32 v9, v9 +; TONGA-NEXT: v_madmk_f32 v8, v9, 0xcf800000, v8 +; TONGA-NEXT: v_cvt_u32_f32_e32 v14, v9 +; TONGA-NEXT: v_cvt_u32_f32_e32 v15, v8 +; TONGA-NEXT: v_mul_lo_u32 v10, s1, v14 +; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[8:9], s1, v15, 0 +; TONGA-NEXT: v_mul_lo_u32 v11, s10, v15 +; TONGA-NEXT: v_add_u32_e32 v9, vcc, v9, v10 +; TONGA-NEXT: v_add_u32_e32 v11, vcc, v9, v11 +; TONGA-NEXT: v_mul_hi_u32 v18, v15, v8 +; TONGA-NEXT: v_mad_u64_u32 v[9:10], s[8:9], v15, v11, 0 +; TONGA-NEXT: v_add_u32_e32 v18, vcc, v18, v9 +; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[8:9], v14, v8, 0 +; TONGA-NEXT: v_addc_u32_e32 v19, vcc, 0, v10, vcc +; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[8:9], v14, v11, 0 +; TONGA-NEXT: v_add_u32_e32 v8, vcc, v18, v8 +; TONGA-NEXT: v_addc_u32_e32 v8, vcc, v19, v9, vcc +; TONGA-NEXT: v_addc_u32_e32 v9, vcc, 0, v11, vcc +; TONGA-NEXT: v_add_u32_e32 v8, vcc, v8, v10 +; TONGA-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; TONGA-NEXT: v_add_u32_e32 v18, vcc, v15, v8 +; TONGA-NEXT: v_addc_u32_e32 v19, vcc, v14, v9, vcc +; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[8:9], s1, v18, 0 +; TONGA-NEXT: v_mul_lo_u32 v14, s1, v19 +; TONGA-NEXT: v_mul_lo_u32 v15, s10, v18 +; TONGA-NEXT: v_mul_hi_u32 v20, v18, v8 +; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[8:9], v19, v8, 0 +; TONGA-NEXT: v_add_u32_e32 v9, vcc, v14, v9 +; TONGA-NEXT: v_add_u32_e32 v9, vcc, v15, v9 +; TONGA-NEXT: v_mad_u64_u32 v[14:15], s[8:9], v18, v9, 0 +; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[8:9], v19, v9, 0 +; TONGA-NEXT: v_add_u32_e32 v14, vcc, v20, v14 +; TONGA-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc +; TONGA-NEXT: v_add_u32_e32 v10, vcc, v14, v10 +; TONGA-NEXT: v_addc_u32_e32 v10, vcc, v15, v11, vcc +; TONGA-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; TONGA-NEXT: v_add_u32_e32 v8, vcc, v10, v8 +; TONGA-NEXT: s_ashr_i32 s10, s3, 31 +; TONGA-NEXT: v_addc_u32_e32 v9, vcc, 0, v9, vcc +; TONGA-NEXT: s_add_u32 s8, s2, s10 +; TONGA-NEXT: v_add_u32_e32 v10, vcc, v18, v8 +; TONGA-NEXT: s_mov_b32 s11, s10 +; TONGA-NEXT: s_addc_u32 s9, s3, s10 +; TONGA-NEXT: v_addc_u32_e32 v11, vcc, v19, v9, vcc +; TONGA-NEXT: s_xor_b64 s[12:13], s[8:9], s[10:11] +; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[8:9], s12, v11, 0 +; TONGA-NEXT: v_mul_hi_u32 v14, s12, v10 +; TONGA-NEXT: v_readfirstlane_b32 s1, v9 +; TONGA-NEXT: v_readfirstlane_b32 s3, v8 +; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[8:9], s13, v11, 0 +; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[8:9], s13, v10, 0 +; TONGA-NEXT: v_readfirstlane_b32 s14, v14 +; TONGA-NEXT: s_add_u32 s3, s14, s3 +; TONGA-NEXT: s_addc_u32 s1, 0, s1 +; TONGA-NEXT: v_readfirstlane_b32 s14, v10 +; TONGA-NEXT: v_readfirstlane_b32 s9, v11 +; TONGA-NEXT: s_add_u32 s3, s3, s14 +; TONGA-NEXT: v_readfirstlane_b32 s8, v9 +; TONGA-NEXT: s_addc_u32 s1, s1, s9 +; TONGA-NEXT: s_addc_u32 s3, s8, 0 +; TONGA-NEXT: v_readfirstlane_b32 s8, v8 +; TONGA-NEXT: s_add_u32 s1, s1, s8 +; TONGA-NEXT: v_mov_b32_e32 v8, s1 +; TONGA-NEXT: v_mad_u64_u32 v[8:9], s[8:9], s6, v8, 0 +; TONGA-NEXT: s_addc_u32 s3, 0, s3 +; TONGA-NEXT: s_mul_i32 s3, s6, s3 +; TONGA-NEXT: v_readfirstlane_b32 s14, v9 +; TONGA-NEXT: s_add_i32 s3, s14, s3 +; TONGA-NEXT: s_mul_i32 s1, s7, s1 +; TONGA-NEXT: s_add_i32 s3, s3, s1 +; TONGA-NEXT: s_sub_i32 s1, s13, s3 +; TONGA-NEXT: v_readfirstlane_b32 s14, v8 +; TONGA-NEXT: s_sub_i32 s12, s12, s14 +; TONGA-NEXT: s_cselect_b64 s[14:15], 1, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 +; TONGA-NEXT: s_subb_u32 s1, s1, s7 +; TONGA-NEXT: s_sub_i32 s18, s12, s6 +; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 +; TONGA-NEXT: s_subb_u32 s19, s1, 0 +; TONGA-NEXT: s_cmp_ge_u32 s19, s7 +; TONGA-NEXT: s_cselect_b32 s20, -1, 0 +; TONGA-NEXT: s_cmp_ge_u32 s18, s6 +; TONGA-NEXT: s_cselect_b32 s21, -1, 0 +; TONGA-NEXT: s_cmp_eq_u32 s19, s7 +; TONGA-NEXT: s_cselect_b32 s20, s21, s20 +; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 +; TONGA-NEXT: s_subb_u32 s1, s1, s7 +; TONGA-NEXT: s_sub_i32 s21, s18, s6 +; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 +; TONGA-NEXT: s_subb_u32 s1, s1, 0 +; TONGA-NEXT: s_cmp_lg_u32 s20, 0 +; TONGA-NEXT: s_cselect_b32 s16, s21, s18 +; TONGA-NEXT: s_cselect_b32 s1, s1, s19 +; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 +; TONGA-NEXT: s_subb_u32 s3, s13, s3 +; TONGA-NEXT: s_cmp_ge_u32 s3, s7 +; TONGA-NEXT: s_cselect_b32 s13, -1, 0 +; TONGA-NEXT: s_cmp_ge_u32 s12, s6 +; TONGA-NEXT: s_cselect_b32 s6, -1, 0 +; TONGA-NEXT: s_cmp_eq_u32 s3, s7 +; TONGA-NEXT: s_cselect_b32 s6, s6, s13 +; TONGA-NEXT: s_cmp_lg_u32 s6, 0 +; TONGA-NEXT: s_cselect_b32 s7, s1, s3 +; TONGA-NEXT: s_cselect_b32 s6, s16, s12 +; TONGA-NEXT: s_xor_b64 s[6:7], s[6:7], s[10:11] +; TONGA-NEXT: s_sub_u32 s6, s6, s10 +; TONGA-NEXT: s_subb_u32 s7, s7, s10 +; TONGA-NEXT: s_cbranch_execnz .LBB12_4 ; TONGA-NEXT: .LBB12_2: -; TONGA-NEXT: v_cvt_f32_u32_e32 v8, v10 -; TONGA-NEXT: v_sub_u32_e32 v9, vcc, 0, v10 +; TONGA-NEXT: v_cvt_f32_u32_e32 v8, s0 +; TONGA-NEXT: s_sub_i32 s1, 0, s0 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v8, v8 ; TONGA-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8 ; TONGA-NEXT: v_cvt_u32_f32_e32 v8, v8 -; TONGA-NEXT: v_mul_lo_u32 v9, v9, v8 +; TONGA-NEXT: v_mul_lo_u32 v9, s1, v8 ; TONGA-NEXT: v_mul_hi_u32 v9, v8, v9 ; TONGA-NEXT: v_add_u32_e32 v8, vcc, v8, v9 -; TONGA-NEXT: v_mul_hi_u32 v8, v14, v8 -; TONGA-NEXT: v_mul_lo_u32 v8, v8, v10 -; TONGA-NEXT: v_sub_u32_e32 v8, vcc, v14, v8 -; TONGA-NEXT: v_subrev_u32_e32 v9, vcc, v10, v8 -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v8, v10 +; TONGA-NEXT: v_mul_hi_u32 v8, s2, v8 +; TONGA-NEXT: v_mul_lo_u32 v8, v8, s0 +; TONGA-NEXT: v_sub_u32_e32 v8, vcc, s2, v8 +; TONGA-NEXT: v_subrev_u32_e32 v9, vcc, s0, v8 +; TONGA-NEXT: v_cmp_le_u32_e32 vcc, s0, v8 ; TONGA-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc -; TONGA-NEXT: v_sub_u32_e32 v9, vcc, v8, v10 -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v8, v10 +; TONGA-NEXT: v_subrev_u32_e32 v9, vcc, s0, v8 +; TONGA-NEXT: v_cmp_le_u32_e32 vcc, s0, v8 ; TONGA-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; TONGA-NEXT: v_mov_b32_e32 v9, 0 +; TONGA-NEXT: s_branch .LBB12_5 ; TONGA-NEXT: .LBB12_3: +; TONGA-NEXT: ; implicit-def: $sgpr6_sgpr7 +; TONGA-NEXT: s_branch .LBB12_2 +; TONGA-NEXT: .LBB12_4: +; TONGA-NEXT: v_mov_b32_e32 v9, s7 +; TONGA-NEXT: v_mov_b32_e32 v8, s6 +; TONGA-NEXT: .LBB12_5: ; TONGA-NEXT: v_or_b32_e32 v11, v17, v13 ; TONGA-NEXT: v_mov_b32_e32 v10, 0 ; TONGA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[10:11] -; TONGA-NEXT: s_cbranch_vccz .LBB12_14 -; TONGA-NEXT: ; %bb.4: +; TONGA-NEXT: s_cbranch_vccz .LBB12_15 +; TONGA-NEXT: ; %bb.6: ; TONGA-NEXT: v_ashrrev_i32_e32 v10, 31, v13 ; TONGA-NEXT: v_add_u32_e32 v11, vcc, v12, v10 ; TONGA-NEXT: v_addc_u32_e32 v13, vcc, v13, v10, vcc -; TONGA-NEXT: v_xor_b32_e32 v15, v11, v10 -; TONGA-NEXT: v_xor_b32_e32 v20, v13, v10 -; TONGA-NEXT: v_cvt_f32_u32_e32 v10, v15 -; TONGA-NEXT: v_cvt_f32_u32_e32 v11, v20 -; TONGA-NEXT: v_sub_u32_e32 v21, vcc, 0, v15 -; TONGA-NEXT: v_subb_u32_e32 v22, vcc, 0, v20, vcc -; TONGA-NEXT: v_madmk_f32 v10, v11, 0x4f800000, v10 -; TONGA-NEXT: v_rcp_f32_e32 v10, v10 -; TONGA-NEXT: v_mul_f32_e32 v10, 0x5f7ffffc, v10 -; TONGA-NEXT: v_mul_f32_e32 v11, 0x2f800000, v10 -; TONGA-NEXT: v_trunc_f32_e32 v11, v11 -; TONGA-NEXT: v_madmk_f32 v10, v11, 0xcf800000, v10 -; TONGA-NEXT: v_cvt_u32_f32_e32 v18, v11 -; TONGA-NEXT: v_cvt_u32_f32_e32 v19, v10 -; TONGA-NEXT: v_mul_lo_u32 v13, v21, v18 -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v21, v19, 0 -; TONGA-NEXT: v_mul_lo_u32 v14, v22, v19 -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v11, v13 -; TONGA-NEXT: v_add_u32_e32 v23, vcc, v11, v14 -; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v19, v23, 0 -; TONGA-NEXT: v_mul_hi_u32 v11, v19, v10 -; TONGA-NEXT: v_add_u32_e32 v24, vcc, v11, v13 -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v18, v10, 0 -; TONGA-NEXT: v_addc_u32_e32 v25, vcc, 0, v14, vcc -; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v18, v23, 0 -; TONGA-NEXT: v_add_u32_e32 v10, vcc, v24, v10 -; TONGA-NEXT: v_addc_u32_e32 v10, vcc, v25, v11, vcc -; TONGA-NEXT: v_addc_u32_e32 v11, vcc, 0, v14, vcc -; TONGA-NEXT: v_add_u32_e32 v10, vcc, v10, v13 -; TONGA-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc -; TONGA-NEXT: v_add_u32_e32 v23, vcc, v19, v10 -; TONGA-NEXT: v_addc_u32_e32 v24, vcc, v18, v11, vcc -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v21, v23, 0 -; TONGA-NEXT: v_mul_lo_u32 v18, v21, v24 -; TONGA-NEXT: v_mul_lo_u32 v19, v22, v23 -; TONGA-NEXT: v_mul_hi_u32 v21, v23, v10 -; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v24, v10, 0 -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v18, v11 -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v11, v19 -; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v23, v11, 0 -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v24, v11, 0 -; TONGA-NEXT: v_add_u32_e32 v18, vcc, v21, v18 -; TONGA-NEXT: v_addc_u32_e32 v19, vcc, 0, v19, vcc -; TONGA-NEXT: v_add_u32_e32 v13, vcc, v18, v13 -; TONGA-NEXT: v_addc_u32_e32 v13, vcc, v19, v14, vcc -; TONGA-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc -; TONGA-NEXT: v_add_u32_e32 v10, vcc, v13, v10 -; TONGA-NEXT: v_addc_u32_e32 v11, vcc, 0, v11, vcc -; TONGA-NEXT: v_add_u32_e32 v13, vcc, v23, v10 -; TONGA-NEXT: v_addc_u32_e32 v14, vcc, v24, v11, vcc -; TONGA-NEXT: v_ashrrev_i32_e32 v18, 31, v17 -; TONGA-NEXT: v_add_u32_e32 v10, vcc, v16, v18 -; TONGA-NEXT: v_xor_b32_e32 v19, v10, v18 -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v19, v14, 0 -; TONGA-NEXT: v_mul_hi_u32 v21, v19, v13 -; TONGA-NEXT: v_addc_u32_e32 v17, vcc, v17, v18, vcc -; TONGA-NEXT: v_xor_b32_e32 v17, v17, v18 -; TONGA-NEXT: v_add_u32_e32 v21, vcc, v21, v10 -; TONGA-NEXT: v_addc_u32_e32 v22, vcc, 0, v11, vcc -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v17, v13, 0 -; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v17, v14, 0 -; TONGA-NEXT: v_add_u32_e32 v10, vcc, v21, v10 -; TONGA-NEXT: v_addc_u32_e32 v10, vcc, v22, v11, vcc -; TONGA-NEXT: v_addc_u32_e32 v11, vcc, 0, v14, vcc -; TONGA-NEXT: v_add_u32_e32 v13, vcc, v10, v13 -; TONGA-NEXT: v_addc_u32_e32 v10, vcc, 0, v11, vcc -; TONGA-NEXT: v_mul_lo_u32 v14, v15, v10 -; TONGA-NEXT: v_mad_u64_u32 v[10:11], s[0:1], v15, v13, 0 -; TONGA-NEXT: v_mul_lo_u32 v13, v20, v13 -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v14, v11 -; TONGA-NEXT: v_add_u32_e32 v11, vcc, v13, v11 -; TONGA-NEXT: v_sub_u32_e32 v13, vcc, v17, v11 -; TONGA-NEXT: v_sub_u32_e32 v10, vcc, v19, v10 -; TONGA-NEXT: v_subb_u32_e64 v13, s[0:1], v13, v20, vcc -; TONGA-NEXT: v_sub_u32_e64 v14, s[0:1], v10, v15 -; TONGA-NEXT: v_subbrev_u32_e64 v19, s[2:3], 0, v13, s[0:1] -; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v19, v20 +; TONGA-NEXT: v_xor_b32_e32 v11, v11, v10 +; TONGA-NEXT: v_xor_b32_e32 v10, v13, v10 +; TONGA-NEXT: v_cvt_f32_u32_e32 v13, v11 +; TONGA-NEXT: v_cvt_f32_u32_e32 v14, v10 +; TONGA-NEXT: v_sub_u32_e32 v22, vcc, 0, v11 +; TONGA-NEXT: v_subb_u32_e32 v23, vcc, 0, v10, vcc +; TONGA-NEXT: v_madmk_f32 v13, v14, 0x4f800000, v13 +; TONGA-NEXT: v_rcp_f32_e32 v13, v13 +; TONGA-NEXT: v_mul_f32_e32 v13, 0x5f7ffffc, v13 +; TONGA-NEXT: v_mul_f32_e32 v14, 0x2f800000, v13 +; TONGA-NEXT: v_trunc_f32_e32 v14, v14 +; TONGA-NEXT: v_madmk_f32 v13, v14, 0xcf800000, v13 +; TONGA-NEXT: v_cvt_u32_f32_e32 v20, v14 +; TONGA-NEXT: v_cvt_u32_f32_e32 v21, v13 +; TONGA-NEXT: v_mul_lo_u32 v15, v22, v20 +; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v22, v21, 0 +; TONGA-NEXT: v_mul_lo_u32 v18, v23, v21 +; TONGA-NEXT: v_add_u32_e32 v14, vcc, v14, v15 +; TONGA-NEXT: v_add_u32_e32 v18, vcc, v14, v18 +; TONGA-NEXT: v_mad_u64_u32 v[14:15], s[0:1], v21, v18, 0 +; TONGA-NEXT: v_mul_hi_u32 v19, v21, v13 +; TONGA-NEXT: v_add_u32_e32 v24, vcc, v19, v14 +; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v20, v13, 0 +; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v20, v18, 0 +; TONGA-NEXT: v_addc_u32_e32 v15, vcc, 0, v15, vcc +; TONGA-NEXT: v_add_u32_e32 v13, vcc, v24, v13 +; TONGA-NEXT: v_addc_u32_e32 v13, vcc, v15, v14, vcc +; TONGA-NEXT: v_addc_u32_e32 v14, vcc, 0, v19, vcc +; TONGA-NEXT: v_add_u32_e32 v13, vcc, v13, v18 +; TONGA-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc +; TONGA-NEXT: v_add_u32_e32 v24, vcc, v21, v13 +; TONGA-NEXT: v_addc_u32_e32 v25, vcc, v20, v14, vcc +; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v22, v24, 0 +; TONGA-NEXT: v_mul_lo_u32 v15, v22, v25 +; TONGA-NEXT: v_mul_lo_u32 v20, v23, v24 +; TONGA-NEXT: v_mad_u64_u32 v[18:19], s[0:1], v25, v13, 0 +; TONGA-NEXT: v_add_u32_e32 v14, vcc, v15, v14 +; TONGA-NEXT: v_add_u32_e32 v20, vcc, v20, v14 +; TONGA-NEXT: v_mad_u64_u32 v[14:15], s[0:1], v24, v20, 0 +; TONGA-NEXT: v_mul_hi_u32 v13, v24, v13 +; TONGA-NEXT: v_mad_u64_u32 v[20:21], s[0:1], v25, v20, 0 +; TONGA-NEXT: v_add_u32_e32 v13, vcc, v13, v14 +; TONGA-NEXT: v_addc_u32_e32 v14, vcc, 0, v15, vcc +; TONGA-NEXT: v_add_u32_e32 v13, vcc, v13, v18 +; TONGA-NEXT: v_addc_u32_e32 v13, vcc, v14, v19, vcc +; TONGA-NEXT: v_addc_u32_e32 v14, vcc, 0, v21, vcc +; TONGA-NEXT: v_add_u32_e32 v13, vcc, v13, v20 +; TONGA-NEXT: v_addc_u32_e32 v14, vcc, 0, v14, vcc +; TONGA-NEXT: v_add_u32_e32 v15, vcc, v24, v13 +; TONGA-NEXT: v_addc_u32_e32 v18, vcc, v25, v14, vcc +; TONGA-NEXT: v_ashrrev_i32_e32 v19, 31, v17 +; TONGA-NEXT: v_add_u32_e32 v13, vcc, v16, v19 +; TONGA-NEXT: v_xor_b32_e32 v20, v13, v19 +; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v20, v18, 0 +; TONGA-NEXT: v_mul_hi_u32 v21, v20, v15 +; TONGA-NEXT: v_addc_u32_e32 v17, vcc, v17, v19, vcc +; TONGA-NEXT: v_xor_b32_e32 v22, v17, v19 +; TONGA-NEXT: v_add_u32_e32 v21, vcc, v21, v13 +; TONGA-NEXT: v_addc_u32_e32 v23, vcc, 0, v14, vcc +; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v22, v15, 0 +; TONGA-NEXT: v_mad_u64_u32 v[17:18], s[0:1], v22, v18, 0 +; TONGA-NEXT: v_add_u32_e32 v13, vcc, v21, v13 +; TONGA-NEXT: v_addc_u32_e32 v13, vcc, v23, v14, vcc +; TONGA-NEXT: v_addc_u32_e32 v14, vcc, 0, v18, vcc +; TONGA-NEXT: v_add_u32_e32 v15, vcc, v13, v17 +; TONGA-NEXT: v_addc_u32_e32 v13, vcc, 0, v14, vcc +; TONGA-NEXT: v_mul_lo_u32 v17, v11, v13 +; TONGA-NEXT: v_mad_u64_u32 v[13:14], s[0:1], v11, v15, 0 +; TONGA-NEXT: v_mul_lo_u32 v15, v10, v15 +; TONGA-NEXT: v_add_u32_e32 v14, vcc, v17, v14 +; TONGA-NEXT: v_add_u32_e32 v14, vcc, v15, v14 +; TONGA-NEXT: v_sub_u32_e32 v15, vcc, v22, v14 +; TONGA-NEXT: v_sub_u32_e32 v13, vcc, v20, v13 +; TONGA-NEXT: v_subb_u32_e64 v15, s[0:1], v15, v10, vcc +; TONGA-NEXT: v_sub_u32_e64 v17, s[0:1], v13, v11 +; TONGA-NEXT: v_subbrev_u32_e64 v18, s[2:3], 0, v15, s[0:1] +; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v18, v10 +; TONGA-NEXT: v_cndmask_b32_e64 v20, 0, -1, s[2:3] +; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v17, v11 ; TONGA-NEXT: v_cndmask_b32_e64 v21, 0, -1, s[2:3] -; TONGA-NEXT: v_cmp_ge_u32_e64 s[2:3], v14, v15 -; TONGA-NEXT: v_subb_u32_e32 v11, vcc, v17, v11, vcc -; TONGA-NEXT: v_cndmask_b32_e64 v22, 0, -1, s[2:3] -; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v19, v20 -; TONGA-NEXT: v_subb_u32_e64 v13, s[0:1], v13, v20, s[0:1] -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v11, v20 -; TONGA-NEXT: v_cndmask_b32_e64 v21, v21, v22, s[2:3] -; TONGA-NEXT: v_sub_u32_e64 v22, s[0:1], v14, v15 -; TONGA-NEXT: v_cndmask_b32_e64 v17, 0, -1, vcc -; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v10, v15 -; TONGA-NEXT: v_subbrev_u32_e64 v13, s[0:1], 0, v13, s[0:1] -; TONGA-NEXT: v_cndmask_b32_e64 v15, 0, -1, vcc -; TONGA-NEXT: v_cmp_eq_u32_e32 vcc, v11, v20 -; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v21 -; TONGA-NEXT: v_cndmask_b32_e32 v15, v17, v15, vcc -; TONGA-NEXT: v_cndmask_b32_e64 v14, v14, v22, s[0:1] -; TONGA-NEXT: v_cmp_ne_u32_e32 vcc, 0, v15 -; TONGA-NEXT: v_cndmask_b32_e64 v13, v19, v13, s[0:1] -; TONGA-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc -; TONGA-NEXT: v_cndmask_b32_e32 v11, v11, v13, vcc -; TONGA-NEXT: v_xor_b32_e32 v10, v10, v18 -; TONGA-NEXT: v_xor_b32_e32 v11, v11, v18 -; TONGA-NEXT: v_sub_u32_e32 v10, vcc, v10, v18 -; TONGA-NEXT: v_subb_u32_e32 v11, vcc, v11, v18, vcc -; TONGA-NEXT: s_cbranch_execnz .LBB12_6 -; TONGA-NEXT: .LBB12_5: +; TONGA-NEXT: v_cmp_eq_u32_e64 s[2:3], v18, v10 +; TONGA-NEXT: v_subb_u32_e64 v15, s[0:1], v15, v10, s[0:1] +; TONGA-NEXT: v_cndmask_b32_e64 v20, v20, v21, s[2:3] +; TONGA-NEXT: v_sub_u32_e64 v21, s[0:1], v17, v11 +; TONGA-NEXT: v_subbrev_u32_e64 v15, s[0:1], 0, v15, s[0:1] +; TONGA-NEXT: v_subb_u32_e32 v14, vcc, v22, v14, vcc +; TONGA-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v20 +; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v14, v10 +; TONGA-NEXT: v_cndmask_b32_e64 v15, v18, v15, s[0:1] +; TONGA-NEXT: v_cndmask_b32_e64 v18, 0, -1, vcc +; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v13, v11 +; TONGA-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc +; TONGA-NEXT: v_cmp_eq_u32_e32 vcc, v14, v10 +; TONGA-NEXT: v_cndmask_b32_e32 v10, v18, v11, vcc +; TONGA-NEXT: v_cndmask_b32_e64 v17, v17, v21, s[0:1] +; TONGA-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 +; TONGA-NEXT: v_cndmask_b32_e32 v11, v13, v17, vcc +; TONGA-NEXT: v_cndmask_b32_e32 v10, v14, v15, vcc +; TONGA-NEXT: v_xor_b32_e32 v11, v11, v19 +; TONGA-NEXT: v_xor_b32_e32 v13, v10, v19 +; TONGA-NEXT: v_sub_u32_e32 v10, vcc, v11, v19 +; TONGA-NEXT: v_subb_u32_e32 v11, vcc, v13, v19, vcc +; TONGA-NEXT: s_cbranch_execnz .LBB12_8 +; TONGA-NEXT: .LBB12_7: ; TONGA-NEXT: v_cvt_f32_u32_e32 v10, v12 ; TONGA-NEXT: v_sub_u32_e32 v11, vcc, 0, v12 ; TONGA-NEXT: v_rcp_iflag_f32_e32 v10, v10 @@ -6370,13 +6492,13 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v10, v12 ; TONGA-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc ; TONGA-NEXT: v_mov_b32_e32 v11, 0 -; TONGA-NEXT: .LBB12_6: +; TONGA-NEXT: .LBB12_8: ; TONGA-NEXT: s_waitcnt vmcnt(0) ; TONGA-NEXT: v_or_b32_e32 v13, v5, v1 ; TONGA-NEXT: v_mov_b32_e32 v12, 0 ; TONGA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[12:13] -; TONGA-NEXT: s_cbranch_vccz .LBB12_15 -; TONGA-NEXT: ; %bb.7: +; TONGA-NEXT: s_cbranch_vccz .LBB12_16 +; TONGA-NEXT: ; %bb.9: ; TONGA-NEXT: v_ashrrev_i32_e32 v12, 31, v1 ; TONGA-NEXT: v_add_u32_e32 v13, vcc, v0, v12 ; TONGA-NEXT: v_addc_u32_e32 v1, vcc, v1, v12, vcc @@ -6418,7 +6540,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_mul_hi_u32 v19, v21, v12 ; TONGA-NEXT: v_mad_u64_u32 v[14:15], s[0:1], v22, v12, 0 ; TONGA-NEXT: v_add_u32_e32 v13, vcc, v16, v13 -; TONGA-NEXT: v_add_u32_e32 v13, vcc, v13, v17 +; TONGA-NEXT: v_add_u32_e32 v13, vcc, v17, v13 ; TONGA-NEXT: v_mad_u64_u32 v[16:17], s[0:1], v21, v13, 0 ; TONGA-NEXT: v_mad_u64_u32 v[12:13], s[0:1], v22, v13, 0 ; TONGA-NEXT: v_add_u32_e32 v16, vcc, v19, v16 @@ -6482,8 +6604,8 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_xor_b32_e32 v1, v1, v16 ; TONGA-NEXT: v_sub_u32_e32 v12, vcc, v5, v16 ; TONGA-NEXT: v_subb_u32_e32 v13, vcc, v1, v16, vcc -; TONGA-NEXT: s_cbranch_execnz .LBB12_9 -; TONGA-NEXT: .LBB12_8: +; TONGA-NEXT: s_cbranch_execnz .LBB12_11 +; TONGA-NEXT: .LBB12_10: ; TONGA-NEXT: v_cvt_f32_u32_e32 v1, v0 ; TONGA-NEXT: v_sub_u32_e32 v5, vcc, 0, v0 ; TONGA-NEXT: v_mov_b32_e32 v13, 0 @@ -6502,12 +6624,12 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_subrev_u32_e32 v4, vcc, v0, v1 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 ; TONGA-NEXT: v_cndmask_b32_e32 v12, v1, v4, vcc -; TONGA-NEXT: .LBB12_9: +; TONGA-NEXT: .LBB12_11: ; TONGA-NEXT: v_or_b32_e32 v1, v7, v3 ; TONGA-NEXT: v_mov_b32_e32 v0, 0 ; TONGA-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[0:1] -; TONGA-NEXT: s_cbranch_vccz .LBB12_16 -; TONGA-NEXT: ; %bb.10: +; TONGA-NEXT: s_cbranch_vccz .LBB12_17 +; TONGA-NEXT: ; %bb.12: ; TONGA-NEXT: v_ashrrev_i32_e32 v0, 31, v3 ; TONGA-NEXT: v_add_u32_e32 v1, vcc, v2, v0 ; TONGA-NEXT: v_addc_u32_e32 v3, vcc, v3, v0, vcc @@ -6549,7 +6671,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_mul_hi_u32 v17, v19, v0 ; TONGA-NEXT: v_mad_u64_u32 v[3:4], s[0:1], v20, v0, 0 ; TONGA-NEXT: v_add_u32_e32 v1, vcc, v14, v1 -; TONGA-NEXT: v_add_u32_e32 v1, vcc, v1, v15 +; TONGA-NEXT: v_add_u32_e32 v1, vcc, v15, v1 ; TONGA-NEXT: v_mad_u64_u32 v[14:15], s[0:1], v19, v1, 0 ; TONGA-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v20, v1, 0 ; TONGA-NEXT: v_add_u32_e32 v14, vcc, v17, v14 @@ -6613,8 +6735,8 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_xor_b32_e32 v1, v1, v15 ; TONGA-NEXT: v_sub_u32_e32 v14, vcc, v0, v15 ; TONGA-NEXT: v_subb_u32_e32 v15, vcc, v1, v15, vcc -; TONGA-NEXT: s_cbranch_execnz .LBB12_12 -; TONGA-NEXT: .LBB12_11: +; TONGA-NEXT: s_cbranch_execnz .LBB12_14 +; TONGA-NEXT: .LBB12_13: ; TONGA-NEXT: v_cvt_f32_u32_e32 v0, v2 ; TONGA-NEXT: v_sub_u32_e32 v1, vcc, 0, v2 ; TONGA-NEXT: v_mov_b32_e32 v15, 0 @@ -6633,7 +6755,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_subrev_u32_e32 v1, vcc, v2, v0 ; TONGA-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 ; TONGA-NEXT: v_cndmask_b32_e32 v14, v0, v1, vcc -; TONGA-NEXT: .LBB12_12: +; TONGA-NEXT: .LBB12_14: ; TONGA-NEXT: v_mov_b32_e32 v0, s4 ; TONGA-NEXT: v_mov_b32_e32 v1, s5 ; TONGA-NEXT: s_add_u32 s0, s4, 16 @@ -6643,16 +6765,13 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: v_mov_b32_e32 v1, s1 ; TONGA-NEXT: flat_store_dwordx4 v[0:1], v[12:15] ; TONGA-NEXT: s_endpgm -; TONGA-NEXT: .LBB12_13: -; TONGA-NEXT: ; implicit-def: $vgpr8_vgpr9 -; TONGA-NEXT: s_branch .LBB12_2 -; TONGA-NEXT: .LBB12_14: -; TONGA-NEXT: s_branch .LBB12_5 ; TONGA-NEXT: .LBB12_15: -; TONGA-NEXT: ; implicit-def: $vgpr12_vgpr13 -; TONGA-NEXT: s_branch .LBB12_8 +; TONGA-NEXT: s_branch .LBB12_7 ; TONGA-NEXT: .LBB12_16: -; TONGA-NEXT: s_branch .LBB12_11 +; TONGA-NEXT: ; implicit-def: $vgpr12_vgpr13 +; TONGA-NEXT: s_branch .LBB12_10 +; TONGA-NEXT: .LBB12_17: +; TONGA-NEXT: s_branch .LBB12_13 ; ; EG-LABEL: srem_v4i64: ; EG: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index c7b690fbd4a21..d2a6c7d32b0a2 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -5,119 +5,159 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_srem: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xd -; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd +; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 -; GCN-NEXT: s_sub_u32 s0, 0, s12 -; GCN-NEXT: s_subb_u32 s1, 0, s13 -; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9 +; GCN-NEXT: s_sub_u32 s10, 0, s8 +; GCN-NEXT: s_subb_u32 s11, 0, s9 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 -; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v5, s1, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s0, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v6, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s1, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s0, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 -; GCN-NEXT: v_mul_hi_u32 v4, s10, v1 -; GCN-NEXT: v_mul_hi_u32 v5, s11, v1 -; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 -; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc -; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 -; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 -; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 -; GCN-NEXT: v_mul_lo_u32 v0, s12, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1 -; GCN-NEXT: v_mov_b32_e32 v3, s13 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0 -; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v5 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v4 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v5 -; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s12, v4 -; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3] -; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1] -; GCN-NEXT: v_mov_b32_e32 v4, s11 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v1 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s10, v0 +; GCN-NEXT: v_readfirstlane_b32 s12, v1 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s1, s10, s12 +; GCN-NEXT: v_readfirstlane_b32 s15, v2 +; GCN-NEXT: s_mul_i32 s13, s11, s0 +; GCN-NEXT: s_mul_i32 s14, s10, s0 +; GCN-NEXT: s_add_i32 s1, s15, s1 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s14 +; GCN-NEXT: s_add_i32 s1, s1, s13 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s1 +; GCN-NEXT: v_mul_hi_u32 v4, v1, s14 +; GCN-NEXT: v_readfirstlane_b32 s13, v3 +; GCN-NEXT: s_mul_i32 s15, s0, s1 +; GCN-NEXT: v_mul_hi_u32 v1, v1, s1 +; GCN-NEXT: s_add_u32 s13, s13, s15 +; GCN-NEXT: v_readfirstlane_b32 s15, v0 +; GCN-NEXT: s_mul_i32 s14, s12, s14 +; GCN-NEXT: s_addc_u32 s15, 0, s15 +; GCN-NEXT: v_readfirstlane_b32 s16, v4 +; GCN-NEXT: s_add_u32 s13, s13, s14 +; GCN-NEXT: s_addc_u32 s13, s15, s16 +; GCN-NEXT: v_readfirstlane_b32 s14, v1 +; GCN-NEXT: s_addc_u32 s14, s14, 0 +; GCN-NEXT: s_mul_i32 s1, s12, s1 +; GCN-NEXT: s_add_u32 s1, s13, s1 +; GCN-NEXT: s_addc_u32 s13, 0, s14 +; GCN-NEXT: s_add_i32 s14, s0, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s14 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_addc_u32 s12, s12, s13 +; GCN-NEXT: s_mul_i32 s0, s10, s12 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_add_i32 s0, s1, s0 +; GCN-NEXT: s_mul_i32 s11, s11, s14 +; GCN-NEXT: s_mul_i32 s1, s10, s14 +; GCN-NEXT: s_add_i32 s0, s0, s11 +; GCN-NEXT: v_mov_b32_e32 v2, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mul_hi_u32 v3, s12, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s14, v2 +; GCN-NEXT: v_mul_hi_u32 v1, s12, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s14, v0 +; GCN-NEXT: s_mul_i32 s11, s14, s0 +; GCN-NEXT: v_readfirstlane_b32 s15, v2 +; GCN-NEXT: s_add_u32 s11, s15, s11 +; GCN-NEXT: v_readfirstlane_b32 s13, v0 +; GCN-NEXT: s_mul_i32 s1, s12, s1 +; GCN-NEXT: s_addc_u32 s13, 0, s13 +; GCN-NEXT: v_readfirstlane_b32 s10, v3 +; GCN-NEXT: s_add_u32 s1, s11, s1 +; GCN-NEXT: s_addc_u32 s1, s13, s10 +; GCN-NEXT: v_readfirstlane_b32 s10, v1 +; GCN-NEXT: s_addc_u32 s10, s10, 0 +; GCN-NEXT: s_mul_i32 s0, s12, s0 +; GCN-NEXT: s_add_u32 s0, s1, s0 +; GCN-NEXT: s_addc_u32 s10, 0, s10 +; GCN-NEXT: s_add_i32 s11, s14, s0 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_addc_u32 s1, s12, s10 +; GCN-NEXT: v_mov_b32_e32 v0, s1 +; GCN-NEXT: v_mul_hi_u32 v1, s6, v0 +; GCN-NEXT: v_mov_b32_e32 v2, s11 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v2 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_readfirstlane_b32 s10, v1 +; GCN-NEXT: v_mul_hi_u32 v1, s7, v2 +; GCN-NEXT: s_mul_i32 s4, s6, s1 +; GCN-NEXT: v_readfirstlane_b32 s12, v3 +; GCN-NEXT: v_mul_hi_u32 v0, s7, v0 +; GCN-NEXT: s_add_u32 s4, s12, s4 +; GCN-NEXT: s_addc_u32 s10, 0, s10 +; GCN-NEXT: s_mul_i32 s11, s7, s11 +; GCN-NEXT: v_readfirstlane_b32 s12, v1 +; GCN-NEXT: s_add_u32 s4, s4, s11 +; GCN-NEXT: s_addc_u32 s4, s10, s12 +; GCN-NEXT: v_readfirstlane_b32 s10, v0 +; GCN-NEXT: s_addc_u32 s10, s10, 0 +; GCN-NEXT: s_mul_i32 s1, s7, s1 +; GCN-NEXT: s_add_u32 s4, s4, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mul_hi_u32 v0, s8, v0 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_addc_u32 s5, 0, s10 +; GCN-NEXT: s_mul_i32 s5, s8, s5 +; GCN-NEXT: v_readfirstlane_b32 s10, v0 +; GCN-NEXT: s_add_i32 s5, s10, s5 +; GCN-NEXT: s_mul_i32 s10, s9, s4 +; GCN-NEXT: s_add_i32 s10, s5, s10 +; GCN-NEXT: s_sub_i32 s11, s7, s10 +; GCN-NEXT: s_mul_i32 s4, s8, s4 +; GCN-NEXT: s_sub_i32 s6, s6, s4 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s12, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s12, 0 +; GCN-NEXT: s_subb_u32 s11, s11, s9 +; GCN-NEXT: s_sub_i32 s13, s6, s8 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s4, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_subb_u32 s14, s11, 0 +; GCN-NEXT: s_cmp_ge_u32 s14, s9 +; GCN-NEXT: s_cselect_b32 s5, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s13, s8 +; GCN-NEXT: s_cselect_b32 s15, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s14, s9 +; GCN-NEXT: s_cselect_b32 s15, s15, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_subb_u32 s11, s11, s9 +; GCN-NEXT: s_sub_i32 s16, s13, s8 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s4, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_subb_u32 s4, s11, 0 +; GCN-NEXT: s_cmp_lg_u32 s15, 0 +; GCN-NEXT: s_cselect_b32 s5, s16, s13 +; GCN-NEXT: s_cselect_b32 s4, s4, s14 +; GCN-NEXT: s_cmp_lg_u32 s12, 0 +; GCN-NEXT: s_subb_u32 s7, s7, s10 +; GCN-NEXT: s_cmp_ge_u32 s7, s9 +; GCN-NEXT: s_cselect_b32 s10, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s6, s8 +; GCN-NEXT: s_cselect_b32 s8, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s7, s9 +; GCN-NEXT: s_cselect_b32 s8, s8, s10 +; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_cselect_b32 s4, s4, s7 +; GCN-NEXT: s_cselect_b32 s5, s5, s6 +; GCN-NEXT: v_mov_b32_e32 v0, s5 +; GCN-NEXT: v_mov_b32_e32 v1, s4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem: @@ -921,133 +961,169 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 % ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 31 -; GCN-NEXT: s_ashr_i64 s[4:5], s[4:5], 31 -; GCN-NEXT: s_ashr_i32 s6, s5, 31 -; GCN-NEXT: s_add_u32 s4, s4, s6 -; GCN-NEXT: s_mov_b32 s7, s6 -; GCN-NEXT: s_addc_u32 s5, s5, s6 -; GCN-NEXT: s_xor_b64 s[8:9], s[4:5], s[6:7] -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9 -; GCN-NEXT: s_sub_u32 s4, 0, s8 -; GCN-NEXT: s_subb_u32 s5, 0, s9 -; GCN-NEXT: s_ashr_i32 s10, s3, 31 +; GCN-NEXT: s_ashr_i64 s[6:7], s[2:3], 31 +; GCN-NEXT: s_ashr_i64 s[2:3], s[4:5], 31 +; GCN-NEXT: s_ashr_i32 s4, s3, 31 +; GCN-NEXT: s_add_u32 s2, s2, s4 +; GCN-NEXT: s_mov_b32 s5, s4 +; GCN-NEXT: s_addc_u32 s3, s3, s4 +; GCN-NEXT: s_xor_b64 s[4:5], s[2:3], s[4:5] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5 +; GCN-NEXT: s_sub_u32 s10, 0, s4 +; GCN-NEXT: s_subb_u32 s11, 0, s5 +; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 -; GCN-NEXT: s_add_u32 s2, s2, s10 -; GCN-NEXT: s_mov_b32 s11, s10 -; GCN-NEXT: s_addc_u32 s3, s3, s10 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: s_xor_b64 s[12:13], s[2:3], s[10:11] -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: v_mul_lo_u32 v2, s4, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v5, s5, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s4, v0 -; GCN-NEXT: s_mov_b32 s6, -1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 -; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GCN-NEXT: v_mul_hi_u32 v7, v1, v2 -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v6 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v4, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v7, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s4, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s5, v0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s4, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s12, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s12, v0 -; GCN-NEXT: v_mul_hi_u32 v4, s12, v1 -; GCN-NEXT: v_mul_hi_u32 v5, s13, v1 -; GCN-NEXT: v_mul_lo_u32 v1, s13, v1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s13, v0 -; GCN-NEXT: v_mul_hi_u32 v0, s13, v0 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc -; GCN-NEXT: v_mul_lo_u32 v1, s8, v1 -; GCN-NEXT: v_mul_hi_u32 v2, s8, v0 -; GCN-NEXT: v_mul_lo_u32 v3, s9, v0 -; GCN-NEXT: v_mul_lo_u32 v0, s8, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s13, v1 -; GCN-NEXT: v_mov_b32_e32 v3, s9 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s12, v0 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s8, v0 -; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v5 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v4 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v5 -; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s8, v4 -; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3] -; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1] -; GCN-NEXT: v_mov_b32_e32 v4, s13 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-NEXT: v_xor_b32_e32 v0, s10, v0 -; GCN-NEXT: v_xor_b32_e32 v1, s10, v1 -; GCN-NEXT: v_mov_b32_e32 v2, s10 -; GCN-NEXT: v_subrev_i32_e32 v0, vcc, s10, v0 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s10, v0 +; GCN-NEXT: v_readfirstlane_b32 s12, v1 +; GCN-NEXT: v_readfirstlane_b32 s8, v0 +; GCN-NEXT: s_mul_i32 s9, s10, s12 +; GCN-NEXT: v_readfirstlane_b32 s15, v2 +; GCN-NEXT: s_mul_i32 s13, s11, s8 +; GCN-NEXT: s_mul_i32 s14, s10, s8 +; GCN-NEXT: s_add_i32 s9, s15, s9 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s14 +; GCN-NEXT: s_add_i32 s9, s9, s13 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s9 +; GCN-NEXT: v_mul_hi_u32 v4, v1, s14 +; GCN-NEXT: v_readfirstlane_b32 s13, v3 +; GCN-NEXT: s_mul_i32 s15, s8, s9 +; GCN-NEXT: s_add_u32 s13, s13, s15 +; GCN-NEXT: v_readfirstlane_b32 s15, v0 +; GCN-NEXT: v_mul_hi_u32 v0, v1, s9 +; GCN-NEXT: s_addc_u32 s15, 0, s15 +; GCN-NEXT: s_mul_i32 s14, s12, s14 +; GCN-NEXT: v_readfirstlane_b32 s16, v4 +; GCN-NEXT: s_add_u32 s13, s13, s14 +; GCN-NEXT: s_addc_u32 s13, s15, s16 +; GCN-NEXT: v_readfirstlane_b32 s14, v0 +; GCN-NEXT: s_addc_u32 s14, s14, 0 +; GCN-NEXT: s_mul_i32 s9, s12, s9 +; GCN-NEXT: s_add_u32 s9, s13, s9 +; GCN-NEXT: s_addc_u32 s13, 0, s14 +; GCN-NEXT: s_add_i32 s14, s8, s9 +; GCN-NEXT: v_mov_b32_e32 v0, s14 +; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 +; GCN-NEXT: s_or_b32 s8, s8, s9 +; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_addc_u32 s12, s12, s13 +; GCN-NEXT: s_mul_i32 s8, s10, s12 +; GCN-NEXT: v_readfirstlane_b32 s9, v0 +; GCN-NEXT: s_add_i32 s8, s9, s8 +; GCN-NEXT: s_mul_i32 s11, s11, s14 +; GCN-NEXT: s_mul_i32 s9, s10, s14 +; GCN-NEXT: s_add_i32 s8, s8, s11 +; GCN-NEXT: v_mov_b32_e32 v2, s9 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mul_hi_u32 v3, s12, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s14, v2 +; GCN-NEXT: v_mul_hi_u32 v1, s12, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s14, v0 +; GCN-NEXT: s_mul_i32 s11, s14, s8 +; GCN-NEXT: v_readfirstlane_b32 s15, v2 +; GCN-NEXT: s_add_u32 s11, s15, s11 +; GCN-NEXT: v_readfirstlane_b32 s13, v0 +; GCN-NEXT: s_mul_i32 s9, s12, s9 +; GCN-NEXT: s_addc_u32 s13, 0, s13 +; GCN-NEXT: v_readfirstlane_b32 s10, v3 +; GCN-NEXT: s_add_u32 s9, s11, s9 +; GCN-NEXT: s_addc_u32 s9, s13, s10 +; GCN-NEXT: v_readfirstlane_b32 s10, v1 +; GCN-NEXT: s_addc_u32 s10, s10, 0 +; GCN-NEXT: s_mul_i32 s8, s12, s8 +; GCN-NEXT: s_add_u32 s8, s9, s8 +; GCN-NEXT: s_addc_u32 s10, 0, s10 +; GCN-NEXT: s_add_i32 s11, s14, s8 +; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_or_b32 s8, s8, s9 +; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_addc_u32 s10, s12, s10 +; GCN-NEXT: s_ashr_i32 s8, s7, 31 +; GCN-NEXT: s_add_u32 s6, s6, s8 +; GCN-NEXT: s_mov_b32 s9, s8 +; GCN-NEXT: s_addc_u32 s7, s7, s8 +; GCN-NEXT: s_xor_b64 s[6:7], s[6:7], s[8:9] +; GCN-NEXT: v_mov_b32_e32 v0, s10 +; GCN-NEXT: v_mul_hi_u32 v1, s6, v0 +; GCN-NEXT: v_mov_b32_e32 v2, s11 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v2 +; GCN-NEXT: s_mul_i32 s12, s6, s10 +; GCN-NEXT: v_readfirstlane_b32 s13, v1 +; GCN-NEXT: v_mul_hi_u32 v1, s7, v2 +; GCN-NEXT: v_readfirstlane_b32 s14, v3 +; GCN-NEXT: v_mul_hi_u32 v0, s7, v0 +; GCN-NEXT: s_add_u32 s12, s14, s12 +; GCN-NEXT: s_addc_u32 s13, 0, s13 +; GCN-NEXT: s_mul_i32 s11, s7, s11 +; GCN-NEXT: v_readfirstlane_b32 s14, v1 +; GCN-NEXT: s_add_u32 s11, s12, s11 +; GCN-NEXT: s_addc_u32 s11, s13, s14 +; GCN-NEXT: v_readfirstlane_b32 s12, v0 +; GCN-NEXT: s_addc_u32 s12, s12, 0 +; GCN-NEXT: s_mul_i32 s10, s7, s10 +; GCN-NEXT: s_add_u32 s10, s11, s10 +; GCN-NEXT: v_mov_b32_e32 v0, s10 +; GCN-NEXT: v_mul_hi_u32 v0, s4, v0 +; GCN-NEXT: s_addc_u32 s11, 0, s12 +; GCN-NEXT: s_mul_i32 s11, s4, s11 +; GCN-NEXT: v_readfirstlane_b32 s12, v0 +; GCN-NEXT: s_add_i32 s11, s12, s11 +; GCN-NEXT: s_mul_i32 s12, s5, s10 +; GCN-NEXT: s_add_i32 s12, s11, s12 +; GCN-NEXT: s_sub_i32 s13, s7, s12 +; GCN-NEXT: s_mul_i32 s10, s4, s10 +; GCN-NEXT: s_sub_i32 s6, s6, s10 +; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_or_b32 s14, s10, s11 +; GCN-NEXT: s_cmp_lg_u32 s14, 0 +; GCN-NEXT: s_subb_u32 s13, s13, s5 +; GCN-NEXT: s_sub_i32 s15, s6, s4 +; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_or_b32 s10, s10, s11 +; GCN-NEXT: s_cmp_lg_u32 s10, 0 +; GCN-NEXT: s_subb_u32 s16, s13, 0 +; GCN-NEXT: s_cmp_ge_u32 s16, s5 +; GCN-NEXT: s_cselect_b32 s11, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s15, s4 +; GCN-NEXT: s_cselect_b32 s17, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s16, s5 +; GCN-NEXT: s_cselect_b32 s17, s17, s11 +; GCN-NEXT: s_cmp_lg_u32 s10, 0 +; GCN-NEXT: s_subb_u32 s13, s13, s5 +; GCN-NEXT: s_sub_i32 s18, s15, s4 +; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_or_b32 s10, s10, s11 +; GCN-NEXT: s_cmp_lg_u32 s10, 0 +; GCN-NEXT: s_subb_u32 s10, s13, 0 +; GCN-NEXT: s_cmp_lg_u32 s17, 0 +; GCN-NEXT: s_cselect_b32 s11, s18, s15 +; GCN-NEXT: s_cselect_b32 s10, s10, s16 +; GCN-NEXT: s_cmp_lg_u32 s14, 0 +; GCN-NEXT: s_subb_u32 s7, s7, s12 +; GCN-NEXT: s_cmp_ge_u32 s7, s5 +; GCN-NEXT: s_cselect_b32 s12, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s6, s4 +; GCN-NEXT: s_cselect_b32 s4, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s7, s5 +; GCN-NEXT: s_cselect_b32 s4, s4, s12 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_cselect_b32 s5, s10, s7 +; GCN-NEXT: s_cselect_b32 s4, s11, s6 +; GCN-NEXT: s_xor_b64 s[4:5], s[4:5], s[8:9] +; GCN-NEXT: s_sub_u32 s4, s4, s8 +; GCN-NEXT: s_subb_u32 s5, s5, s8 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mov_b32_e32 v1, s5 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem33_64: @@ -1236,110 +1312,145 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-LABEL: s_test_srem_k_num_i64: ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_ashr_i32 s4, s3, 31 ; GCN-NEXT: s_add_u32 s2, s2, s4 ; GCN-NEXT: s_mov_b32 s5, s4 ; GCN-NEXT: s_addc_u32 s3, s3, s4 -; GCN-NEXT: s_xor_b64 s[8:9], s[2:3], s[4:5] -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9 -; GCN-NEXT: s_sub_u32 s2, 0, s8 -; GCN-NEXT: s_subb_u32 s3, 0, s9 -; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: s_xor_b64 s[4:5], s[2:3], s[4:5] +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5 +; GCN-NEXT: s_sub_u32 s2, 0, s4 +; GCN-NEXT: s_subb_u32 s8, 0, s5 +; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 -; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 -; GCN-NEXT: v_mul_lo_u32 v5, s3, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s2, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v6, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s2, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 -; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 -; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 -; GCN-NEXT: v_mov_b32_e32 v3, s9 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v1, s9, v0 -; GCN-NEXT: v_mul_hi_u32 v2, s8, v0 -; GCN-NEXT: v_mul_lo_u32 v0, s8, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v1 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s8, v0 -; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s9, v5 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s8, v4 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s9, v5 -; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s8, v4 -; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3] -; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] -; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s9, v1 -; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s8, v0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s9, v1 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s9, v1 +; GCN-NEXT: v_readfirstlane_b32 s6, v0 +; GCN-NEXT: s_mul_i32 s7, s2, s9 +; GCN-NEXT: v_readfirstlane_b32 s12, v2 +; GCN-NEXT: s_mul_i32 s10, s8, s6 +; GCN-NEXT: s_mul_i32 s11, s2, s6 +; GCN-NEXT: s_add_i32 s7, s12, s7 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s11 +; GCN-NEXT: s_add_i32 s7, s7, s10 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s7 +; GCN-NEXT: v_mul_hi_u32 v4, v1, s11 +; GCN-NEXT: v_readfirstlane_b32 s10, v3 +; GCN-NEXT: s_mul_i32 s13, s6, s7 +; GCN-NEXT: v_mul_hi_u32 v1, v1, s7 +; GCN-NEXT: s_add_u32 s10, s10, s13 +; GCN-NEXT: v_readfirstlane_b32 s13, v0 +; GCN-NEXT: s_mul_i32 s11, s9, s11 +; GCN-NEXT: s_addc_u32 s13, 0, s13 +; GCN-NEXT: v_readfirstlane_b32 s12, v4 +; GCN-NEXT: s_add_u32 s10, s10, s11 +; GCN-NEXT: s_addc_u32 s10, s13, s12 +; GCN-NEXT: v_readfirstlane_b32 s11, v1 +; GCN-NEXT: s_addc_u32 s11, s11, 0 +; GCN-NEXT: s_mul_i32 s7, s9, s7 +; GCN-NEXT: s_add_u32 s7, s10, s7 +; GCN-NEXT: s_addc_u32 s10, 0, s11 +; GCN-NEXT: s_add_i32 s11, s6, s7 +; GCN-NEXT: v_mov_b32_e32 v0, s11 +; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: s_or_b32 s6, s6, s7 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_addc_u32 s9, s9, s10 +; GCN-NEXT: s_mul_i32 s6, s2, s9 +; GCN-NEXT: v_readfirstlane_b32 s7, v0 +; GCN-NEXT: s_add_i32 s6, s7, s6 +; GCN-NEXT: s_mul_i32 s8, s8, s11 +; GCN-NEXT: s_mul_i32 s2, s2, s11 +; GCN-NEXT: s_add_i32 s6, s6, s8 +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mul_hi_u32 v3, s9, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s11, v2 +; GCN-NEXT: v_mul_hi_u32 v1, s9, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: s_mul_i32 s8, s11, s6 +; GCN-NEXT: v_readfirstlane_b32 s12, v2 +; GCN-NEXT: s_add_u32 s8, s12, s8 +; GCN-NEXT: v_readfirstlane_b32 s10, v0 +; GCN-NEXT: s_mul_i32 s2, s9, s2 +; GCN-NEXT: s_addc_u32 s10, 0, s10 +; GCN-NEXT: v_readfirstlane_b32 s7, v3 +; GCN-NEXT: s_add_u32 s2, s8, s2 +; GCN-NEXT: s_addc_u32 s2, s10, s7 +; GCN-NEXT: v_readfirstlane_b32 s7, v1 +; GCN-NEXT: s_addc_u32 s7, s7, 0 +; GCN-NEXT: s_mul_i32 s6, s9, s6 +; GCN-NEXT: s_add_u32 s2, s2, s6 +; GCN-NEXT: s_addc_u32 s8, 0, s7 +; GCN-NEXT: s_add_i32 s11, s11, s2 +; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: s_or_b32 s2, s6, s7 +; GCN-NEXT: s_cmp_lg_u32 s2, 0 +; GCN-NEXT: s_addc_u32 s6, s9, s8 +; GCN-NEXT: v_mul_hi_u32 v1, s11, 24 +; GCN-NEXT: v_mul_hi_u32 v0, s6, 24 +; GCN-NEXT: s_mul_i32 s6, s6, 24 +; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: v_readfirstlane_b32 s8, v1 +; GCN-NEXT: v_readfirstlane_b32 s7, v0 +; GCN-NEXT: s_add_u32 s6, s8, s6 +; GCN-NEXT: s_addc_u32 s6, 0, s7 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mul_hi_u32 v0, s4, v0 +; GCN-NEXT: s_mul_i32 s7, s5, s6 +; GCN-NEXT: s_mul_i32 s6, s4, s6 +; GCN-NEXT: v_readfirstlane_b32 s8, v0 +; GCN-NEXT: s_add_i32 s8, s8, s7 +; GCN-NEXT: s_sub_i32 s9, 0, s8 +; GCN-NEXT: s_sub_i32 s10, 24, s6 +; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: s_or_b32 s11, s6, s7 +; GCN-NEXT: s_cmp_lg_u32 s11, 0 +; GCN-NEXT: s_subb_u32 s9, s9, s5 +; GCN-NEXT: s_sub_i32 s12, s10, s4 +; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: s_or_b32 s6, s6, s7 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_subb_u32 s13, s9, 0 +; GCN-NEXT: s_cmp_ge_u32 s13, s5 +; GCN-NEXT: s_cselect_b32 s7, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s12, s4 +; GCN-NEXT: s_cselect_b32 s14, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s13, s5 +; GCN-NEXT: s_cselect_b32 s14, s14, s7 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_subb_u32 s9, s9, s5 +; GCN-NEXT: s_sub_i32 s15, s12, s4 +; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: s_or_b32 s6, s6, s7 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 +; GCN-NEXT: s_subb_u32 s6, s9, 0 +; GCN-NEXT: s_cmp_lg_u32 s14, 0 +; GCN-NEXT: s_cselect_b32 s7, s15, s12 +; GCN-NEXT: s_cselect_b32 s6, s6, s13 +; GCN-NEXT: s_cmp_lg_u32 s11, 0 +; GCN-NEXT: s_subb_u32 s8, 0, s8 +; GCN-NEXT: s_cmp_ge_u32 s8, s5 +; GCN-NEXT: s_cselect_b32 s9, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s10, s4 +; GCN-NEXT: s_cselect_b32 s4, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s8, s5 +; GCN-NEXT: s_cselect_b32 s4, s4, s9 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_cselect_b32 s4, s6, s8 +; GCN-NEXT: s_cselect_b32 s5, s7, s10 +; GCN-NEXT: v_mov_b32_e32 v0, s5 +; GCN-NEXT: v_mov_b32_e32 v1, s4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem_k_num_i64: diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll index bf1f6980fe25a..cacdee31e8099 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -50,7 +50,7 @@ define amdgpu_kernel void @s_test_udiv_i64(ptr addrspace(1) %out, i64 %x, i64 %y ; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 ; GCN-NEXT: v_mul_lo_u32 v3, s4, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v4, v2 ; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 ; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 ; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 @@ -788,104 +788,137 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 ; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 ; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 -; GCN-NEXT: s_sub_u32 s4, 0, s2 -; GCN-NEXT: s_subb_u32 s5, 0, s3 +; GCN-NEXT: s_sub_u32 s6, 0, s2 +; GCN-NEXT: s_subb_u32 s8, 0, s3 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v2, s4, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v5, s5, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s4, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v6, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s4, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s4, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s5, v0 -; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s4, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 -; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 -; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 -; GCN-NEXT: v_mov_b32_e32 v4, s3 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s6, v0 +; GCN-NEXT: v_readfirstlane_b32 s9, v1 +; GCN-NEXT: v_readfirstlane_b32 s4, v0 +; GCN-NEXT: s_mul_i32 s5, s6, s9 +; GCN-NEXT: v_readfirstlane_b32 s12, v2 +; GCN-NEXT: s_mul_i32 s10, s8, s4 +; GCN-NEXT: s_mul_i32 s11, s6, s4 +; GCN-NEXT: s_add_i32 s5, s12, s5 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s11 +; GCN-NEXT: s_add_i32 s5, s5, s10 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s5 +; GCN-NEXT: v_mul_hi_u32 v4, v1, s11 +; GCN-NEXT: v_readfirstlane_b32 s10, v3 +; GCN-NEXT: v_mul_hi_u32 v1, v1, s5 +; GCN-NEXT: s_mul_i32 s13, s4, s5 +; GCN-NEXT: s_add_u32 s10, s10, s13 +; GCN-NEXT: v_readfirstlane_b32 s13, v0 +; GCN-NEXT: s_mul_i32 s11, s9, s11 +; GCN-NEXT: s_addc_u32 s13, 0, s13 +; GCN-NEXT: v_readfirstlane_b32 s12, v4 +; GCN-NEXT: s_add_u32 s10, s10, s11 +; GCN-NEXT: v_readfirstlane_b32 s14, v1 +; GCN-NEXT: s_addc_u32 s10, s13, s12 +; GCN-NEXT: s_addc_u32 s11, s14, 0 +; GCN-NEXT: s_mul_i32 s5, s9, s5 +; GCN-NEXT: s_add_u32 s5, s10, s5 +; GCN-NEXT: s_addc_u32 s10, 0, s11 +; GCN-NEXT: s_add_i32 s11, s4, s5 +; GCN-NEXT: v_mov_b32_e32 v0, s11 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: v_mul_hi_u32 v0, s6, v0 +; GCN-NEXT: s_or_b32 s4, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_addc_u32 s9, s9, s10 +; GCN-NEXT: s_mul_i32 s4, s6, s9 +; GCN-NEXT: v_readfirstlane_b32 s5, v0 +; GCN-NEXT: s_add_i32 s4, s5, s4 +; GCN-NEXT: s_mul_i32 s8, s8, s11 +; GCN-NEXT: s_mul_i32 s5, s6, s11 +; GCN-NEXT: s_add_i32 s4, s4, s8 +; GCN-NEXT: v_mov_b32_e32 v2, s5 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mul_hi_u32 v3, s9, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s11, v2 +; GCN-NEXT: v_mul_hi_u32 v1, s9, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: s_mul_i32 s8, s11, s4 +; GCN-NEXT: v_readfirstlane_b32 s12, v2 +; GCN-NEXT: s_add_u32 s8, s12, s8 +; GCN-NEXT: v_readfirstlane_b32 s10, v0 +; GCN-NEXT: s_mul_i32 s5, s9, s5 +; GCN-NEXT: s_addc_u32 s10, 0, s10 +; GCN-NEXT: v_readfirstlane_b32 s6, v3 +; GCN-NEXT: s_add_u32 s5, s8, s5 +; GCN-NEXT: s_addc_u32 s5, s10, s6 +; GCN-NEXT: v_readfirstlane_b32 s6, v1 +; GCN-NEXT: s_addc_u32 s6, s6, 0 +; GCN-NEXT: s_mul_i32 s4, s9, s4 +; GCN-NEXT: s_add_u32 s4, s5, s4 +; GCN-NEXT: s_addc_u32 s6, 0, s6 +; GCN-NEXT: s_add_i32 s11, s11, s4 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s4, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_addc_u32 s4, s9, s6 +; GCN-NEXT: v_mul_hi_u32 v1, s11, 24 +; GCN-NEXT: v_mul_hi_u32 v0, s4, 24 +; GCN-NEXT: s_mul_i32 s4, s4, 24 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_readfirstlane_b32 s8, v1 +; GCN-NEXT: v_readfirstlane_b32 s5, v0 +; GCN-NEXT: s_add_u32 s4, s8, s4 +; GCN-NEXT: s_addc_u32 s8, 0, s5 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 ; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 -; GCN-NEXT: v_mul_hi_u32 v2, s2, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; GCN-NEXT: v_mul_lo_u32 v2, s2, v0 -; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, 24, v2 -; GCN-NEXT: v_subb_u32_e64 v3, s[0:1], v3, v4, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s2, v2 -; GCN-NEXT: v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v3 -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v4 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] -; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v3 -; GCN-NEXT: v_cndmask_b32_e64 v3, v5, v4, s[0:1] -; GCN-NEXT: v_add_i32_e64 v4, s[0:1], 1, v0 -; GCN-NEXT: v_addc_u32_e64 v5, s[0:1], 0, 0, s[0:1] -; GCN-NEXT: v_add_i32_e64 v6, s[0:1], 2, v0 -; GCN-NEXT: v_addc_u32_e64 v7, s[0:1], 0, 0, s[0:1] -; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v3 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v6, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v4, v5, v7, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v2 -; GCN-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mul_i32 s0, s3, s8 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_add_i32 s9, s1, s0 +; GCN-NEXT: s_sub_i32 s10, 0, s9 +; GCN-NEXT: s_mul_i32 s0, s2, s8 +; GCN-NEXT: s_sub_i32 s11, 24, s0 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_or_b32 s12, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s12, 0 +; GCN-NEXT: s_subb_u32 s10, s10, s3 +; GCN-NEXT: s_sub_i32 s13, s11, s2 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_subb_u32 s0, s10, 0 +; GCN-NEXT: s_cmp_ge_u32 s0, s3 +; GCN-NEXT: s_cselect_b32 s1, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s13, s2 +; GCN-NEXT: s_cselect_b32 s10, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s0, s3 +; GCN-NEXT: s_cselect_b32 s0, s10, s1 +; GCN-NEXT: s_add_u32 s1, s8, 1 +; GCN-NEXT: s_addc_u32 s10, 0, 0 +; GCN-NEXT: s_add_u32 s13, s8, 2 +; GCN-NEXT: s_addc_u32 s14, 0, 0 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_cselect_b32 s0, s13, s1 +; GCN-NEXT: s_cselect_b32 s1, s14, s10 +; GCN-NEXT: s_cmp_lg_u32 s12, 0 +; GCN-NEXT: s_subb_u32 s9, 0, s9 +; GCN-NEXT: s_cmp_ge_u32 s9, s3 +; GCN-NEXT: s_cselect_b32 s10, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s11, s2 +; GCN-NEXT: s_cselect_b32 s2, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s9, s3 +; GCN-NEXT: s_cselect_b32 s2, s2, s10 +; GCN-NEXT: s_cmp_lg_u32 s2, 0 +; GCN-NEXT: s_cselect_b32 s1, s1, 0 +; GCN-NEXT: s_cselect_b32 s0, s0, s8 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll index c4d928185d8f4..c9915a82f5504 100644 --- a/llvm/test/CodeGen/AMDGPU/urem64.ll +++ b/llvm/test/CodeGen/AMDGPU/urem64.ll @@ -5,119 +5,159 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_urem_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0xd -; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x9 -; GCN-NEXT: s_mov_b32 s7, 0xf000 -; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd +; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s3, 0xf000 +; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s12 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s13 -; GCN-NEXT: s_sub_u32 s0, 0, s12 -; GCN-NEXT: s_subb_u32 s1, 0, s13 -; GCN-NEXT: s_mov_b32 s4, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s9 +; GCN-NEXT: s_sub_u32 s10, 0, s8 +; GCN-NEXT: s_subb_u32 s11, 0, s9 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 -; GCN-NEXT: s_mov_b32 s5, s9 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v5, s1, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s0, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v6, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s1, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s0, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 -; GCN-NEXT: v_mul_hi_u32 v4, s10, v1 -; GCN-NEXT: v_mul_hi_u32 v5, s11, v1 -; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 -; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc -; GCN-NEXT: v_mul_lo_u32 v1, s12, v1 -; GCN-NEXT: v_mul_hi_u32 v2, s12, v0 -; GCN-NEXT: v_mul_lo_u32 v3, s13, v0 -; GCN-NEXT: v_mul_lo_u32 v0, s12, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s11, v1 -; GCN-NEXT: v_mov_b32_e32 v3, s13 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s10, v0 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s12, v0 -; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s13, v5 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s12, v4 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s13, v5 -; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s12, v4 -; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3] -; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1] -; GCN-NEXT: v_mov_b32_e32 v4, s11 -; GCN-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s13, v1 -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s12, v0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s13, v1 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_mul_hi_u32 v2, s10, v0 +; GCN-NEXT: v_readfirstlane_b32 s12, v1 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s1, s10, s12 +; GCN-NEXT: v_readfirstlane_b32 s15, v2 +; GCN-NEXT: s_mul_i32 s13, s11, s0 +; GCN-NEXT: s_mul_i32 s14, s10, s0 +; GCN-NEXT: s_add_i32 s1, s15, s1 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s14 +; GCN-NEXT: s_add_i32 s1, s1, s13 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s1 +; GCN-NEXT: v_mul_hi_u32 v4, v1, s14 +; GCN-NEXT: v_readfirstlane_b32 s13, v3 +; GCN-NEXT: s_mul_i32 s15, s0, s1 +; GCN-NEXT: v_mul_hi_u32 v1, v1, s1 +; GCN-NEXT: s_add_u32 s13, s13, s15 +; GCN-NEXT: v_readfirstlane_b32 s15, v0 +; GCN-NEXT: s_mul_i32 s14, s12, s14 +; GCN-NEXT: s_addc_u32 s15, 0, s15 +; GCN-NEXT: v_readfirstlane_b32 s16, v4 +; GCN-NEXT: s_add_u32 s13, s13, s14 +; GCN-NEXT: s_addc_u32 s13, s15, s16 +; GCN-NEXT: v_readfirstlane_b32 s14, v1 +; GCN-NEXT: s_addc_u32 s14, s14, 0 +; GCN-NEXT: s_mul_i32 s1, s12, s1 +; GCN-NEXT: s_add_u32 s1, s13, s1 +; GCN-NEXT: s_addc_u32 s13, 0, s14 +; GCN-NEXT: s_add_i32 s14, s0, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s14 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_addc_u32 s12, s12, s13 +; GCN-NEXT: s_mul_i32 s0, s10, s12 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_add_i32 s0, s1, s0 +; GCN-NEXT: s_mul_i32 s11, s11, s14 +; GCN-NEXT: s_mul_i32 s1, s10, s14 +; GCN-NEXT: s_add_i32 s0, s0, s11 +; GCN-NEXT: v_mov_b32_e32 v2, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mul_hi_u32 v3, s12, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s14, v2 +; GCN-NEXT: v_mul_hi_u32 v1, s12, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s14, v0 +; GCN-NEXT: s_mul_i32 s11, s14, s0 +; GCN-NEXT: v_readfirstlane_b32 s15, v2 +; GCN-NEXT: s_add_u32 s11, s15, s11 +; GCN-NEXT: v_readfirstlane_b32 s13, v0 +; GCN-NEXT: s_mul_i32 s1, s12, s1 +; GCN-NEXT: s_addc_u32 s13, 0, s13 +; GCN-NEXT: v_readfirstlane_b32 s10, v3 +; GCN-NEXT: s_add_u32 s1, s11, s1 +; GCN-NEXT: s_addc_u32 s1, s13, s10 +; GCN-NEXT: v_readfirstlane_b32 s10, v1 +; GCN-NEXT: s_addc_u32 s10, s10, 0 +; GCN-NEXT: s_mul_i32 s0, s12, s0 +; GCN-NEXT: s_add_u32 s0, s1, s0 +; GCN-NEXT: s_addc_u32 s10, 0, s10 +; GCN-NEXT: s_add_i32 s11, s14, s0 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_addc_u32 s1, s12, s10 +; GCN-NEXT: v_mov_b32_e32 v0, s1 +; GCN-NEXT: v_mul_hi_u32 v1, s6, v0 +; GCN-NEXT: v_mov_b32_e32 v2, s11 +; GCN-NEXT: v_mul_hi_u32 v3, s6, v2 +; GCN-NEXT: s_mov_b32 s0, s4 +; GCN-NEXT: v_readfirstlane_b32 s10, v1 +; GCN-NEXT: v_mul_hi_u32 v1, s7, v2 +; GCN-NEXT: s_mul_i32 s4, s6, s1 +; GCN-NEXT: v_readfirstlane_b32 s12, v3 +; GCN-NEXT: v_mul_hi_u32 v0, s7, v0 +; GCN-NEXT: s_add_u32 s4, s12, s4 +; GCN-NEXT: s_addc_u32 s10, 0, s10 +; GCN-NEXT: s_mul_i32 s11, s7, s11 +; GCN-NEXT: v_readfirstlane_b32 s12, v1 +; GCN-NEXT: s_add_u32 s4, s4, s11 +; GCN-NEXT: s_addc_u32 s4, s10, s12 +; GCN-NEXT: v_readfirstlane_b32 s10, v0 +; GCN-NEXT: s_addc_u32 s10, s10, 0 +; GCN-NEXT: s_mul_i32 s1, s7, s1 +; GCN-NEXT: s_add_u32 s4, s4, s1 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mul_hi_u32 v0, s8, v0 +; GCN-NEXT: s_mov_b32 s1, s5 +; GCN-NEXT: s_addc_u32 s5, 0, s10 +; GCN-NEXT: s_mul_i32 s5, s8, s5 +; GCN-NEXT: v_readfirstlane_b32 s10, v0 +; GCN-NEXT: s_add_i32 s5, s10, s5 +; GCN-NEXT: s_mul_i32 s10, s9, s4 +; GCN-NEXT: s_add_i32 s10, s5, s10 +; GCN-NEXT: s_sub_i32 s11, s7, s10 +; GCN-NEXT: s_mul_i32 s4, s8, s4 +; GCN-NEXT: s_sub_i32 s6, s6, s4 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s12, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s12, 0 +; GCN-NEXT: s_subb_u32 s11, s11, s9 +; GCN-NEXT: s_sub_i32 s13, s6, s8 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s4, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_subb_u32 s14, s11, 0 +; GCN-NEXT: s_cmp_ge_u32 s14, s9 +; GCN-NEXT: s_cselect_b32 s5, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s13, s8 +; GCN-NEXT: s_cselect_b32 s15, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s14, s9 +; GCN-NEXT: s_cselect_b32 s15, s15, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_subb_u32 s11, s11, s9 +; GCN-NEXT: s_sub_i32 s16, s13, s8 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s4, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_subb_u32 s4, s11, 0 +; GCN-NEXT: s_cmp_lg_u32 s15, 0 +; GCN-NEXT: s_cselect_b32 s5, s16, s13 +; GCN-NEXT: s_cselect_b32 s4, s4, s14 +; GCN-NEXT: s_cmp_lg_u32 s12, 0 +; GCN-NEXT: s_subb_u32 s7, s7, s10 +; GCN-NEXT: s_cmp_ge_u32 s7, s9 +; GCN-NEXT: s_cselect_b32 s10, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s6, s8 +; GCN-NEXT: s_cselect_b32 s8, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s7, s9 +; GCN-NEXT: s_cselect_b32 s8, s8, s10 +; GCN-NEXT: s_cmp_lg_u32 s8, 0 +; GCN-NEXT: s_cselect_b32 s4, s4, s7 +; GCN-NEXT: s_cselect_b32 s5, s5, s6 +; GCN-NEXT: v_mov_b32_e32 v0, s5 +; GCN-NEXT: v_mov_b32_e32 v1, s4 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem_i64: @@ -764,106 +804,143 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i6 define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) { ; GCN-LABEL: s_test_urem_k_num_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x9 -; GCN-NEXT: s_mov_b32 s11, 0xf000 -; GCN-NEXT: s_mov_b32 s10, -1 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9 +; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7 -; GCN-NEXT: s_sub_u32 s0, 0, s6 -; GCN-NEXT: s_subb_u32 s1, 0, s7 -; GCN-NEXT: s_mov_b32 s8, s4 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-NEXT: s_sub_u32 s6, 0, s2 +; GCN-NEXT: s_subb_u32 s8, 0, s3 ; GCN-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GCN-NEXT: v_rcp_f32_e32 v0, v0 -; GCN-NEXT: s_mov_b32 s9, s5 ; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 ; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 ; GCN-NEXT: v_trunc_f32_e32 v1, v1 ; GCN-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v5, s1, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s0, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_mul_hi_u32 v3, v0, v4 -; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v6, v1, v4 -; GCN-NEXT: v_mul_lo_u32 v4, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v8, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 -; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v7, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v4 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v5, v6, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v8, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, s0, v1 -; GCN-NEXT: v_mul_hi_u32 v3, s0, v0 -; GCN-NEXT: v_mul_lo_u32 v4, s1, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; GCN-NEXT: v_mul_lo_u32 v3, s0, v0 -; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 -; GCN-NEXT: v_mul_lo_u32 v6, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v7, v0, v3 -; GCN-NEXT: v_mul_hi_u32 v8, v0, v2 -; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 -; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v2 -; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 -; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v8, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 -; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, v7, v5, vcc -; GCN-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v4, vcc -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 -; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 -; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 -; GCN-NEXT: v_mov_b32_e32 v3, s7 -; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v1, vcc -; GCN-NEXT: v_mul_lo_u32 v1, s7, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GCN-NEXT: v_mul_hi_u32 v2, s6, v0 -; GCN-NEXT: v_mul_lo_u32 v0, s6, v0 -; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v2 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, 0, v1 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, 24, v0 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, vcc -; GCN-NEXT: v_subrev_i32_e64 v4, s[0:1], s6, v0 -; GCN-NEXT: v_subbrev_u32_e64 v5, s[2:3], 0, v2, s[0:1] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s7, v5 -; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_le_u32_e64 s[2:3], s6, v4 -; GCN-NEXT: v_subb_u32_e64 v2, s[0:1], v2, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[2:3] -; GCN-NEXT: v_cmp_eq_u32_e64 s[2:3], s7, v5 -; GCN-NEXT: v_subrev_i32_e64 v3, s[0:1], s6, v4 -; GCN-NEXT: v_cndmask_b32_e64 v6, v6, v7, s[2:3] -; GCN-NEXT: v_subbrev_u32_e64 v2, s[0:1], 0, v2, s[0:1] -; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc -; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v6 -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 -; GCN-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc -; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 -; GCN-NEXT: v_cndmask_b32_e64 v2, v5, v2, s[0:1] -; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc -; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s7, v1 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc -; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 -; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc -; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 +; GCN-NEXT: v_readfirstlane_b32 s9, v1 +; GCN-NEXT: v_readfirstlane_b32 s4, v0 +; GCN-NEXT: s_mul_i32 s5, s6, s9 +; GCN-NEXT: v_readfirstlane_b32 s12, v2 +; GCN-NEXT: s_mul_i32 s10, s8, s4 +; GCN-NEXT: s_mul_i32 s11, s6, s4 +; GCN-NEXT: s_add_i32 s5, s12, s5 +; GCN-NEXT: v_mul_hi_u32 v3, v0, s11 +; GCN-NEXT: s_add_i32 s5, s5, s10 +; GCN-NEXT: v_mul_hi_u32 v0, v0, s5 +; GCN-NEXT: v_mul_hi_u32 v4, v1, s11 +; GCN-NEXT: v_readfirstlane_b32 s10, v3 +; GCN-NEXT: v_mul_hi_u32 v1, v1, s5 +; GCN-NEXT: s_mul_i32 s13, s4, s5 +; GCN-NEXT: s_add_u32 s10, s10, s13 +; GCN-NEXT: v_readfirstlane_b32 s13, v0 +; GCN-NEXT: s_mul_i32 s11, s9, s11 +; GCN-NEXT: s_addc_u32 s13, 0, s13 +; GCN-NEXT: v_readfirstlane_b32 s12, v4 +; GCN-NEXT: s_add_u32 s10, s10, s11 +; GCN-NEXT: v_readfirstlane_b32 s14, v1 +; GCN-NEXT: s_addc_u32 s10, s13, s12 +; GCN-NEXT: s_addc_u32 s11, s14, 0 +; GCN-NEXT: s_mul_i32 s5, s9, s5 +; GCN-NEXT: s_add_u32 s5, s10, s5 +; GCN-NEXT: s_addc_u32 s10, 0, s11 +; GCN-NEXT: s_add_i32 s11, s4, s5 +; GCN-NEXT: v_mov_b32_e32 v0, s11 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: v_mul_hi_u32 v0, s6, v0 +; GCN-NEXT: s_or_b32 s4, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_addc_u32 s9, s9, s10 +; GCN-NEXT: s_mul_i32 s4, s6, s9 +; GCN-NEXT: v_readfirstlane_b32 s5, v0 +; GCN-NEXT: s_add_i32 s4, s5, s4 +; GCN-NEXT: s_mul_i32 s8, s8, s11 +; GCN-NEXT: s_mul_i32 s5, s6, s11 +; GCN-NEXT: s_add_i32 s4, s4, s8 +; GCN-NEXT: v_mov_b32_e32 v2, s5 +; GCN-NEXT: v_mov_b32_e32 v0, s4 +; GCN-NEXT: v_mul_hi_u32 v3, s9, v2 +; GCN-NEXT: v_mul_hi_u32 v2, s11, v2 +; GCN-NEXT: v_mul_hi_u32 v1, s9, v0 +; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 +; GCN-NEXT: s_mul_i32 s8, s11, s4 +; GCN-NEXT: v_readfirstlane_b32 s12, v2 +; GCN-NEXT: s_add_u32 s8, s12, s8 +; GCN-NEXT: v_readfirstlane_b32 s10, v0 +; GCN-NEXT: s_mul_i32 s5, s9, s5 +; GCN-NEXT: s_addc_u32 s10, 0, s10 +; GCN-NEXT: v_readfirstlane_b32 s6, v3 +; GCN-NEXT: s_add_u32 s5, s8, s5 +; GCN-NEXT: s_addc_u32 s5, s10, s6 +; GCN-NEXT: v_readfirstlane_b32 s6, v1 +; GCN-NEXT: s_addc_u32 s6, s6, 0 +; GCN-NEXT: s_mul_i32 s4, s9, s4 +; GCN-NEXT: s_add_u32 s4, s5, s4 +; GCN-NEXT: s_addc_u32 s6, 0, s6 +; GCN-NEXT: s_add_i32 s11, s11, s4 +; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_or_b32 s4, s4, s5 +; GCN-NEXT: s_cmp_lg_u32 s4, 0 +; GCN-NEXT: s_addc_u32 s4, s9, s6 +; GCN-NEXT: v_mul_hi_u32 v1, s11, 24 +; GCN-NEXT: v_mul_hi_u32 v0, s4, 24 +; GCN-NEXT: s_mul_i32 s4, s4, 24 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: v_readfirstlane_b32 s8, v1 +; GCN-NEXT: v_readfirstlane_b32 s5, v0 +; GCN-NEXT: s_add_u32 s4, s8, s4 +; GCN-NEXT: s_addc_u32 s8, 0, s5 +; GCN-NEXT: v_mov_b32_e32 v0, s8 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mul_i32 s0, s3, s8 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_add_i32 s9, s1, s0 +; GCN-NEXT: s_sub_i32 s10, 0, s9 +; GCN-NEXT: s_mul_i32 s0, s2, s8 +; GCN-NEXT: s_sub_i32 s8, 24, s0 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_or_b32 s11, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s11, 0 +; GCN-NEXT: s_subb_u32 s10, s10, s3 +; GCN-NEXT: s_sub_i32 s12, s8, s2 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_subb_u32 s13, s10, 0 +; GCN-NEXT: s_cmp_ge_u32 s13, s3 +; GCN-NEXT: s_cselect_b32 s1, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s12, s2 +; GCN-NEXT: s_cselect_b32 s14, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s13, s3 +; GCN-NEXT: s_cselect_b32 s14, s14, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_subb_u32 s10, s10, s3 +; GCN-NEXT: s_sub_i32 s15, s12, s2 +; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_or_b32 s0, s0, s1 +; GCN-NEXT: s_cmp_lg_u32 s0, 0 +; GCN-NEXT: s_subb_u32 s0, s10, 0 +; GCN-NEXT: s_cmp_lg_u32 s14, 0 +; GCN-NEXT: s_cselect_b32 s1, s15, s12 +; GCN-NEXT: s_cselect_b32 s0, s0, s13 +; GCN-NEXT: s_cmp_lg_u32 s11, 0 +; GCN-NEXT: s_subb_u32 s9, 0, s9 +; GCN-NEXT: s_cmp_ge_u32 s9, s3 +; GCN-NEXT: s_cselect_b32 s10, -1, 0 +; GCN-NEXT: s_cmp_ge_u32 s8, s2 +; GCN-NEXT: s_cselect_b32 s2, -1, 0 +; GCN-NEXT: s_cmp_eq_u32 s9, s3 +; GCN-NEXT: s_cselect_b32 s2, s2, s10 +; GCN-NEXT: s_cmp_lg_u32 s2, 0 +; GCN-NEXT: s_cselect_b32 s0, s0, s9 +; GCN-NEXT: s_cselect_b32 s1, s1, s8 +; GCN-NEXT: v_mov_b32_e32 v0, s1 +; GCN-NEXT: v_mov_b32_e32 v1, s0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem_k_num_i64: diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll index 2a76d83cd7dac..89f719da21ebf 100644 --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -730,19 +730,19 @@ bb: define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1032-LABEL: test_udiv64: ; GFX1032: ; %bb.0: ; %bb -; GFX1032-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 +; GFX1032-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 ; GFX1032-NEXT: s_waitcnt lgkmcnt(0) -; GFX1032-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 +; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0 ; GFX1032-NEXT: s_waitcnt lgkmcnt(0) -; GFX1032-NEXT: s_or_b64 s[8:9], s[6:7], s[4:5] -; GFX1032-NEXT: s_mov_b32 s8, 0 -; GFX1032-NEXT: s_cmp_lg_u64 s[8:9], 0 +; GFX1032-NEXT: s_or_b64 s[4:5], s[2:3], s[0:1] +; GFX1032-NEXT: s_mov_b32 s4, 0 +; GFX1032-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX1032-NEXT: s_cbranch_scc0 .LBB15_4 ; GFX1032-NEXT: ; %bb.1: -; GFX1032-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GFX1032-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GFX1032-NEXT: s_sub_u32 s9, 0, s4 -; GFX1032-NEXT: s_subb_u32 s10, 0, s5 +; GFX1032-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GFX1032-NEXT: v_cvt_f32_u32_e32 v1, s1 +; GFX1032-NEXT: s_sub_u32 s9, 0, s0 +; GFX1032-NEXT: s_subb_u32 s10, 0, s1 ; GFX1032-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GFX1032-NEXT: v_rcp_f32_e32 v0, v0 ; GFX1032-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -751,160 +751,158 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1032-NEXT: v_madmk_f32 v0, v1, 0xcf800000, v0 ; GFX1032-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX1032-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1032-NEXT: v_readfirstlane_b32 s0, v1 -; GFX1032-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1032-NEXT: s_mul_i32 s11, s9, s0 -; GFX1032-NEXT: s_mul_hi_u32 s13, s9, s1 -; GFX1032-NEXT: s_mul_i32 s12, s10, s1 +; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s8, v0 +; GFX1032-NEXT: s_mul_i32 s11, s9, s5 +; GFX1032-NEXT: s_mul_hi_u32 s13, s9, s8 +; GFX1032-NEXT: s_mul_i32 s12, s10, s8 ; GFX1032-NEXT: s_add_i32 s11, s13, s11 -; GFX1032-NEXT: s_mul_i32 s14, s9, s1 +; GFX1032-NEXT: s_mul_i32 s14, s9, s8 ; GFX1032-NEXT: s_add_i32 s11, s11, s12 -; GFX1032-NEXT: s_mul_hi_u32 s13, s1, s14 -; GFX1032-NEXT: s_mul_hi_u32 s15, s0, s14 -; GFX1032-NEXT: s_mul_i32 s12, s0, s14 -; GFX1032-NEXT: s_mul_hi_u32 s14, s1, s11 -; GFX1032-NEXT: s_mul_i32 s1, s1, s11 -; GFX1032-NEXT: s_mul_hi_u32 s16, s0, s11 -; GFX1032-NEXT: s_add_u32 s1, s13, s1 -; GFX1032-NEXT: s_addc_u32 s13, 0, s14 -; GFX1032-NEXT: s_add_u32 s1, s1, s12 -; GFX1032-NEXT: s_mul_i32 s11, s0, s11 -; GFX1032-NEXT: s_addc_u32 s1, s13, s15 -; GFX1032-NEXT: s_addc_u32 s12, s16, 0 -; GFX1032-NEXT: s_add_u32 s1, s1, s11 -; GFX1032-NEXT: s_addc_u32 s11, 0, s12 -; GFX1032-NEXT: v_add_co_u32 v0, s1, v0, s1 -; GFX1032-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1032-NEXT: s_addc_u32 s0, s0, s11 -; GFX1032-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1032-NEXT: s_mul_i32 s11, s9, s0 -; GFX1032-NEXT: s_mul_hi_u32 s12, s9, s1 -; GFX1032-NEXT: s_mul_i32 s10, s10, s1 -; GFX1032-NEXT: s_add_i32 s11, s12, s11 -; GFX1032-NEXT: s_mul_i32 s9, s9, s1 -; GFX1032-NEXT: s_add_i32 s11, s11, s10 -; GFX1032-NEXT: s_mul_hi_u32 s12, s0, s9 -; GFX1032-NEXT: s_mul_i32 s13, s0, s9 -; GFX1032-NEXT: s_mul_hi_u32 s9, s1, s9 -; GFX1032-NEXT: s_mul_hi_u32 s14, s1, s11 -; GFX1032-NEXT: s_mul_i32 s1, s1, s11 -; GFX1032-NEXT: s_mul_hi_u32 s10, s0, s11 -; GFX1032-NEXT: s_add_u32 s1, s9, s1 -; GFX1032-NEXT: s_addc_u32 s9, 0, s14 -; GFX1032-NEXT: s_add_u32 s1, s1, s13 -; GFX1032-NEXT: s_mul_i32 s11, s0, s11 -; GFX1032-NEXT: s_addc_u32 s1, s9, s12 -; GFX1032-NEXT: s_addc_u32 s9, s10, 0 -; GFX1032-NEXT: s_add_u32 s1, s1, s11 -; GFX1032-NEXT: s_addc_u32 s9, 0, s9 -; GFX1032-NEXT: v_add_co_u32 v0, s1, v0, s1 -; GFX1032-NEXT: s_cmp_lg_u32 s1, 0 -; GFX1032-NEXT: s_addc_u32 s0, s0, s9 -; GFX1032-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1032-NEXT: s_mul_i32 s10, s6, s0 -; GFX1032-NEXT: s_mul_hi_u32 s9, s6, s0 -; GFX1032-NEXT: s_mul_hi_u32 s11, s7, s0 -; GFX1032-NEXT: s_mul_i32 s0, s7, s0 -; GFX1032-NEXT: s_mul_hi_u32 s12, s6, s1 -; GFX1032-NEXT: s_mul_hi_u32 s13, s7, s1 -; GFX1032-NEXT: s_mul_i32 s1, s7, s1 -; GFX1032-NEXT: s_add_u32 s10, s12, s10 -; GFX1032-NEXT: s_addc_u32 s9, 0, s9 -; GFX1032-NEXT: s_add_u32 s1, s10, s1 -; GFX1032-NEXT: s_addc_u32 s1, s9, s13 -; GFX1032-NEXT: s_addc_u32 s9, s11, 0 -; GFX1032-NEXT: s_add_u32 s1, s1, s0 -; GFX1032-NEXT: s_addc_u32 s9, 0, s9 -; GFX1032-NEXT: s_mul_hi_u32 s0, s4, s1 -; GFX1032-NEXT: s_mul_i32 s11, s4, s9 -; GFX1032-NEXT: s_mul_i32 s12, s4, s1 -; GFX1032-NEXT: s_add_i32 s0, s0, s11 -; GFX1032-NEXT: v_sub_co_u32 v0, s11, s6, s12 -; GFX1032-NEXT: s_mul_i32 s10, s5, s1 -; GFX1032-NEXT: s_add_i32 s0, s0, s10 -; GFX1032-NEXT: v_sub_co_u32 v1, s12, v0, s4 -; GFX1032-NEXT: s_sub_i32 s10, s7, s0 +; GFX1032-NEXT: s_mul_hi_u32 s13, s8, s14 +; GFX1032-NEXT: s_mul_i32 s16, s8, s11 +; GFX1032-NEXT: s_mul_hi_u32 s15, s5, s14 +; GFX1032-NEXT: s_mul_i32 s12, s5, s14 +; GFX1032-NEXT: s_mul_hi_u32 s14, s8, s11 +; GFX1032-NEXT: s_add_u32 s13, s13, s16 +; GFX1032-NEXT: s_addc_u32 s14, 0, s14 +; GFX1032-NEXT: s_mul_hi_u32 s17, s5, s11 +; GFX1032-NEXT: s_add_u32 s12, s13, s12 +; GFX1032-NEXT: s_mul_i32 s11, s5, s11 +; GFX1032-NEXT: s_addc_u32 s12, s14, s15 +; GFX1032-NEXT: s_addc_u32 s13, s17, 0 +; GFX1032-NEXT: s_add_u32 s11, s12, s11 +; GFX1032-NEXT: s_addc_u32 s12, 0, s13 +; GFX1032-NEXT: s_add_i32 s8, s8, s11 +; GFX1032-NEXT: s_cselect_b32 s11, 1, 0 +; GFX1032-NEXT: s_mul_hi_u32 s13, s9, s8 ; GFX1032-NEXT: s_cmp_lg_u32 s11, 0 -; GFX1032-NEXT: s_subb_u32 s10, s10, s5 +; GFX1032-NEXT: s_mul_i32 s11, s9, s8 +; GFX1032-NEXT: s_addc_u32 s5, s5, s12 +; GFX1032-NEXT: s_mul_i32 s10, s10, s8 +; GFX1032-NEXT: s_mul_i32 s9, s9, s5 +; GFX1032-NEXT: s_mul_hi_u32 s12, s8, s11 +; GFX1032-NEXT: s_add_i32 s9, s13, s9 +; GFX1032-NEXT: s_mul_hi_u32 s13, s5, s11 +; GFX1032-NEXT: s_add_i32 s9, s9, s10 +; GFX1032-NEXT: s_mul_i32 s10, s5, s11 +; GFX1032-NEXT: s_mul_i32 s15, s8, s9 +; GFX1032-NEXT: s_mul_hi_u32 s14, s8, s9 +; GFX1032-NEXT: s_add_u32 s12, s12, s15 +; GFX1032-NEXT: s_addc_u32 s14, 0, s14 +; GFX1032-NEXT: s_mul_hi_u32 s11, s5, s9 +; GFX1032-NEXT: s_add_u32 s10, s12, s10 +; GFX1032-NEXT: s_mul_i32 s9, s5, s9 +; GFX1032-NEXT: s_addc_u32 s10, s14, s13 +; GFX1032-NEXT: s_addc_u32 s11, s11, 0 +; GFX1032-NEXT: s_add_u32 s9, s10, s9 +; GFX1032-NEXT: s_addc_u32 s10, 0, s11 +; GFX1032-NEXT: s_add_i32 s8, s8, s9 +; GFX1032-NEXT: s_cselect_b32 s9, 1, 0 +; GFX1032-NEXT: s_mul_hi_u32 s11, s2, s8 +; GFX1032-NEXT: s_cmp_lg_u32 s9, 0 +; GFX1032-NEXT: s_mul_hi_u32 s9, s3, s8 +; GFX1032-NEXT: s_addc_u32 s5, s5, s10 +; GFX1032-NEXT: s_mul_i32 s8, s3, s8 +; GFX1032-NEXT: s_mul_i32 s12, s2, s5 +; GFX1032-NEXT: s_mul_hi_u32 s10, s2, s5 +; GFX1032-NEXT: s_add_u32 s11, s11, s12 +; GFX1032-NEXT: s_addc_u32 s10, 0, s10 +; GFX1032-NEXT: s_mul_hi_u32 s13, s3, s5 +; GFX1032-NEXT: s_add_u32 s8, s11, s8 +; GFX1032-NEXT: s_mul_i32 s5, s3, s5 +; GFX1032-NEXT: s_addc_u32 s8, s10, s9 +; GFX1032-NEXT: s_addc_u32 s9, s13, 0 +; GFX1032-NEXT: s_add_u32 s5, s8, s5 +; GFX1032-NEXT: s_addc_u32 s8, 0, s9 +; GFX1032-NEXT: s_mul_hi_u32 s9, s0, s5 +; GFX1032-NEXT: s_mul_i32 s10, s0, s8 +; GFX1032-NEXT: s_mul_i32 s11, s1, s5 +; GFX1032-NEXT: s_add_i32 s9, s9, s10 +; GFX1032-NEXT: s_mul_i32 s10, s0, s5 +; GFX1032-NEXT: s_add_i32 s9, s9, s11 +; GFX1032-NEXT: s_sub_i32 s11, s3, s9 +; GFX1032-NEXT: s_sub_i32 s10, s2, s10 +; GFX1032-NEXT: s_cselect_b32 s12, 1, 0 ; GFX1032-NEXT: s_cmp_lg_u32 s12, 0 -; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v1 -; GFX1032-NEXT: s_subb_u32 s10, s10, 0 -; GFX1032-NEXT: s_cmp_ge_u32 s10, s5 -; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo -; GFX1032-NEXT: s_cselect_b32 s12, -1, 0 -; GFX1032-NEXT: s_cmp_eq_u32 s10, s5 -; GFX1032-NEXT: s_cselect_b32 vcc_lo, -1, 0 -; GFX1032-NEXT: s_add_u32 s10, s1, 1 -; GFX1032-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo -; GFX1032-NEXT: s_addc_u32 s12, s9, 0 -; GFX1032-NEXT: s_add_u32 s13, s1, 2 -; GFX1032-NEXT: s_addc_u32 s14, s9, 0 +; GFX1032-NEXT: s_subb_u32 s11, s11, s1 +; GFX1032-NEXT: s_sub_i32 s13, s10, s0 +; GFX1032-NEXT: s_cselect_b32 s14, 1, 0 +; GFX1032-NEXT: s_cmp_lg_u32 s14, 0 +; GFX1032-NEXT: s_subb_u32 s11, s11, 0 +; GFX1032-NEXT: s_cmp_ge_u32 s11, s1 +; GFX1032-NEXT: s_cselect_b32 s14, -1, 0 +; GFX1032-NEXT: s_cmp_ge_u32 s13, s0 +; GFX1032-NEXT: s_cselect_b32 s13, -1, 0 +; GFX1032-NEXT: s_cmp_eq_u32 s11, s1 +; GFX1032-NEXT: s_cselect_b32 s11, s13, s14 +; GFX1032-NEXT: s_add_u32 s13, s5, 1 +; GFX1032-NEXT: s_addc_u32 s14, s8, 0 +; GFX1032-NEXT: s_add_u32 s15, s5, 2 +; GFX1032-NEXT: s_addc_u32 s16, s8, 0 ; GFX1032-NEXT: s_cmp_lg_u32 s11, 0 -; GFX1032-NEXT: v_cmp_le_u32_e32 vcc_lo, s4, v0 -; GFX1032-NEXT: s_subb_u32 s0, s7, s0 -; GFX1032-NEXT: v_mov_b32_e32 v2, s13 -; GFX1032-NEXT: s_cmp_ge_u32 s0, s5 -; GFX1032-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc_lo -; GFX1032-NEXT: s_cselect_b32 s7, -1, 0 -; GFX1032-NEXT: s_cmp_eq_u32 s0, s5 -; GFX1032-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1 -; GFX1032-NEXT: s_cselect_b32 s0, -1, 0 -; GFX1032-NEXT: v_mov_b32_e32 v1, s14 -; GFX1032-NEXT: v_cndmask_b32_e64 v0, s7, v0, s0 -; GFX1032-NEXT: v_cndmask_b32_e32 v2, s10, v2, vcc_lo -; GFX1032-NEXT: v_cndmask_b32_e32 v1, s12, v1, vcc_lo -; GFX1032-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0 -; GFX1032-NEXT: v_cndmask_b32_e32 v1, s9, v1, vcc_lo -; GFX1032-NEXT: v_cndmask_b32_e32 v0, s1, v2, vcc_lo -; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s8 +; GFX1032-NEXT: s_cselect_b32 s11, s15, s13 +; GFX1032-NEXT: s_cselect_b32 s13, s16, s14 +; GFX1032-NEXT: s_cmp_lg_u32 s12, 0 +; GFX1032-NEXT: s_subb_u32 s3, s3, s9 +; GFX1032-NEXT: s_cmp_ge_u32 s3, s1 +; GFX1032-NEXT: s_cselect_b32 s9, -1, 0 +; GFX1032-NEXT: s_cmp_ge_u32 s10, s0 +; GFX1032-NEXT: s_cselect_b32 s10, -1, 0 +; GFX1032-NEXT: s_cmp_eq_u32 s3, s1 +; GFX1032-NEXT: s_cselect_b32 s1, s10, s9 +; GFX1032-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1032-NEXT: s_cselect_b32 s9, s13, s8 +; GFX1032-NEXT: s_cselect_b32 s8, s11, s5 +; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4 ; GFX1032-NEXT: s_cbranch_vccnz .LBB15_3 ; GFX1032-NEXT: .LBB15_2: -; GFX1032-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GFX1032-NEXT: s_sub_i32 s1, 0, s4 +; GFX1032-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GFX1032-NEXT: s_sub_i32 s3, 0, s0 +; GFX1032-NEXT: s_mov_b32 s9, 0 ; GFX1032-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX1032-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX1032-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1032-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1032-NEXT: s_mul_i32 s1, s1, s0 -; GFX1032-NEXT: s_mul_hi_u32 s1, s0, s1 -; GFX1032-NEXT: s_add_i32 s0, s0, s1 -; GFX1032-NEXT: s_mul_hi_u32 s0, s6, s0 -; GFX1032-NEXT: s_mul_i32 s1, s0, s4 -; GFX1032-NEXT: s_add_i32 s5, s0, 1 -; GFX1032-NEXT: s_sub_i32 s1, s6, s1 -; GFX1032-NEXT: s_sub_i32 s6, s1, s4 -; GFX1032-NEXT: s_cmp_ge_u32 s1, s4 -; GFX1032-NEXT: s_cselect_b32 s0, s5, s0 -; GFX1032-NEXT: s_cselect_b32 s1, s6, s1 -; GFX1032-NEXT: s_add_i32 s5, s0, 1 -; GFX1032-NEXT: s_cmp_ge_u32 s1, s4 -; GFX1032-NEXT: s_mov_b32 s1, 0 -; GFX1032-NEXT: s_cselect_b32 s0, s5, s0 -; GFX1032-NEXT: v_mov_b32_e32 v0, s0 -; GFX1032-NEXT: v_mov_b32_e32 v1, s1 +; GFX1032-NEXT: v_readfirstlane_b32 s1, v0 +; GFX1032-NEXT: s_mul_i32 s3, s3, s1 +; GFX1032-NEXT: s_mul_hi_u32 s3, s1, s3 +; GFX1032-NEXT: s_add_i32 s1, s1, s3 +; GFX1032-NEXT: s_mul_hi_u32 s1, s2, s1 +; GFX1032-NEXT: s_mul_i32 s3, s1, s0 +; GFX1032-NEXT: s_sub_i32 s2, s2, s3 +; GFX1032-NEXT: s_add_i32 s3, s1, 1 +; GFX1032-NEXT: s_sub_i32 s4, s2, s0 +; GFX1032-NEXT: s_cmp_ge_u32 s2, s0 +; GFX1032-NEXT: s_cselect_b32 s1, s3, s1 +; GFX1032-NEXT: s_cselect_b32 s2, s4, s2 +; GFX1032-NEXT: s_add_i32 s3, s1, 1 +; GFX1032-NEXT: s_cmp_ge_u32 s2, s0 +; GFX1032-NEXT: s_cselect_b32 s8, s3, s1 ; GFX1032-NEXT: .LBB15_3: +; GFX1032-NEXT: v_mov_b32_e32 v0, s8 ; GFX1032-NEXT: v_mov_b32_e32 v2, 0 -; GFX1032-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] offset:16 +; GFX1032-NEXT: v_mov_b32_e32 v1, s9 +; GFX1032-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] offset:16 ; GFX1032-NEXT: s_endpgm ; GFX1032-NEXT: .LBB15_4: -; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1032-NEXT: ; implicit-def: $sgpr8_sgpr9 ; GFX1032-NEXT: s_branch .LBB15_2 ; ; GFX1064-LABEL: test_udiv64: ; GFX1064: ; %bb.0: ; %bb -; GFX1064-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24 +; GFX1064-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24 ; GFX1064-NEXT: s_waitcnt lgkmcnt(0) -; GFX1064-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0 +; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[6:7], 0x0 ; GFX1064-NEXT: s_waitcnt lgkmcnt(0) -; GFX1064-NEXT: s_or_b64 s[0:1], s[6:7], s[4:5] -; GFX1064-NEXT: s_mov_b32 s0, 0 -; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1064-NEXT: s_or_b64 s[4:5], s[2:3], s[0:1] +; GFX1064-NEXT: s_mov_b32 s4, 0 +; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX1064-NEXT: s_cbranch_scc0 .LBB15_4 ; GFX1064-NEXT: ; %bb.1: -; GFX1064-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GFX1064-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GFX1064-NEXT: s_sub_u32 s9, 0, s4 -; GFX1064-NEXT: s_subb_u32 s10, 0, s5 +; GFX1064-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GFX1064-NEXT: v_cvt_f32_u32_e32 v1, s1 +; GFX1064-NEXT: s_sub_u32 s9, 0, s0 +; GFX1064-NEXT: s_subb_u32 s10, 0, s1 ; GFX1064-NEXT: v_madmk_f32 v0, v1, 0x4f800000, v0 ; GFX1064-NEXT: v_rcp_f32_e32 v0, v0 ; GFX1064-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 @@ -914,141 +912,139 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1064-NEXT: v_cvt_u32_f32_e32 v1, v1 ; GFX1064-NEXT: v_cvt_u32_f32_e32 v0, v0 ; GFX1064-NEXT: v_readfirstlane_b32 s8, v1 -; GFX1064-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1064-NEXT: s_mul_i32 s1, s9, s8 -; GFX1064-NEXT: s_mul_hi_u32 s12, s9, s0 -; GFX1064-NEXT: s_mul_i32 s11, s10, s0 -; GFX1064-NEXT: s_add_i32 s1, s12, s1 -; GFX1064-NEXT: s_mul_i32 s13, s9, s0 -; GFX1064-NEXT: s_add_i32 s1, s1, s11 -; GFX1064-NEXT: s_mul_hi_u32 s12, s0, s13 +; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1064-NEXT: s_mul_i32 s5, s9, s8 +; GFX1064-NEXT: s_mul_hi_u32 s12, s9, s4 +; GFX1064-NEXT: s_mul_i32 s11, s10, s4 +; GFX1064-NEXT: s_add_i32 s5, s12, s5 +; GFX1064-NEXT: s_mul_i32 s13, s9, s4 +; GFX1064-NEXT: s_add_i32 s5, s5, s11 +; GFX1064-NEXT: s_mul_hi_u32 s12, s4, s13 +; GFX1064-NEXT: s_mul_i32 s15, s4, s5 ; GFX1064-NEXT: s_mul_hi_u32 s14, s8, s13 ; GFX1064-NEXT: s_mul_i32 s11, s8, s13 -; GFX1064-NEXT: s_mul_hi_u32 s13, s0, s1 -; GFX1064-NEXT: s_mul_i32 s0, s0, s1 -; GFX1064-NEXT: s_mul_hi_u32 s15, s8, s1 -; GFX1064-NEXT: s_add_u32 s0, s12, s0 -; GFX1064-NEXT: s_addc_u32 s12, 0, s13 -; GFX1064-NEXT: s_add_u32 s0, s0, s11 -; GFX1064-NEXT: s_mul_i32 s1, s8, s1 -; GFX1064-NEXT: s_addc_u32 s0, s12, s14 -; GFX1064-NEXT: s_addc_u32 s11, s15, 0 -; GFX1064-NEXT: s_add_u32 s0, s0, s1 -; GFX1064-NEXT: s_addc_u32 s11, 0, s11 -; GFX1064-NEXT: v_add_co_u32 v0, s[0:1], v0, s0 -; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0 +; GFX1064-NEXT: s_mul_hi_u32 s13, s4, s5 +; GFX1064-NEXT: s_add_u32 s12, s12, s15 +; GFX1064-NEXT: s_addc_u32 s13, 0, s13 +; GFX1064-NEXT: s_mul_hi_u32 s16, s8, s5 +; GFX1064-NEXT: s_add_u32 s11, s12, s11 +; GFX1064-NEXT: s_mul_i32 s5, s8, s5 +; GFX1064-NEXT: s_addc_u32 s11, s13, s14 +; GFX1064-NEXT: s_addc_u32 s12, s16, 0 +; GFX1064-NEXT: s_add_u32 s5, s11, s5 +; GFX1064-NEXT: s_addc_u32 s11, 0, s12 +; GFX1064-NEXT: s_add_i32 s12, s4, s5 +; GFX1064-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX1064-NEXT: s_mul_hi_u32 s13, s9, s12 +; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX1064-NEXT: s_mul_i32 s4, s9, s12 ; GFX1064-NEXT: s_addc_u32 s8, s8, s11 -; GFX1064-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1064-NEXT: s_mul_i32 s1, s9, s8 -; GFX1064-NEXT: s_mul_hi_u32 s11, s9, s0 -; GFX1064-NEXT: s_mul_i32 s10, s10, s0 -; GFX1064-NEXT: s_add_i32 s1, s11, s1 -; GFX1064-NEXT: s_mul_i32 s9, s9, s0 -; GFX1064-NEXT: s_add_i32 s1, s1, s10 -; GFX1064-NEXT: s_mul_hi_u32 s11, s8, s9 -; GFX1064-NEXT: s_mul_i32 s12, s8, s9 -; GFX1064-NEXT: s_mul_hi_u32 s9, s0, s9 -; GFX1064-NEXT: s_mul_hi_u32 s13, s0, s1 -; GFX1064-NEXT: s_mul_i32 s0, s0, s1 -; GFX1064-NEXT: s_mul_hi_u32 s10, s8, s1 -; GFX1064-NEXT: s_add_u32 s0, s9, s0 -; GFX1064-NEXT: s_addc_u32 s9, 0, s13 -; GFX1064-NEXT: s_add_u32 s0, s0, s12 -; GFX1064-NEXT: s_mul_i32 s1, s8, s1 -; GFX1064-NEXT: s_addc_u32 s0, s9, s11 -; GFX1064-NEXT: s_addc_u32 s9, s10, 0 -; GFX1064-NEXT: s_add_u32 s0, s0, s1 +; GFX1064-NEXT: s_mul_i32 s10, s10, s12 +; GFX1064-NEXT: s_mul_i32 s9, s9, s8 +; GFX1064-NEXT: s_mul_hi_u32 s5, s12, s4 +; GFX1064-NEXT: s_add_i32 s9, s13, s9 +; GFX1064-NEXT: s_mul_hi_u32 s11, s8, s4 +; GFX1064-NEXT: s_add_i32 s9, s9, s10 +; GFX1064-NEXT: s_mul_i32 s4, s8, s4 +; GFX1064-NEXT: s_mul_i32 s14, s12, s9 +; GFX1064-NEXT: s_mul_hi_u32 s13, s12, s9 +; GFX1064-NEXT: s_add_u32 s5, s5, s14 +; GFX1064-NEXT: s_addc_u32 s13, 0, s13 +; GFX1064-NEXT: s_mul_hi_u32 s10, s8, s9 +; GFX1064-NEXT: s_add_u32 s4, s5, s4 +; GFX1064-NEXT: s_mul_i32 s9, s8, s9 +; GFX1064-NEXT: s_addc_u32 s4, s13, s11 +; GFX1064-NEXT: s_addc_u32 s5, s10, 0 +; GFX1064-NEXT: s_add_u32 s4, s4, s9 +; GFX1064-NEXT: s_addc_u32 s9, 0, s5 +; GFX1064-NEXT: s_add_i32 s12, s12, s4 +; GFX1064-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX1064-NEXT: s_mul_hi_u32 s10, s2, s12 +; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX1064-NEXT: s_mul_hi_u32 s4, s3, s12 +; GFX1064-NEXT: s_addc_u32 s5, s8, s9 +; GFX1064-NEXT: s_mul_i32 s8, s3, s12 +; GFX1064-NEXT: s_mul_i32 s11, s2, s5 +; GFX1064-NEXT: s_mul_hi_u32 s9, s2, s5 +; GFX1064-NEXT: s_add_u32 s10, s10, s11 ; GFX1064-NEXT: s_addc_u32 s9, 0, s9 -; GFX1064-NEXT: v_add_co_u32 v0, s[0:1], v0, s0 -; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1064-NEXT: s_addc_u32 s0, s8, s9 -; GFX1064-NEXT: v_readfirstlane_b32 s1, v0 -; GFX1064-NEXT: s_mul_i32 s9, s6, s0 -; GFX1064-NEXT: s_mul_hi_u32 s8, s6, s0 -; GFX1064-NEXT: s_mul_hi_u32 s10, s7, s0 -; GFX1064-NEXT: s_mul_i32 s0, s7, s0 -; GFX1064-NEXT: s_mul_hi_u32 s11, s6, s1 -; GFX1064-NEXT: s_mul_hi_u32 s12, s7, s1 -; GFX1064-NEXT: s_mul_i32 s1, s7, s1 -; GFX1064-NEXT: s_add_u32 s9, s11, s9 -; GFX1064-NEXT: s_addc_u32 s8, 0, s8 -; GFX1064-NEXT: s_add_u32 s1, s9, s1 -; GFX1064-NEXT: s_addc_u32 s1, s8, s12 -; GFX1064-NEXT: s_addc_u32 s8, s10, 0 -; GFX1064-NEXT: s_add_u32 s10, s1, s0 +; GFX1064-NEXT: s_mul_hi_u32 s12, s3, s5 +; GFX1064-NEXT: s_add_u32 s8, s10, s8 +; GFX1064-NEXT: s_mul_i32 s5, s3, s5 +; GFX1064-NEXT: s_addc_u32 s4, s9, s4 +; GFX1064-NEXT: s_addc_u32 s8, s12, 0 +; GFX1064-NEXT: s_add_u32 s10, s4, s5 ; GFX1064-NEXT: s_addc_u32 s11, 0, s8 -; GFX1064-NEXT: s_mul_hi_u32 s0, s4, s10 -; GFX1064-NEXT: s_mul_i32 s1, s4, s11 -; GFX1064-NEXT: s_mul_i32 s9, s4, s10 -; GFX1064-NEXT: s_add_i32 s12, s0, s1 -; GFX1064-NEXT: v_sub_co_u32 v0, s[0:1], s6, s9 -; GFX1064-NEXT: s_mul_i32 s8, s5, s10 -; GFX1064-NEXT: s_add_i32 s12, s12, s8 -; GFX1064-NEXT: v_sub_co_u32 v1, s[8:9], v0, s4 -; GFX1064-NEXT: s_sub_i32 s13, s7, s12 -; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1064-NEXT: s_subb_u32 s13, s13, s5 +; GFX1064-NEXT: s_mul_hi_u32 s4, s0, s10 +; GFX1064-NEXT: s_mul_i32 s5, s0, s11 +; GFX1064-NEXT: s_mul_i32 s8, s1, s10 +; GFX1064-NEXT: s_add_i32 s4, s4, s5 +; GFX1064-NEXT: s_add_i32 s12, s4, s8 +; GFX1064-NEXT: s_mul_i32 s4, s0, s10 +; GFX1064-NEXT: s_sub_i32 s8, s3, s12 +; GFX1064-NEXT: s_sub_i32 s13, s2, s4 +; GFX1064-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX1064-NEXT: s_subb_u32 s14, s8, s1 +; GFX1064-NEXT: s_sub_i32 s15, s13, s0 +; GFX1064-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GFX1064-NEXT: s_cmp_lg_u64 s[8:9], 0 -; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s4, v1 -; GFX1064-NEXT: s_subb_u32 s8, s13, 0 -; GFX1064-NEXT: s_cmp_ge_u32 s8, s5 -; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX1064-NEXT: s_subb_u32 s8, s14, 0 +; GFX1064-NEXT: s_cmp_ge_u32 s8, s1 ; GFX1064-NEXT: s_cselect_b32 s9, -1, 0 -; GFX1064-NEXT: s_cmp_eq_u32 s8, s5 -; GFX1064-NEXT: s_cselect_b64 vcc, -1, 0 -; GFX1064-NEXT: s_add_u32 s8, s10, 1 -; GFX1064-NEXT: v_cndmask_b32_e32 v1, s9, v1, vcc -; GFX1064-NEXT: s_addc_u32 s9, s11, 0 -; GFX1064-NEXT: s_add_u32 s13, s10, 2 +; GFX1064-NEXT: s_cmp_ge_u32 s15, s0 +; GFX1064-NEXT: s_cselect_b32 s14, -1, 0 +; GFX1064-NEXT: s_cmp_eq_u32 s8, s1 +; GFX1064-NEXT: s_cselect_b32 s8, s14, s9 +; GFX1064-NEXT: s_add_u32 s9, s10, 1 ; GFX1064-NEXT: s_addc_u32 s14, s11, 0 -; GFX1064-NEXT: s_cmp_lg_u64 s[0:1], 0 -; GFX1064-NEXT: v_cmp_le_u32_e32 vcc, s4, v0 -; GFX1064-NEXT: s_subb_u32 s0, s7, s12 -; GFX1064-NEXT: v_mov_b32_e32 v2, s13 -; GFX1064-NEXT: s_cmp_ge_u32 s0, s5 -; GFX1064-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc -; GFX1064-NEXT: s_cselect_b32 s7, -1, 0 -; GFX1064-NEXT: s_cmp_eq_u32 s0, s5 -; GFX1064-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 -; GFX1064-NEXT: s_cselect_b64 s[0:1], -1, 0 -; GFX1064-NEXT: v_mov_b32_e32 v1, s14 -; GFX1064-NEXT: v_cndmask_b32_e64 v0, s7, v0, s[0:1] -; GFX1064-NEXT: v_cndmask_b32_e32 v2, s8, v2, vcc -; GFX1064-NEXT: v_cndmask_b32_e32 v1, s9, v1, vcc -; GFX1064-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 -; GFX1064-NEXT: v_cndmask_b32_e32 v1, s11, v1, vcc -; GFX1064-NEXT: v_cndmask_b32_e32 v0, s10, v2, vcc +; GFX1064-NEXT: s_add_u32 s15, s10, 2 +; GFX1064-NEXT: s_addc_u32 s16, s11, 0 +; GFX1064-NEXT: s_cmp_lg_u32 s8, 0 +; GFX1064-NEXT: s_cselect_b32 s15, s15, s9 +; GFX1064-NEXT: s_cselect_b32 s14, s16, s14 +; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 +; GFX1064-NEXT: s_subb_u32 s3, s3, s12 +; GFX1064-NEXT: s_cmp_ge_u32 s3, s1 +; GFX1064-NEXT: s_cselect_b32 s4, -1, 0 +; GFX1064-NEXT: s_cmp_ge_u32 s13, s0 +; GFX1064-NEXT: s_cselect_b32 s5, -1, 0 +; GFX1064-NEXT: s_cmp_eq_u32 s3, s1 +; GFX1064-NEXT: s_cselect_b32 s1, s5, s4 +; GFX1064-NEXT: s_cmp_lg_u32 s1, 0 +; GFX1064-NEXT: s_cselect_b32 s5, s14, s11 +; GFX1064-NEXT: s_cselect_b32 s4, s15, s10 ; GFX1064-NEXT: s_cbranch_execnz .LBB15_3 ; GFX1064-NEXT: .LBB15_2: -; GFX1064-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GFX1064-NEXT: s_sub_i32 s1, 0, s4 +; GFX1064-NEXT: v_cvt_f32_u32_e32 v0, s0 +; GFX1064-NEXT: s_sub_i32 s3, 0, s0 +; GFX1064-NEXT: s_mov_b32 s5, 0 ; GFX1064-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GFX1064-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 ; GFX1064-NEXT: v_cvt_u32_f32_e32 v0, v0 -; GFX1064-NEXT: v_readfirstlane_b32 s0, v0 -; GFX1064-NEXT: s_mul_i32 s1, s1, s0 -; GFX1064-NEXT: s_mul_hi_u32 s1, s0, s1 -; GFX1064-NEXT: s_add_i32 s0, s0, s1 -; GFX1064-NEXT: s_mul_hi_u32 s0, s6, s0 -; GFX1064-NEXT: s_mul_i32 s1, s0, s4 -; GFX1064-NEXT: s_add_i32 s5, s0, 1 -; GFX1064-NEXT: s_sub_i32 s1, s6, s1 -; GFX1064-NEXT: s_sub_i32 s6, s1, s4 -; GFX1064-NEXT: s_cmp_ge_u32 s1, s4 -; GFX1064-NEXT: s_cselect_b32 s0, s5, s0 -; GFX1064-NEXT: s_cselect_b32 s1, s6, s1 -; GFX1064-NEXT: s_add_i32 s5, s0, 1 -; GFX1064-NEXT: s_cmp_ge_u32 s1, s4 -; GFX1064-NEXT: s_mov_b32 s1, 0 -; GFX1064-NEXT: s_cselect_b32 s0, s5, s0 -; GFX1064-NEXT: v_mov_b32_e32 v0, s0 -; GFX1064-NEXT: v_mov_b32_e32 v1, s1 +; GFX1064-NEXT: v_readfirstlane_b32 s1, v0 +; GFX1064-NEXT: s_mul_i32 s3, s3, s1 +; GFX1064-NEXT: s_mul_hi_u32 s3, s1, s3 +; GFX1064-NEXT: s_add_i32 s1, s1, s3 +; GFX1064-NEXT: s_mul_hi_u32 s1, s2, s1 +; GFX1064-NEXT: s_mul_i32 s3, s1, s0 +; GFX1064-NEXT: s_sub_i32 s2, s2, s3 +; GFX1064-NEXT: s_add_i32 s3, s1, 1 +; GFX1064-NEXT: s_sub_i32 s4, s2, s0 +; GFX1064-NEXT: s_cmp_ge_u32 s2, s0 +; GFX1064-NEXT: s_cselect_b32 s1, s3, s1 +; GFX1064-NEXT: s_cselect_b32 s2, s4, s2 +; GFX1064-NEXT: s_add_i32 s3, s1, 1 +; GFX1064-NEXT: s_cmp_ge_u32 s2, s0 +; GFX1064-NEXT: s_cselect_b32 s4, s3, s1 ; GFX1064-NEXT: .LBB15_3: +; GFX1064-NEXT: v_mov_b32_e32 v0, s4 ; GFX1064-NEXT: v_mov_b32_e32 v2, 0 -; GFX1064-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] offset:16 +; GFX1064-NEXT: v_mov_b32_e32 v1, s5 +; GFX1064-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] offset:16 ; GFX1064-NEXT: s_endpgm ; GFX1064-NEXT: .LBB15_4: -; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1064-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX1064-NEXT: s_branch .LBB15_2 bb: %tmp = getelementptr inbounds i64, ptr addrspace(1) %arg, i64 1 From 2c0e79c4f5cf9470969f458bc3c582757204bb5e Mon Sep 17 00:00:00 2001 From: John Lu Date: Fri, 19 Sep 2025 15:17:42 -0500 Subject: [PATCH 2/9] Add test ensuring S_UADDO_PSEUDO selection Signed-off-by: John Lu --- llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll diff --git a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll new file mode 100644 index 0000000000000..607997ecf6d1e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll @@ -0,0 +1,28 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=amdgcn-amd-amdpal -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN-ISEL %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s +; Ensure that S_UADDO_PSEUDO is selected when carryout user is S_ADD_CO_PSEUDO + +; GCN-ISEL-LABEL: name: s_uaddo_pseudo +; GCN-ISEL-LABEL: body: +; GCN-ISEL: S_UADDO_PSEUDO +; GCN-ISEL: S_ADD_CO_PSEUDO + +define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: s_uaddo_pseudo: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_add_i32 s0, s0, s1 +; CHECK-NEXT: s_cselect_b64 s[0:1], 1, 0 +; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 +; CHECK-NEXT: s_addc_u32 s0, 1, 0 +; CHECK-NEXT: ; return to shader part epilog + %pair = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val0, i32 %val1) + %carryout = extractvalue {i32, i1} %pair, 1 + %add_overflow = sext i1 %carryout to i32 + %cmp_carryout = icmp ult i32 0, %add_overflow + %zext_carryout = zext i1 %cmp_carryout to i32 + %result = add i32 %zext_carryout, 1 + ret i32 %result +} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GCN-ISEL: {{.*}} From 5fbc22d38616e03cbddbe842e050c8c52e660776 Mon Sep 17 00:00:00 2001 From: LU-JOHN Date: Mon, 22 Sep 2025 10:07:16 -0500 Subject: [PATCH 3/9] Clean up code. Co-authored-by: Matt Arsenault --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index b1368329284c3..8f28db2dc6a2d 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5956,6 +5956,10 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_XOR_B64); case AMDGPU::S_UADDO_PSEUDO: case AMDGPU::S_USUBO_PSEUDO: { +<<<<<<< HEAD +======= + const DebugLoc &DL = MI.getDebugLoc(); +>>>>>>> 27321ddcdbe2 (Clean up code.) MachineOperand &Dest0 = MI.getOperand(0); MachineOperand &Dest1 = MI.getOperand(1); MachineOperand &Src0 = MI.getOperand(2); @@ -5970,11 +5974,8 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, .add(Src1); // clang-format on - const TargetRegisterClass *Dest1RC = MRI.getRegClass(Dest1.getReg()); - unsigned Dest1Size = TRI->getRegSizeInBits(*Dest1RC); - assert(Dest1Size == 64 || Dest1Size == 32); unsigned SelOpc = - (Dest1Size == 64) ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32; + Subtarget->isWave64() ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32; BuildMI(*BB, MI, DL, TII->get(SelOpc), Dest1.getReg()).addImm(1).addImm(0); MI.eraseFromParent(); From ff4ae2cac3b1bf3a706aa271b32526703b72698c Mon Sep 17 00:00:00 2001 From: John Lu Date: Mon, 22 Sep 2025 11:02:53 -0500 Subject: [PATCH 4/9] Streamline testcase Signed-off-by: John Lu --- llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll index 607997ecf6d1e..2d380e622d028 100644 --- a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll +++ b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll @@ -8,19 +8,17 @@ ; GCN-ISEL: S_UADDO_PSEUDO ; GCN-ISEL: S_ADD_CO_PSEUDO -define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0, i32 inreg %val1) { +define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0) { ; CHECK-LABEL: s_uaddo_pseudo: ; CHECK: ; %bb.0: -; CHECK-NEXT: s_add_i32 s0, s0, s1 +; CHECK-NEXT: s_add_i32 s0, s0, 1 ; CHECK-NEXT: s_cselect_b64 s[0:1], 1, 0 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 ; CHECK-NEXT: s_addc_u32 s0, 1, 0 ; CHECK-NEXT: ; return to shader part epilog - %pair = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %val0, i32 %val1) - %carryout = extractvalue {i32, i1} %pair, 1 - %add_overflow = sext i1 %carryout to i32 - %cmp_carryout = icmp ult i32 0, %add_overflow - %zext_carryout = zext i1 %cmp_carryout to i32 + %pair = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %val0, i32 1) + %carryout = extractvalue { i32, i1 } %pair, 1 + %zext_carryout = zext i1 %carryout to i32 %result = add i32 %zext_carryout, 1 ret i32 %result } From 2474bc90141ecd94b746f97b08ca92c0f3a8e5d8 Mon Sep 17 00:00:00 2001 From: John Lu Date: Mon, 22 Sep 2025 13:03:41 -0500 Subject: [PATCH 5/9] Update tests Signed-off-by: John Lu --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 - .../AMDGPU/amdgpu-codegenprepare-idiv.ll | 232 +++++++-------- .../test/CodeGen/AMDGPU/carryout-selection.ll | 82 +++--- .../expand-scalar-carry-out-select-user.ll | 8 +- llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll | 2 +- llvm/test/CodeGen/AMDGPU/sdiv64.ll | 22 +- llvm/test/CodeGen/AMDGPU/srem.ll | 270 +++++++++--------- llvm/test/CodeGen/AMDGPU/srem64.ll | 36 +-- llvm/test/CodeGen/AMDGPU/udiv64.ll | 10 +- llvm/test/CodeGen/AMDGPU/urem64.ll | 22 +- llvm/test/CodeGen/AMDGPU/wave32.ll | 26 +- 11 files changed, 355 insertions(+), 359 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 8f28db2dc6a2d..c669b0bfb2b50 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5956,10 +5956,6 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, return lowerWaveReduce(MI, *BB, *getSubtarget(), AMDGPU::S_XOR_B64); case AMDGPU::S_UADDO_PSEUDO: case AMDGPU::S_USUBO_PSEUDO: { -<<<<<<< HEAD -======= - const DebugLoc &DL = MI.getDebugLoc(); ->>>>>>> 27321ddcdbe2 (Clean up code.) MachineOperand &Dest0 = MI.getOperand(0); MachineOperand &Dest1 = MI.getOperand(1); MachineOperand &Src0 = MI.getOperand(2); diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index e68353e5223fb..ed41b9ece116a 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -7841,7 +7841,7 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_mul_i32 s1, s14, s1 ; GFX6-NEXT: s_add_u32 s1, s15, s1 ; GFX6-NEXT: s_addc_u32 s15, 0, s16 -; GFX6-NEXT: s_add_i32 s16, s0, s1 +; GFX6-NEXT: s_add_u32 s16, s0, s1 ; GFX6-NEXT: v_mov_b32_e32 v0, s16 ; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s12, v0 @@ -7874,7 +7874,7 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_mul_i32 s0, s14, s0 ; GFX6-NEXT: s_add_u32 s0, s1, s0 ; GFX6-NEXT: s_addc_u32 s12, 0, s12 -; GFX6-NEXT: s_add_i32 s15, s16, s0 +; GFX6-NEXT: s_add_u32 s15, s16, s0 ; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_cmp_lg_u32 s0, 0 @@ -7915,12 +7915,12 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_add_i32 s16, s4, s5 ; GFX6-NEXT: s_sub_i32 s17, s7, s16 ; GFX6-NEXT: s_mul_i32 s4, s10, s14 -; GFX6-NEXT: s_sub_i32 s6, s6, s4 +; GFX6-NEXT: s_sub_u32 s6, s6, s4 ; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX6-NEXT: s_or_b32 s18, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s18, 0 ; GFX6-NEXT: s_subb_u32 s17, s17, s11 -; GFX6-NEXT: s_sub_i32 s19, s6, s10 +; GFX6-NEXT: s_sub_u32 s19, s6, s10 ; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX6-NEXT: s_or_b32 s4, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 @@ -8004,7 +8004,7 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_mul_i32 s5, s12, s5 ; GFX9-NEXT: s_add_u32 s5, s13, s5 ; GFX9-NEXT: s_addc_u32 s13, 0, s14 -; GFX9-NEXT: s_add_i32 s14, s4, s5 +; GFX9-NEXT: s_add_u32 s14, s4, s5 ; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s12, s12, s13 @@ -8028,7 +8028,7 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_mul_i32 s4, s12, s4 ; GFX9-NEXT: s_add_u32 s4, s10, s4 ; GFX9-NEXT: s_addc_u32 s10, 0, s5 -; GFX9-NEXT: s_add_i32 s14, s14, s4 +; GFX9-NEXT: s_add_u32 s11, s14, s4 ; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s10, s12, s10 @@ -8038,17 +8038,17 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_addc_u32 s3, s3, s4 ; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] -; GFX9-NEXT: s_mul_i32 s12, s2, s10 -; GFX9-NEXT: s_mul_hi_u32 s13, s2, s14 -; GFX9-NEXT: s_mul_hi_u32 s11, s2, s10 -; GFX9-NEXT: s_add_u32 s12, s13, s12 -; GFX9-NEXT: s_addc_u32 s11, 0, s11 -; GFX9-NEXT: s_mul_hi_u32 s15, s3, s14 -; GFX9-NEXT: s_mul_i32 s14, s3, s14 -; GFX9-NEXT: s_add_u32 s12, s12, s14 -; GFX9-NEXT: s_mul_hi_u32 s13, s3, s10 -; GFX9-NEXT: s_addc_u32 s11, s11, s15 -; GFX9-NEXT: s_addc_u32 s12, s13, 0 +; GFX9-NEXT: s_mul_i32 s13, s2, s10 +; GFX9-NEXT: s_mul_hi_u32 s14, s2, s11 +; GFX9-NEXT: s_mul_hi_u32 s12, s2, s10 +; GFX9-NEXT: s_add_u32 s13, s14, s13 +; GFX9-NEXT: s_addc_u32 s12, 0, s12 +; GFX9-NEXT: s_mul_hi_u32 s15, s3, s11 +; GFX9-NEXT: s_mul_i32 s11, s3, s11 +; GFX9-NEXT: s_add_u32 s11, s13, s11 +; GFX9-NEXT: s_mul_hi_u32 s14, s3, s10 +; GFX9-NEXT: s_addc_u32 s11, s12, s15 +; GFX9-NEXT: s_addc_u32 s12, s14, 0 ; GFX9-NEXT: s_mul_i32 s10, s3, s10 ; GFX9-NEXT: s_add_u32 s14, s11, s10 ; GFX9-NEXT: s_addc_u32 s15, 0, s12 @@ -8059,11 +8059,11 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_add_i32 s16, s10, s11 ; GFX9-NEXT: s_sub_i32 s12, s3, s16 ; GFX9-NEXT: s_mul_i32 s10, s8, s14 -; GFX9-NEXT: s_sub_i32 s2, s2, s10 +; GFX9-NEXT: s_sub_u32 s2, s2, s10 ; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s17, s12, s9 -; GFX9-NEXT: s_sub_i32 s18, s2, s8 +; GFX9-NEXT: s_sub_u32 s18, s2, s8 ; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_subb_u32 s12, s17, 0 @@ -8348,7 +8348,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_mul_i32 s13, s16, s13 ; GFX6-NEXT: s_add_u32 s13, s17, s13 ; GFX6-NEXT: s_addc_u32 s17, 0, s18 -; GFX6-NEXT: s_add_i32 s18, s12, s13 +; GFX6-NEXT: s_add_u32 s18, s12, s13 ; GFX6-NEXT: v_mov_b32_e32 v0, s18 ; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s14, v0 @@ -8381,7 +8381,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_mul_i32 s12, s16, s12 ; GFX6-NEXT: s_add_u32 s12, s13, s12 ; GFX6-NEXT: s_addc_u32 s14, 0, s14 -; GFX6-NEXT: s_add_i32 s15, s18, s12 +; GFX6-NEXT: s_add_u32 s15, s18, s12 ; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX6-NEXT: s_or_b32 s12, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 @@ -8420,12 +8420,12 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_add_i32 s18, s14, s15 ; GFX6-NEXT: s_sub_i32 s19, s9, s18 ; GFX6-NEXT: s_mul_i32 s14, s6, s17 -; GFX6-NEXT: s_sub_i32 s8, s8, s14 +; GFX6-NEXT: s_sub_u32 s8, s8, s14 ; GFX6-NEXT: s_cselect_b64 s[14:15], 1, 0 ; GFX6-NEXT: s_or_b32 s20, s14, s15 ; GFX6-NEXT: s_cmp_lg_u32 s20, 0 ; GFX6-NEXT: s_subb_u32 s19, s19, s7 -; GFX6-NEXT: s_sub_i32 s21, s8, s6 +; GFX6-NEXT: s_sub_u32 s21, s8, s6 ; GFX6-NEXT: s_cselect_b64 s[14:15], 1, 0 ; GFX6-NEXT: s_or_b32 s14, s14, s15 ; GFX6-NEXT: s_cmp_lg_u32 s14, 0 @@ -8503,7 +8503,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_mul_i32 s3, s16, s3 ; GFX6-NEXT: s_add_u32 s3, s4, s3 ; GFX6-NEXT: s_addc_u32 s4, 0, s5 -; GFX6-NEXT: s_add_i32 s5, s2, s3 +; GFX6-NEXT: s_add_u32 s5, s2, s3 ; GFX6-NEXT: v_mov_b32_e32 v0, s5 ; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s12, v0 @@ -8536,7 +8536,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_mul_i32 s2, s4, s2 ; GFX6-NEXT: s_add_u32 s2, s3, s2 ; GFX6-NEXT: s_addc_u32 s12, 0, s12 -; GFX6-NEXT: s_add_i32 s13, s5, s2 +; GFX6-NEXT: s_add_u32 s13, s5, s2 ; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 ; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 @@ -8576,12 +8576,12 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_add_i32 s18, s12, s13 ; GFX6-NEXT: s_sub_i32 s19, s11, s18 ; GFX6-NEXT: s_mul_i32 s12, s8, s16 -; GFX6-NEXT: s_sub_i32 s10, s10, s12 +; GFX6-NEXT: s_sub_u32 s10, s10, s12 ; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX6-NEXT: s_or_b32 s20, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s20, 0 ; GFX6-NEXT: s_subb_u32 s19, s19, s9 -; GFX6-NEXT: s_sub_i32 s21, s10, s8 +; GFX6-NEXT: s_sub_u32 s21, s10, s8 ; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX6-NEXT: s_or_b32 s12, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 @@ -8668,7 +8668,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mul_i32 s13, s16, s13 ; GFX9-NEXT: s_add_u32 s13, s17, s13 ; GFX9-NEXT: s_addc_u32 s17, 0, s18 -; GFX9-NEXT: s_add_i32 s18, s12, s13 +; GFX9-NEXT: s_add_u32 s18, s12, s13 ; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_addc_u32 s16, s16, s17 @@ -8692,7 +8692,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mul_i32 s12, s16, s12 ; GFX9-NEXT: s_add_u32 s12, s14, s12 ; GFX9-NEXT: s_addc_u32 s14, 0, s13 -; GFX9-NEXT: s_add_i32 s18, s18, s12 +; GFX9-NEXT: s_add_u32 s15, s18, s12 ; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_addc_u32 s14, s16, s14 @@ -8701,17 +8701,17 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mov_b32 s13, s12 ; GFX9-NEXT: s_addc_u32 s9, s9, s12 ; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[12:13] -; GFX9-NEXT: s_mul_i32 s16, s8, s14 -; GFX9-NEXT: s_mul_hi_u32 s17, s8, s18 -; GFX9-NEXT: s_mul_hi_u32 s15, s8, s14 -; GFX9-NEXT: s_add_u32 s16, s17, s16 -; GFX9-NEXT: s_addc_u32 s15, 0, s15 -; GFX9-NEXT: s_mul_hi_u32 s19, s9, s18 -; GFX9-NEXT: s_mul_i32 s18, s9, s18 -; GFX9-NEXT: s_add_u32 s16, s16, s18 -; GFX9-NEXT: s_mul_hi_u32 s17, s9, s14 -; GFX9-NEXT: s_addc_u32 s15, s15, s19 -; GFX9-NEXT: s_addc_u32 s16, s17, 0 +; GFX9-NEXT: s_mul_i32 s17, s8, s14 +; GFX9-NEXT: s_mul_hi_u32 s18, s8, s15 +; GFX9-NEXT: s_mul_hi_u32 s16, s8, s14 +; GFX9-NEXT: s_add_u32 s17, s18, s17 +; GFX9-NEXT: s_addc_u32 s16, 0, s16 +; GFX9-NEXT: s_mul_hi_u32 s19, s9, s15 +; GFX9-NEXT: s_mul_i32 s15, s9, s15 +; GFX9-NEXT: s_add_u32 s15, s17, s15 +; GFX9-NEXT: s_mul_hi_u32 s18, s9, s14 +; GFX9-NEXT: s_addc_u32 s15, s16, s19 +; GFX9-NEXT: s_addc_u32 s16, s18, 0 ; GFX9-NEXT: s_mul_i32 s14, s9, s14 ; GFX9-NEXT: s_add_u32 s18, s15, s14 ; GFX9-NEXT: s_addc_u32 s19, 0, s16 @@ -8722,11 +8722,11 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_i32 s20, s14, s15 ; GFX9-NEXT: s_sub_i32 s16, s9, s20 ; GFX9-NEXT: s_mul_i32 s14, s6, s18 -; GFX9-NEXT: s_sub_i32 s8, s8, s14 +; GFX9-NEXT: s_sub_u32 s8, s8, s14 ; GFX9-NEXT: s_cselect_b64 s[14:15], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GFX9-NEXT: s_subb_u32 s21, s16, s7 -; GFX9-NEXT: s_sub_i32 s22, s8, s6 +; GFX9-NEXT: s_sub_u32 s22, s8, s6 ; GFX9-NEXT: s_cselect_b64 s[16:17], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GFX9-NEXT: s_subb_u32 s16, s21, 0 @@ -8799,7 +8799,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mul_i32 s12, s13, s12 ; GFX9-NEXT: s_add_u32 s5, s5, s12 ; GFX9-NEXT: s_addc_u32 s12, 0, s16 -; GFX9-NEXT: s_add_i32 s16, s4, s5 +; GFX9-NEXT: s_add_u32 s16, s4, s5 ; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s12, s13, s12 @@ -8823,7 +8823,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mul_i32 s4, s12, s4 ; GFX9-NEXT: s_add_u32 s4, s8, s4 ; GFX9-NEXT: s_addc_u32 s8, 0, s5 -; GFX9-NEXT: s_add_i32 s16, s16, s4 +; GFX9-NEXT: s_add_u32 s13, s16, s4 ; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s12, s12, s8 @@ -8833,16 +8833,16 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_addc_u32 s9, s11, s4 ; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[4:5] ; GFX9-NEXT: s_mul_i32 s11, s8, s12 -; GFX9-NEXT: s_mul_hi_u32 s13, s8, s16 +; GFX9-NEXT: s_mul_hi_u32 s16, s8, s13 ; GFX9-NEXT: s_mul_hi_u32 s10, s8, s12 -; GFX9-NEXT: s_add_u32 s11, s13, s11 +; GFX9-NEXT: s_add_u32 s11, s16, s11 ; GFX9-NEXT: s_addc_u32 s10, 0, s10 -; GFX9-NEXT: s_mul_hi_u32 s17, s9, s16 -; GFX9-NEXT: s_mul_i32 s16, s9, s16 -; GFX9-NEXT: s_add_u32 s11, s11, s16 -; GFX9-NEXT: s_mul_hi_u32 s13, s9, s12 +; GFX9-NEXT: s_mul_hi_u32 s17, s9, s13 +; GFX9-NEXT: s_mul_i32 s13, s9, s13 +; GFX9-NEXT: s_add_u32 s11, s11, s13 +; GFX9-NEXT: s_mul_hi_u32 s16, s9, s12 ; GFX9-NEXT: s_addc_u32 s10, s10, s17 -; GFX9-NEXT: s_addc_u32 s11, s13, 0 +; GFX9-NEXT: s_addc_u32 s11, s16, 0 ; GFX9-NEXT: s_mul_i32 s12, s9, s12 ; GFX9-NEXT: s_add_u32 s16, s10, s12 ; GFX9-NEXT: s_addc_u32 s17, 0, s11 @@ -8853,11 +8853,11 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_i32 s18, s10, s11 ; GFX9-NEXT: s_sub_i32 s12, s9, s18 ; GFX9-NEXT: s_mul_i32 s10, s6, s16 -; GFX9-NEXT: s_sub_i32 s8, s8, s10 +; GFX9-NEXT: s_sub_u32 s8, s8, s10 ; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s19, s12, s7 -; GFX9-NEXT: s_sub_i32 s20, s8, s6 +; GFX9-NEXT: s_sub_u32 s20, s8, s6 ; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_subb_u32 s12, s19, 0 @@ -9109,7 +9109,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_mul_i32 s1, s12, s1 ; GFX6-NEXT: s_add_u32 s1, s13, s1 ; GFX6-NEXT: s_addc_u32 s13, 0, s14 -; GFX6-NEXT: s_add_i32 s14, s0, s1 +; GFX6-NEXT: s_add_u32 s14, s0, s1 ; GFX6-NEXT: v_mov_b32_e32 v0, s14 ; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s10, v0 @@ -9142,7 +9142,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_mul_i32 s0, s12, s0 ; GFX6-NEXT: s_add_u32 s0, s1, s0 ; GFX6-NEXT: s_addc_u32 s10, 0, s10 -; GFX6-NEXT: s_add_i32 s13, s14, s0 +; GFX6-NEXT: s_add_u32 s13, s14, s0 ; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_cmp_lg_u32 s0, 0 @@ -9183,12 +9183,12 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_add_i32 s13, s4, s5 ; GFX6-NEXT: s_sub_i32 s14, s7, s13 ; GFX6-NEXT: s_mul_i32 s4, s8, s12 -; GFX6-NEXT: s_sub_i32 s6, s6, s4 +; GFX6-NEXT: s_sub_u32 s6, s6, s4 ; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX6-NEXT: s_or_b32 s12, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_subb_u32 s14, s14, s9 -; GFX6-NEXT: s_sub_i32 s15, s6, s8 +; GFX6-NEXT: s_sub_u32 s15, s6, s8 ; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX6-NEXT: s_or_b32 s4, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 @@ -9201,7 +9201,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_cselect_b32 s17, s17, s5 ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 ; GFX6-NEXT: s_subb_u32 s14, s14, s9 -; GFX6-NEXT: s_sub_i32 s18, s15, s8 +; GFX6-NEXT: s_sub_u32 s18, s15, s8 ; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX6-NEXT: s_or_b32 s4, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 @@ -9274,7 +9274,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_mul_i32 s5, s10, s5 ; GFX9-NEXT: s_add_u32 s5, s11, s5 ; GFX9-NEXT: s_addc_u32 s11, 0, s12 -; GFX9-NEXT: s_add_i32 s12, s4, s5 +; GFX9-NEXT: s_add_u32 s12, s4, s5 ; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s10, s10, s11 @@ -9298,7 +9298,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_mul_i32 s4, s10, s4 ; GFX9-NEXT: s_add_u32 s4, s8, s4 ; GFX9-NEXT: s_addc_u32 s8, 0, s5 -; GFX9-NEXT: s_add_i32 s12, s12, s4 +; GFX9-NEXT: s_add_u32 s9, s12, s4 ; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s8, s10, s8 @@ -9308,17 +9308,17 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_addc_u32 s3, s3, s4 ; GFX9-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] -; GFX9-NEXT: s_mul_i32 s10, s2, s8 -; GFX9-NEXT: s_mul_hi_u32 s11, s2, s12 -; GFX9-NEXT: s_mul_hi_u32 s9, s2, s8 -; GFX9-NEXT: s_add_u32 s10, s11, s10 -; GFX9-NEXT: s_addc_u32 s9, 0, s9 -; GFX9-NEXT: s_mul_hi_u32 s13, s3, s12 -; GFX9-NEXT: s_mul_i32 s12, s3, s12 -; GFX9-NEXT: s_add_u32 s10, s10, s12 -; GFX9-NEXT: s_mul_hi_u32 s11, s3, s8 -; GFX9-NEXT: s_addc_u32 s9, s9, s13 -; GFX9-NEXT: s_addc_u32 s10, s11, 0 +; GFX9-NEXT: s_mul_i32 s11, s2, s8 +; GFX9-NEXT: s_mul_hi_u32 s12, s2, s9 +; GFX9-NEXT: s_mul_hi_u32 s10, s2, s8 +; GFX9-NEXT: s_add_u32 s11, s12, s11 +; GFX9-NEXT: s_addc_u32 s10, 0, s10 +; GFX9-NEXT: s_mul_hi_u32 s13, s3, s9 +; GFX9-NEXT: s_mul_i32 s9, s3, s9 +; GFX9-NEXT: s_add_u32 s9, s11, s9 +; GFX9-NEXT: s_mul_hi_u32 s12, s3, s8 +; GFX9-NEXT: s_addc_u32 s9, s10, s13 +; GFX9-NEXT: s_addc_u32 s10, s12, 0 ; GFX9-NEXT: s_mul_i32 s8, s3, s8 ; GFX9-NEXT: s_add_u32 s8, s9, s8 ; GFX9-NEXT: s_addc_u32 s9, 0, s10 @@ -9329,11 +9329,11 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_add_i32 s12, s9, s10 ; GFX9-NEXT: s_sub_i32 s10, s3, s12 ; GFX9-NEXT: s_mul_i32 s8, s6, s8 -; GFX9-NEXT: s_sub_i32 s2, s2, s8 +; GFX9-NEXT: s_sub_u32 s2, s2, s8 ; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_subb_u32 s13, s10, s7 -; GFX9-NEXT: s_sub_i32 s14, s2, s6 +; GFX9-NEXT: s_sub_u32 s14, s2, s6 ; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s15, s13, 0 @@ -9345,7 +9345,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_cselect_b32 s16, s17, s16 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s13, s13, s7 -; GFX9-NEXT: s_sub_i32 s17, s14, s6 +; GFX9-NEXT: s_sub_u32 s17, s14, s6 ; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s10, s13, 0 @@ -9510,7 +9510,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_mul_i32 s7, s14, s7 ; GFX6-NEXT: s_add_u32 s7, s15, s7 ; GFX6-NEXT: s_addc_u32 s15, 0, s16 -; GFX6-NEXT: s_add_i32 s16, s6, s7 +; GFX6-NEXT: s_add_u32 s16, s6, s7 ; GFX6-NEXT: v_mov_b32_e32 v0, s16 ; GFX6-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s12, v0 @@ -9543,7 +9543,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_mul_i32 s6, s14, s6 ; GFX6-NEXT: s_add_u32 s6, s7, s6 ; GFX6-NEXT: s_addc_u32 s12, 0, s12 -; GFX6-NEXT: s_add_i32 s13, s16, s6 +; GFX6-NEXT: s_add_u32 s13, s16, s6 ; GFX6-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GFX6-NEXT: s_or_b32 s6, s6, s7 ; GFX6-NEXT: s_cmp_lg_u32 s6, 0 @@ -9582,12 +9582,12 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_add_i32 s14, s13, s14 ; GFX6-NEXT: s_sub_i32 s15, s9, s14 ; GFX6-NEXT: s_mul_i32 s12, s2, s12 -; GFX6-NEXT: s_sub_i32 s8, s8, s12 +; GFX6-NEXT: s_sub_u32 s8, s8, s12 ; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX6-NEXT: s_or_b32 s16, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_subb_u32 s15, s15, s3 -; GFX6-NEXT: s_sub_i32 s17, s8, s2 +; GFX6-NEXT: s_sub_u32 s17, s8, s2 ; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX6-NEXT: s_or_b32 s12, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 @@ -9600,7 +9600,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_cselect_b32 s19, s19, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_subb_u32 s15, s15, s3 -; GFX6-NEXT: s_sub_i32 s20, s17, s2 +; GFX6-NEXT: s_sub_u32 s20, s17, s2 ; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX6-NEXT: s_or_b32 s12, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 @@ -9667,7 +9667,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_mul_i32 s3, s14, s3 ; GFX6-NEXT: s_add_u32 s3, s4, s3 ; GFX6-NEXT: s_addc_u32 s4, 0, s5 -; GFX6-NEXT: s_add_i32 s5, s2, s3 +; GFX6-NEXT: s_add_u32 s5, s2, s3 ; GFX6-NEXT: v_mov_b32_e32 v0, s5 ; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0 @@ -9700,7 +9700,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_mul_i32 s2, s4, s2 ; GFX6-NEXT: s_add_u32 s2, s3, s2 ; GFX6-NEXT: s_addc_u32 s8, 0, s8 -; GFX6-NEXT: s_add_i32 s14, s5, s2 +; GFX6-NEXT: s_add_u32 s14, s5, s2 ; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 ; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 @@ -9740,12 +9740,12 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_add_i32 s14, s10, s14 ; GFX6-NEXT: s_sub_i32 s15, s9, s14 ; GFX6-NEXT: s_mul_i32 s10, s6, s11 -; GFX6-NEXT: s_sub_i32 s8, s8, s10 +; GFX6-NEXT: s_sub_u32 s8, s8, s10 ; GFX6-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX6-NEXT: s_or_b32 s16, s10, s11 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_subb_u32 s15, s15, s7 -; GFX6-NEXT: s_sub_i32 s17, s8, s6 +; GFX6-NEXT: s_sub_u32 s17, s8, s6 ; GFX6-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX6-NEXT: s_or_b32 s10, s10, s11 ; GFX6-NEXT: s_cmp_lg_u32 s10, 0 @@ -9758,7 +9758,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_cselect_b32 s19, s19, s11 ; GFX6-NEXT: s_cmp_lg_u32 s10, 0 ; GFX6-NEXT: s_subb_u32 s15, s15, s7 -; GFX6-NEXT: s_sub_i32 s20, s17, s6 +; GFX6-NEXT: s_sub_u32 s20, s17, s6 ; GFX6-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX6-NEXT: s_or_b32 s10, s10, s11 ; GFX6-NEXT: s_cmp_lg_u32 s10, 0 @@ -9834,7 +9834,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mul_i32 s7, s14, s7 ; GFX9-NEXT: s_add_u32 s7, s15, s7 ; GFX9-NEXT: s_addc_u32 s15, 0, s16 -; GFX9-NEXT: s_add_i32 s16, s6, s7 +; GFX9-NEXT: s_add_u32 s16, s6, s7 ; GFX9-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX9-NEXT: s_addc_u32 s14, s14, s15 @@ -9858,7 +9858,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mul_i32 s6, s14, s6 ; GFX9-NEXT: s_add_u32 s6, s12, s6 ; GFX9-NEXT: s_addc_u32 s12, 0, s7 -; GFX9-NEXT: s_add_i32 s16, s16, s6 +; GFX9-NEXT: s_add_u32 s13, s16, s6 ; GFX9-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX9-NEXT: s_addc_u32 s12, s14, s12 @@ -9867,17 +9867,17 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mov_b32 s7, s6 ; GFX9-NEXT: s_addc_u32 s9, s9, s6 ; GFX9-NEXT: s_xor_b64 s[8:9], s[8:9], s[6:7] -; GFX9-NEXT: s_mul_i32 s14, s8, s12 -; GFX9-NEXT: s_mul_hi_u32 s15, s8, s16 -; GFX9-NEXT: s_mul_hi_u32 s13, s8, s12 -; GFX9-NEXT: s_add_u32 s14, s15, s14 -; GFX9-NEXT: s_addc_u32 s13, 0, s13 -; GFX9-NEXT: s_mul_hi_u32 s17, s9, s16 -; GFX9-NEXT: s_mul_i32 s16, s9, s16 -; GFX9-NEXT: s_add_u32 s14, s14, s16 -; GFX9-NEXT: s_mul_hi_u32 s15, s9, s12 -; GFX9-NEXT: s_addc_u32 s13, s13, s17 -; GFX9-NEXT: s_addc_u32 s14, s15, 0 +; GFX9-NEXT: s_mul_i32 s15, s8, s12 +; GFX9-NEXT: s_mul_hi_u32 s16, s8, s13 +; GFX9-NEXT: s_mul_hi_u32 s14, s8, s12 +; GFX9-NEXT: s_add_u32 s15, s16, s15 +; GFX9-NEXT: s_addc_u32 s14, 0, s14 +; GFX9-NEXT: s_mul_hi_u32 s17, s9, s13 +; GFX9-NEXT: s_mul_i32 s13, s9, s13 +; GFX9-NEXT: s_add_u32 s13, s15, s13 +; GFX9-NEXT: s_mul_hi_u32 s16, s9, s12 +; GFX9-NEXT: s_addc_u32 s13, s14, s17 +; GFX9-NEXT: s_addc_u32 s14, s16, 0 ; GFX9-NEXT: s_mul_i32 s12, s9, s12 ; GFX9-NEXT: s_add_u32 s12, s13, s12 ; GFX9-NEXT: s_addc_u32 s13, 0, s14 @@ -9888,11 +9888,11 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_i32 s16, s13, s14 ; GFX9-NEXT: s_sub_i32 s14, s9, s16 ; GFX9-NEXT: s_mul_i32 s12, s2, s12 -; GFX9-NEXT: s_sub_i32 s8, s8, s12 +; GFX9-NEXT: s_sub_u32 s8, s8, s12 ; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_subb_u32 s17, s14, s3 -; GFX9-NEXT: s_sub_i32 s18, s8, s2 +; GFX9-NEXT: s_sub_u32 s18, s8, s2 ; GFX9-NEXT: s_cselect_b64 s[14:15], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GFX9-NEXT: s_subb_u32 s19, s17, 0 @@ -9904,7 +9904,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_cselect_b32 s20, s21, s20 ; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GFX9-NEXT: s_subb_u32 s17, s17, s3 -; GFX9-NEXT: s_sub_i32 s21, s18, s2 +; GFX9-NEXT: s_sub_u32 s21, s18, s2 ; GFX9-NEXT: s_cselect_b64 s[14:15], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GFX9-NEXT: s_subb_u32 s14, s17, 0 @@ -9966,7 +9966,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mul_i32 s8, s9, s8 ; GFX9-NEXT: s_add_u32 s5, s5, s8 ; GFX9-NEXT: s_addc_u32 s8, 0, s14 -; GFX9-NEXT: s_add_i32 s14, s4, s5 +; GFX9-NEXT: s_add_u32 s14, s4, s5 ; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s8, s9, s8 @@ -9990,7 +9990,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mul_i32 s4, s8, s4 ; GFX9-NEXT: s_add_u32 s4, s6, s4 ; GFX9-NEXT: s_addc_u32 s6, 0, s5 -; GFX9-NEXT: s_add_i32 s14, s14, s4 +; GFX9-NEXT: s_add_u32 s9, s14, s4 ; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s8, s8, s6 @@ -9999,17 +9999,17 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_mov_b32 s5, s4 ; GFX9-NEXT: s_addc_u32 s7, s11, s4 ; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], s[4:5] -; GFX9-NEXT: s_mul_i32 s10, s6, s8 -; GFX9-NEXT: s_mul_hi_u32 s11, s6, s14 -; GFX9-NEXT: s_mul_hi_u32 s9, s6, s8 -; GFX9-NEXT: s_add_u32 s10, s11, s10 -; GFX9-NEXT: s_addc_u32 s9, 0, s9 -; GFX9-NEXT: s_mul_hi_u32 s15, s7, s14 -; GFX9-NEXT: s_mul_i32 s14, s7, s14 -; GFX9-NEXT: s_add_u32 s10, s10, s14 -; GFX9-NEXT: s_mul_hi_u32 s11, s7, s8 -; GFX9-NEXT: s_addc_u32 s9, s9, s15 -; GFX9-NEXT: s_addc_u32 s10, s11, 0 +; GFX9-NEXT: s_mul_i32 s11, s6, s8 +; GFX9-NEXT: s_mul_hi_u32 s14, s6, s9 +; GFX9-NEXT: s_mul_hi_u32 s10, s6, s8 +; GFX9-NEXT: s_add_u32 s11, s14, s11 +; GFX9-NEXT: s_addc_u32 s10, 0, s10 +; GFX9-NEXT: s_mul_hi_u32 s15, s7, s9 +; GFX9-NEXT: s_mul_i32 s9, s7, s9 +; GFX9-NEXT: s_add_u32 s9, s11, s9 +; GFX9-NEXT: s_mul_hi_u32 s14, s7, s8 +; GFX9-NEXT: s_addc_u32 s9, s10, s15 +; GFX9-NEXT: s_addc_u32 s10, s14, 0 ; GFX9-NEXT: s_mul_i32 s8, s7, s8 ; GFX9-NEXT: s_add_u32 s8, s9, s8 ; GFX9-NEXT: s_addc_u32 s9, 0, s10 @@ -10020,11 +10020,11 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_i32 s14, s9, s10 ; GFX9-NEXT: s_sub_i32 s10, s7, s14 ; GFX9-NEXT: s_mul_i32 s8, s2, s8 -; GFX9-NEXT: s_sub_i32 s6, s6, s8 +; GFX9-NEXT: s_sub_u32 s6, s6, s8 ; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_subb_u32 s15, s10, s3 -; GFX9-NEXT: s_sub_i32 s16, s6, s2 +; GFX9-NEXT: s_sub_u32 s16, s6, s2 ; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s17, s15, 0 @@ -10036,7 +10036,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_cselect_b32 s18, s19, s18 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s15, s15, s3 -; GFX9-NEXT: s_sub_i32 s19, s16, s2 +; GFX9-NEXT: s_sub_u32 s19, s16, s2 ; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s10, s15, 0 diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll index cca83bdd0b956..7a6d0ecfee120 100644 --- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll +++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll @@ -2215,11 +2215,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; VI-NEXT: s_add_i32 s14, s8, s9 ; VI-NEXT: s_sub_i32 s10, s3, s14 ; VI-NEXT: v_readfirstlane_b32 s8, v0 -; VI-NEXT: s_sub_i32 s15, s2, s8 +; VI-NEXT: s_sub_u32 s15, s2, s8 ; VI-NEXT: s_cselect_b64 s[8:9], 1, 0 ; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 ; VI-NEXT: s_subb_u32 s16, s10, s5 -; VI-NEXT: s_sub_i32 s17, s15, s4 +; VI-NEXT: s_sub_u32 s17, s15, s4 ; VI-NEXT: s_cselect_b64 s[10:11], 1, 0 ; VI-NEXT: s_cmp_lg_u64 s[10:11], 0 ; VI-NEXT: s_subb_u32 s10, s16, 0 @@ -2329,7 +2329,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX9-NEXT: s_mul_i32 s9, s12, s9 ; GFX9-NEXT: s_add_u32 s9, s13, s9 ; GFX9-NEXT: s_addc_u32 s13, 0, s14 -; GFX9-NEXT: s_add_i32 s14, s8, s9 +; GFX9-NEXT: s_add_u32 s14, s8, s9 ; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_addc_u32 s12, s12, s13 @@ -2353,21 +2353,21 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX9-NEXT: s_mul_i32 s8, s12, s8 ; GFX9-NEXT: s_add_u32 s8, s10, s8 ; GFX9-NEXT: s_addc_u32 s10, 0, s9 -; GFX9-NEXT: s_add_i32 s14, s14, s8 +; GFX9-NEXT: s_add_u32 s11, s14, s8 ; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_addc_u32 s8, s12, s10 ; GFX9-NEXT: s_mul_i32 s10, s2, s8 -; GFX9-NEXT: s_mul_hi_u32 s11, s2, s14 +; GFX9-NEXT: s_mul_hi_u32 s12, s2, s11 ; GFX9-NEXT: s_mul_hi_u32 s9, s2, s8 -; GFX9-NEXT: s_add_u32 s10, s11, s10 +; GFX9-NEXT: s_add_u32 s10, s12, s10 ; GFX9-NEXT: s_addc_u32 s9, 0, s9 -; GFX9-NEXT: s_mul_i32 s13, s3, s14 -; GFX9-NEXT: s_mul_hi_u32 s12, s3, s14 -; GFX9-NEXT: s_add_u32 s10, s10, s13 -; GFX9-NEXT: s_mul_hi_u32 s11, s3, s8 -; GFX9-NEXT: s_addc_u32 s9, s9, s12 -; GFX9-NEXT: s_addc_u32 s10, s11, 0 +; GFX9-NEXT: s_mul_hi_u32 s13, s3, s11 +; GFX9-NEXT: s_mul_i32 s11, s3, s11 +; GFX9-NEXT: s_add_u32 s10, s10, s11 +; GFX9-NEXT: s_mul_hi_u32 s12, s3, s8 +; GFX9-NEXT: s_addc_u32 s9, s9, s13 +; GFX9-NEXT: s_addc_u32 s10, s12, 0 ; GFX9-NEXT: s_mul_i32 s8, s3, s8 ; GFX9-NEXT: s_add_u32 s12, s9, s8 ; GFX9-NEXT: s_addc_u32 s13, 0, s10 @@ -2378,11 +2378,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX9-NEXT: s_add_i32 s14, s8, s9 ; GFX9-NEXT: s_sub_i32 s10, s3, s14 ; GFX9-NEXT: s_mul_i32 s8, s6, s12 -; GFX9-NEXT: s_sub_i32 s15, s2, s8 +; GFX9-NEXT: s_sub_u32 s15, s2, s8 ; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_subb_u32 s16, s10, s7 -; GFX9-NEXT: s_sub_i32 s17, s15, s6 +; GFX9-NEXT: s_sub_u32 s17, s15, s6 ; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s10, s16, 0 @@ -2488,7 +2488,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1010-NEXT: s_addc_u32 s13, s17, 0 ; GFX1010-NEXT: s_add_u32 s11, s12, s11 ; GFX1010-NEXT: s_addc_u32 s12, 0, s13 -; GFX1010-NEXT: s_add_i32 s8, s8, s11 +; GFX1010-NEXT: s_add_u32 s8, s8, s11 ; GFX1010-NEXT: s_cselect_b32 s11, 1, 0 ; GFX1010-NEXT: s_mul_hi_u32 s13, s9, s8 ; GFX1010-NEXT: s_cmp_lg_u32 s11, 0 @@ -2512,7 +2512,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1010-NEXT: s_addc_u32 s11, s11, 0 ; GFX1010-NEXT: s_add_u32 s9, s10, s9 ; GFX1010-NEXT: s_addc_u32 s10, 0, s11 -; GFX1010-NEXT: s_add_i32 s8, s8, s9 +; GFX1010-NEXT: s_add_u32 s8, s8, s9 ; GFX1010-NEXT: s_cselect_b32 s9, 1, 0 ; GFX1010-NEXT: s_mul_hi_u32 s11, s2, s8 ; GFX1010-NEXT: s_cmp_lg_u32 s9, 0 @@ -2537,11 +2537,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1010-NEXT: s_mul_i32 s10, s6, s5 ; GFX1010-NEXT: s_add_i32 s9, s9, s11 ; GFX1010-NEXT: s_sub_i32 s11, s3, s9 -; GFX1010-NEXT: s_sub_i32 s10, s2, s10 +; GFX1010-NEXT: s_sub_u32 s10, s2, s10 ; GFX1010-NEXT: s_cselect_b32 s12, 1, 0 ; GFX1010-NEXT: s_cmp_lg_u32 s12, 0 ; GFX1010-NEXT: s_subb_u32 s11, s11, s7 -; GFX1010-NEXT: s_sub_i32 s13, s10, s6 +; GFX1010-NEXT: s_sub_u32 s13, s10, s6 ; GFX1010-NEXT: s_cselect_b32 s14, 1, 0 ; GFX1010-NEXT: s_cmp_lg_u32 s14, 0 ; GFX1010-NEXT: s_subb_u32 s11, s11, 0 @@ -2648,7 +2648,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W32-NEXT: s_addc_u32 s13, s17, 0 ; GFX1030W32-NEXT: s_add_u32 s11, s12, s11 ; GFX1030W32-NEXT: s_addc_u32 s12, 0, s13 -; GFX1030W32-NEXT: s_add_i32 s8, s8, s11 +; GFX1030W32-NEXT: s_add_u32 s8, s8, s11 ; GFX1030W32-NEXT: s_cselect_b32 s11, 1, 0 ; GFX1030W32-NEXT: s_mul_hi_u32 s13, s9, s8 ; GFX1030W32-NEXT: s_cmp_lg_u32 s11, 0 @@ -2672,7 +2672,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W32-NEXT: s_addc_u32 s11, s11, 0 ; GFX1030W32-NEXT: s_add_u32 s9, s10, s9 ; GFX1030W32-NEXT: s_addc_u32 s10, 0, s11 -; GFX1030W32-NEXT: s_add_i32 s8, s8, s9 +; GFX1030W32-NEXT: s_add_u32 s8, s8, s9 ; GFX1030W32-NEXT: s_cselect_b32 s9, 1, 0 ; GFX1030W32-NEXT: s_mul_hi_u32 s11, s2, s8 ; GFX1030W32-NEXT: s_cmp_lg_u32 s9, 0 @@ -2697,11 +2697,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W32-NEXT: s_mul_i32 s10, s4, s7 ; GFX1030W32-NEXT: s_add_i32 s9, s9, s11 ; GFX1030W32-NEXT: s_sub_i32 s11, s3, s9 -; GFX1030W32-NEXT: s_sub_i32 s10, s2, s10 +; GFX1030W32-NEXT: s_sub_u32 s10, s2, s10 ; GFX1030W32-NEXT: s_cselect_b32 s12, 1, 0 ; GFX1030W32-NEXT: s_cmp_lg_u32 s12, 0 ; GFX1030W32-NEXT: s_subb_u32 s11, s11, s5 -; GFX1030W32-NEXT: s_sub_i32 s13, s10, s4 +; GFX1030W32-NEXT: s_sub_u32 s13, s10, s4 ; GFX1030W32-NEXT: s_cselect_b32 s14, 1, 0 ; GFX1030W32-NEXT: s_cmp_lg_u32 s14, 0 ; GFX1030W32-NEXT: s_subb_u32 s11, s11, 0 @@ -2808,7 +2808,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W64-NEXT: s_addc_u32 s12, s16, 0 ; GFX1030W64-NEXT: s_add_u32 s7, s11, s7 ; GFX1030W64-NEXT: s_addc_u32 s11, 0, s12 -; GFX1030W64-NEXT: s_add_i32 s12, s6, s7 +; GFX1030W64-NEXT: s_add_u32 s12, s6, s7 ; GFX1030W64-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GFX1030W64-NEXT: s_mul_hi_u32 s13, s9, s12 ; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 @@ -2832,16 +2832,16 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W64-NEXT: s_addc_u32 s7, s10, 0 ; GFX1030W64-NEXT: s_add_u32 s6, s6, s9 ; GFX1030W64-NEXT: s_addc_u32 s9, 0, s7 -; GFX1030W64-NEXT: s_add_i32 s12, s12, s6 +; GFX1030W64-NEXT: s_add_u32 s10, s12, s6 ; GFX1030W64-NEXT: s_cselect_b64 s[6:7], 1, 0 -; GFX1030W64-NEXT: s_mul_hi_u32 s10, s2, s12 +; GFX1030W64-NEXT: s_mul_hi_u32 s11, s2, s10 ; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 -; GFX1030W64-NEXT: s_mul_hi_u32 s6, s3, s12 +; GFX1030W64-NEXT: s_mul_hi_u32 s6, s3, s10 ; GFX1030W64-NEXT: s_addc_u32 s7, s8, s9 -; GFX1030W64-NEXT: s_mul_i32 s8, s3, s12 -; GFX1030W64-NEXT: s_mul_i32 s11, s2, s7 +; GFX1030W64-NEXT: s_mul_i32 s8, s3, s10 +; GFX1030W64-NEXT: s_mul_i32 s10, s2, s7 ; GFX1030W64-NEXT: s_mul_hi_u32 s9, s2, s7 -; GFX1030W64-NEXT: s_add_u32 s10, s10, s11 +; GFX1030W64-NEXT: s_add_u32 s10, s11, s10 ; GFX1030W64-NEXT: s_addc_u32 s9, 0, s9 ; GFX1030W64-NEXT: s_mul_hi_u32 s12, s3, s7 ; GFX1030W64-NEXT: s_add_u32 s8, s10, s8 @@ -2857,11 +2857,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W64-NEXT: s_add_i32 s12, s6, s8 ; GFX1030W64-NEXT: s_mul_i32 s6, s4, s10 ; GFX1030W64-NEXT: s_sub_i32 s8, s3, s12 -; GFX1030W64-NEXT: s_sub_i32 s13, s2, s6 +; GFX1030W64-NEXT: s_sub_u32 s13, s2, s6 ; GFX1030W64-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX1030W64-NEXT: s_subb_u32 s14, s8, s5 -; GFX1030W64-NEXT: s_sub_i32 s15, s13, s4 +; GFX1030W64-NEXT: s_sub_u32 s15, s13, s4 ; GFX1030W64-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GFX1030W64-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX1030W64-NEXT: s_subb_u32 s8, s14, 0 @@ -2973,7 +2973,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX11-NEXT: s_addc_u32 s13, s17, 0 ; GFX11-NEXT: s_add_u32 s11, s12, s11 ; GFX11-NEXT: s_addc_u32 s12, 0, s13 -; GFX11-NEXT: s_add_i32 s8, s8, s11 +; GFX11-NEXT: s_add_u32 s8, s8, s11 ; GFX11-NEXT: s_cselect_b32 s11, 1, 0 ; GFX11-NEXT: s_mul_hi_u32 s13, s9, s8 ; GFX11-NEXT: s_cmp_lg_u32 s11, 0 @@ -2997,7 +2997,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX11-NEXT: s_addc_u32 s11, s11, 0 ; GFX11-NEXT: s_add_u32 s9, s10, s9 ; GFX11-NEXT: s_addc_u32 s10, 0, s11 -; GFX11-NEXT: s_add_i32 s8, s8, s9 +; GFX11-NEXT: s_add_u32 s8, s8, s9 ; GFX11-NEXT: s_cselect_b32 s9, 1, 0 ; GFX11-NEXT: s_mul_hi_u32 s11, s2, s8 ; GFX11-NEXT: s_cmp_lg_u32 s9, 0 @@ -3023,11 +3023,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX11-NEXT: s_add_i32 s9, s9, s11 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_sub_i32 s11, s3, s9 -; GFX11-NEXT: s_sub_i32 s10, s2, s10 +; GFX11-NEXT: s_sub_u32 s10, s2, s10 ; GFX11-NEXT: s_cselect_b32 s12, 1, 0 ; GFX11-NEXT: s_cmp_lg_u32 s12, 0 ; GFX11-NEXT: s_subb_u32 s11, s11, s5 -; GFX11-NEXT: s_sub_i32 s13, s10, s4 +; GFX11-NEXT: s_sub_u32 s13, s10, s4 ; GFX11-NEXT: s_cselect_b32 s14, 1, 0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_cmp_lg_u32 s14, 0 @@ -3105,7 +3105,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1250-NEXT: s_wait_kmcnt 0x0 ; GFX1250-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5] ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX1250-NEXT: s_and_b64 s[6:7], s[6:7], lit64(0xffffffff00000000) +; GFX1250-NEXT: s_and_b64 s[6:7], s[6:7], 0xffffffff00000000 ; GFX1250-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX1250-NEXT: s_cbranch_scc0 .LBB16_4 ; GFX1250-NEXT: ; %bb.1: @@ -3140,7 +3140,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1250-NEXT: s_add_co_ci_u32 s13, s18, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_add_nc_u64 s[12:13], s[6:7], s[12:13] -; GFX1250-NEXT: s_add_co_i32 s8, s8, s12 +; GFX1250-NEXT: s_add_co_u32 s8, s8, s12 ; GFX1250-NEXT: s_cselect_b32 s6, 1, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_cmp_lg_u32 s6, 0 @@ -3160,7 +3160,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1250-NEXT: s_add_co_ci_u32 s11, s16, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_add_nc_u64 s[10:11], s[6:7], s[10:11] -; GFX1250-NEXT: s_add_co_i32 s8, s8, s10 +; GFX1250-NEXT: s_add_co_u32 s8, s8, s10 ; GFX1250-NEXT: s_cselect_b32 s10, 1, 0 ; GFX1250-NEXT: s_mul_hi_u32 s6, s2, s8 ; GFX1250-NEXT: s_cmp_lg_u32 s10, 0 @@ -3177,17 +3177,17 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1250-NEXT: s_add_co_ci_u32 s11, s13, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_add_nc_u64 s[8:9], s[6:7], s[10:11] -; GFX1250-NEXT: s_and_b64 s[10:11], s[8:9], lit64(0xffffffff00000000) +; GFX1250-NEXT: s_and_b64 s[10:11], s[8:9], 0xffffffff00000000 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_or_b32 s10, s10, s8 ; GFX1250-NEXT: s_mul_u64 s[8:9], s[4:5], s[10:11] ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-NEXT: s_sub_co_i32 s6, s2, s8 +; GFX1250-NEXT: s_sub_co_u32 s6, s2, s8 ; GFX1250-NEXT: s_cselect_b32 s8, 1, 0 ; GFX1250-NEXT: s_sub_co_i32 s12, s3, s9 ; GFX1250-NEXT: s_cmp_lg_u32 s8, 0 ; GFX1250-NEXT: s_sub_co_ci_u32 s12, s12, s5 -; GFX1250-NEXT: s_sub_co_i32 s13, s6, s4 +; GFX1250-NEXT: s_sub_co_u32 s13, s6, s4 ; GFX1250-NEXT: s_cselect_b32 s14, 1, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_cmp_lg_u32 s14, 0 diff --git a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll index 4f5e4eb4eaeb4..897232d1756de 100644 --- a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll +++ b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll @@ -11,7 +11,7 @@ define i32 @s_add_co_select_user() { ; GFX7-NEXT: s_mov_b64 s[4:5], 0 ; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: s_add_i32 s7, s6, s6 +; GFX7-NEXT: s_add_u32 s7, s6, s6 ; GFX7-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX7-NEXT: s_or_b32 s4, s4, s5 ; GFX7-NEXT: s_cmp_lg_u32 s4, 0 @@ -30,7 +30,7 @@ define i32 @s_add_co_select_user() { ; GFX9-NEXT: s_mov_b64 s[4:5], 0 ; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: s_add_i32 s7, s6, s6 +; GFX9-NEXT: s_add_u32 s7, s6, s6 ; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s8, s6, 0 @@ -48,7 +48,7 @@ define i32 @s_add_co_select_user() { ; GFX10-NEXT: s_mov_b64 s[4:5], 0 ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: s_add_i32 s5, s4, s4 +; GFX10-NEXT: s_add_u32 s5, s4, s4 ; GFX10-NEXT: s_cselect_b32 s6, 1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 ; GFX10-NEXT: s_addc_u32 s6, s4, 0 @@ -66,7 +66,7 @@ define i32 @s_add_co_select_user() { ; GFX11-NEXT: s_mov_b64 s[0:1], 0 ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_add_i32 s1, s0, s0 +; GFX11-NEXT: s_add_u32 s1, s0, s0 ; GFX11-NEXT: s_cselect_b32 s2, 1, 0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_cmp_lg_u32 s2, 0 diff --git a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll index 2d380e622d028..ebcd84782a3dc 100644 --- a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll +++ b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll @@ -11,7 +11,7 @@ define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0) { ; CHECK-LABEL: s_uaddo_pseudo: ; CHECK: ; %bb.0: -; CHECK-NEXT: s_add_i32 s0, s0, 1 +; CHECK-NEXT: s_add_u32 s0, s0, 1 ; CHECK-NEXT: s_cselect_b64 s[0:1], 1, 0 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 ; CHECK-NEXT: s_addc_u32 s0, 1, 0 diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index 58b019cc2d27a..6e712fae961aa 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -54,7 +54,7 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_mul_i32 s1, s14, s1 ; GCN-NEXT: s_add_u32 s1, s15, s1 ; GCN-NEXT: s_addc_u32 s15, 0, s16 -; GCN-NEXT: s_add_i32 s16, s0, s1 +; GCN-NEXT: s_add_u32 s16, s0, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s16 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s12, v0 @@ -87,7 +87,7 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_mul_i32 s0, s14, s0 ; GCN-NEXT: s_add_u32 s0, s1, s0 ; GCN-NEXT: s_addc_u32 s12, 0, s12 -; GCN-NEXT: s_add_i32 s15, s16, s0 +; GCN-NEXT: s_add_u32 s15, s16, s0 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 @@ -128,12 +128,12 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_add_i32 s16, s4, s5 ; GCN-NEXT: s_sub_i32 s17, s7, s16 ; GCN-NEXT: s_mul_i32 s4, s10, s14 -; GCN-NEXT: s_sub_i32 s6, s6, s4 +; GCN-NEXT: s_sub_u32 s6, s6, s4 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s18, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s18, 0 ; GCN-NEXT: s_subb_u32 s17, s17, s11 -; GCN-NEXT: s_sub_i32 s19, s6, s10 +; GCN-NEXT: s_sub_u32 s19, s6, s10 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 @@ -1190,7 +1190,7 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_mul_i32 s9, s11, s9 ; GCN-NEXT: s_add_u32 s9, s12, s9 ; GCN-NEXT: s_addc_u32 s12, 0, s13 -; GCN-NEXT: s_add_i32 s13, s8, s9 +; GCN-NEXT: s_add_u32 s13, s8, s9 ; GCN-NEXT: v_mov_b32_e32 v0, s13 ; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 @@ -1223,12 +1223,12 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_mul_i32 s8, s11, s8 ; GCN-NEXT: s_add_u32 s2, s2, s8 ; GCN-NEXT: s_addc_u32 s10, 0, s9 -; GCN-NEXT: s_add_i32 s13, s13, s2 +; GCN-NEXT: s_add_u32 s2, s13, s2 ; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 -; GCN-NEXT: s_or_b32 s2, s8, s9 -; GCN-NEXT: s_cmp_lg_u32 s2, 0 +; GCN-NEXT: s_or_b32 s8, s8, s9 +; GCN-NEXT: s_cmp_lg_u32 s8, 0 ; GCN-NEXT: s_addc_u32 s8, s11, s10 -; GCN-NEXT: v_mul_hi_u32 v1, s13, 24 +; GCN-NEXT: v_mul_hi_u32 v1, s2, 24 ; GCN-NEXT: v_mul_hi_u32 v0, s8, 24 ; GCN-NEXT: s_mul_i32 s8, s8, 24 ; GCN-NEXT: s_mov_b32 s2, -1 @@ -1243,12 +1243,12 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_add_i32 s11, s9, s8 ; GCN-NEXT: s_sub_i32 s12, 0, s11 ; GCN-NEXT: s_mul_i32 s8, s6, s10 -; GCN-NEXT: s_sub_i32 s13, 24, s8 +; GCN-NEXT: s_sub_u32 s13, 24, s8 ; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GCN-NEXT: s_or_b32 s14, s8, s9 ; GCN-NEXT: s_cmp_lg_u32 s14, 0 ; GCN-NEXT: s_subb_u32 s12, s12, s7 -; GCN-NEXT: s_sub_i32 s15, s13, s6 +; GCN-NEXT: s_sub_u32 s15, s13, s6 ; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GCN-NEXT: s_or_b32 s8, s8, s9 ; GCN-NEXT: s_cmp_lg_u32 s8, 0 diff --git a/llvm/test/CodeGen/AMDGPU/srem.ll b/llvm/test/CodeGen/AMDGPU/srem.ll index fce960038444a..964af8ab47c82 100644 --- a/llvm/test/CodeGen/AMDGPU/srem.ll +++ b/llvm/test/CodeGen/AMDGPU/srem.ll @@ -1544,7 +1544,7 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GCN-NEXT: s_mul_i32 s11, s13, s11 ; GCN-NEXT: s_add_u32 s11, s14, s11 ; GCN-NEXT: s_addc_u32 s14, 0, s15 -; GCN-NEXT: s_add_i32 s15, s10, s11 +; GCN-NEXT: s_add_u32 s15, s10, s11 ; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GCN-NEXT: s_addc_u32 s13, s13, s14 @@ -1568,29 +1568,29 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GCN-NEXT: s_mul_i32 s10, s13, s10 ; GCN-NEXT: s_add_u32 s3, s3, s10 ; GCN-NEXT: s_addc_u32 s12, 0, s11 -; GCN-NEXT: s_add_i32 s15, s15, s3 +; GCN-NEXT: s_add_u32 s3, s15, s3 ; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[10:11], 0 -; GCN-NEXT: s_addc_u32 s3, s13, s12 +; GCN-NEXT: s_addc_u32 s14, s13, s12 ; GCN-NEXT: s_ashr_i32 s10, s5, 31 ; GCN-NEXT: s_add_u32 s12, s4, s10 ; GCN-NEXT: s_mov_b32 s11, s10 ; GCN-NEXT: s_addc_u32 s13, s5, s10 ; GCN-NEXT: s_xor_b64 s[12:13], s[12:13], s[10:11] -; GCN-NEXT: s_mul_i32 s14, s12, s3 -; GCN-NEXT: s_mul_hi_u32 s16, s12, s15 -; GCN-NEXT: s_mul_hi_u32 s5, s12, s3 -; GCN-NEXT: s_add_u32 s14, s16, s14 +; GCN-NEXT: s_mul_i32 s15, s12, s14 +; GCN-NEXT: s_mul_hi_u32 s16, s12, s3 +; GCN-NEXT: s_mul_hi_u32 s5, s12, s14 +; GCN-NEXT: s_add_u32 s15, s16, s15 ; GCN-NEXT: s_addc_u32 s5, 0, s5 -; GCN-NEXT: s_mul_hi_u32 s17, s13, s15 -; GCN-NEXT: s_mul_i32 s15, s13, s15 -; GCN-NEXT: s_add_u32 s14, s14, s15 -; GCN-NEXT: s_mul_hi_u32 s16, s13, s3 -; GCN-NEXT: s_addc_u32 s5, s5, s17 -; GCN-NEXT: s_addc_u32 s14, s16, 0 +; GCN-NEXT: s_mul_hi_u32 s17, s13, s3 ; GCN-NEXT: s_mul_i32 s3, s13, s3 -; GCN-NEXT: s_add_u32 s3, s5, s3 -; GCN-NEXT: s_addc_u32 s5, 0, s14 +; GCN-NEXT: s_add_u32 s3, s15, s3 +; GCN-NEXT: s_mul_hi_u32 s16, s13, s14 +; GCN-NEXT: s_addc_u32 s3, s5, s17 +; GCN-NEXT: s_addc_u32 s5, s16, 0 +; GCN-NEXT: s_mul_i32 s14, s13, s14 +; GCN-NEXT: s_add_u32 s3, s3, s14 +; GCN-NEXT: s_addc_u32 s5, 0, s5 ; GCN-NEXT: s_mul_i32 s5, s8, s5 ; GCN-NEXT: s_mul_hi_u32 s14, s8, s3 ; GCN-NEXT: s_add_i32 s5, s14, s5 @@ -1598,11 +1598,11 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GCN-NEXT: s_add_i32 s5, s5, s14 ; GCN-NEXT: s_sub_i32 s16, s13, s5 ; GCN-NEXT: s_mul_i32 s3, s8, s3 -; GCN-NEXT: s_sub_i32 s3, s12, s3 +; GCN-NEXT: s_sub_u32 s3, s12, s3 ; GCN-NEXT: s_cselect_b64 s[14:15], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GCN-NEXT: s_subb_u32 s12, s16, s9 -; GCN-NEXT: s_sub_i32 s18, s3, s8 +; GCN-NEXT: s_sub_u32 s18, s3, s8 ; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s19, s12, 0 @@ -1614,7 +1614,7 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GCN-NEXT: s_cselect_b32 s20, s21, s20 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s12, s12, s9 -; GCN-NEXT: s_sub_i32 s21, s18, s8 +; GCN-NEXT: s_sub_u32 s21, s18, s8 ; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s12, s12, 0 @@ -1929,11 +1929,11 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; TONGA-NEXT: s_add_i32 s5, s5, s3 ; TONGA-NEXT: s_sub_i32 s3, s13, s5 ; TONGA-NEXT: v_readfirstlane_b32 s14, v0 -; TONGA-NEXT: s_sub_i32 s12, s12, s14 +; TONGA-NEXT: s_sub_u32 s12, s12, s14 ; TONGA-NEXT: s_cselect_b64 s[14:15], 1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 ; TONGA-NEXT: s_subb_u32 s3, s3, s7 -; TONGA-NEXT: s_sub_i32 s18, s12, s6 +; TONGA-NEXT: s_sub_u32 s18, s12, s6 ; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s19, s3, 0 @@ -1945,7 +1945,7 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; TONGA-NEXT: s_cselect_b32 s20, s21, s20 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s3, s3, s7 -; TONGA-NEXT: s_sub_i32 s21, s18, s6 +; TONGA-NEXT: s_sub_u32 s21, s18, s6 ; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s3, s3, 0 @@ -2761,7 +2761,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s15, s17, s15 ; GCN-NEXT: s_add_u32 s15, s18, s15 ; GCN-NEXT: s_addc_u32 s18, 0, s19 -; GCN-NEXT: s_add_i32 s19, s14, s15 +; GCN-NEXT: s_add_u32 s19, s14, s15 ; GCN-NEXT: s_cselect_b64 s[14:15], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GCN-NEXT: s_addc_u32 s17, s17, s18 @@ -2785,29 +2785,29 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s14, s17, s14 ; GCN-NEXT: s_add_u32 s9, s9, s14 ; GCN-NEXT: s_addc_u32 s16, 0, s15 -; GCN-NEXT: s_add_i32 s19, s19, s9 +; GCN-NEXT: s_add_u32 s9, s19, s9 ; GCN-NEXT: s_cselect_b64 s[14:15], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 -; GCN-NEXT: s_addc_u32 s9, s17, s16 +; GCN-NEXT: s_addc_u32 s18, s17, s16 ; GCN-NEXT: s_ashr_i32 s14, s11, 31 ; GCN-NEXT: s_add_u32 s16, s10, s14 ; GCN-NEXT: s_mov_b32 s15, s14 ; GCN-NEXT: s_addc_u32 s17, s11, s14 ; GCN-NEXT: s_xor_b64 s[16:17], s[16:17], s[14:15] -; GCN-NEXT: s_mul_i32 s18, s16, s9 -; GCN-NEXT: s_mul_hi_u32 s20, s16, s19 -; GCN-NEXT: s_mul_hi_u32 s11, s16, s9 -; GCN-NEXT: s_add_u32 s18, s20, s18 +; GCN-NEXT: s_mul_i32 s19, s16, s18 +; GCN-NEXT: s_mul_hi_u32 s20, s16, s9 +; GCN-NEXT: s_mul_hi_u32 s11, s16, s18 +; GCN-NEXT: s_add_u32 s19, s20, s19 ; GCN-NEXT: s_addc_u32 s11, 0, s11 -; GCN-NEXT: s_mul_hi_u32 s21, s17, s19 -; GCN-NEXT: s_mul_i32 s19, s17, s19 -; GCN-NEXT: s_add_u32 s18, s18, s19 -; GCN-NEXT: s_mul_hi_u32 s20, s17, s9 -; GCN-NEXT: s_addc_u32 s11, s11, s21 -; GCN-NEXT: s_addc_u32 s18, s20, 0 +; GCN-NEXT: s_mul_hi_u32 s21, s17, s9 ; GCN-NEXT: s_mul_i32 s9, s17, s9 -; GCN-NEXT: s_add_u32 s9, s11, s9 -; GCN-NEXT: s_addc_u32 s11, 0, s18 +; GCN-NEXT: s_add_u32 s9, s19, s9 +; GCN-NEXT: s_mul_hi_u32 s20, s17, s18 +; GCN-NEXT: s_addc_u32 s9, s11, s21 +; GCN-NEXT: s_addc_u32 s11, s20, 0 +; GCN-NEXT: s_mul_i32 s18, s17, s18 +; GCN-NEXT: s_add_u32 s9, s9, s18 +; GCN-NEXT: s_addc_u32 s11, 0, s11 ; GCN-NEXT: s_mul_i32 s11, s6, s11 ; GCN-NEXT: s_mul_hi_u32 s18, s6, s9 ; GCN-NEXT: s_add_i32 s11, s18, s11 @@ -2815,11 +2815,11 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_i32 s11, s11, s18 ; GCN-NEXT: s_sub_i32 s20, s17, s11 ; GCN-NEXT: s_mul_i32 s9, s6, s9 -; GCN-NEXT: s_sub_i32 s9, s16, s9 +; GCN-NEXT: s_sub_u32 s9, s16, s9 ; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s16, s20, s7 -; GCN-NEXT: s_sub_i32 s22, s9, s6 +; GCN-NEXT: s_sub_u32 s22, s9, s6 ; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_subb_u32 s23, s16, 0 @@ -2831,7 +2831,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cselect_b32 s24, s25, s24 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_subb_u32 s16, s16, s7 -; GCN-NEXT: s_sub_i32 s25, s22, s6 +; GCN-NEXT: s_sub_u32 s25, s22, s6 ; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_subb_u32 s16, s16, 0 @@ -2918,7 +2918,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s13, s15, s13 ; GCN-NEXT: s_add_u32 s13, s16, s13 ; GCN-NEXT: s_addc_u32 s16, 0, s17 -; GCN-NEXT: s_add_i32 s17, s12, s13 +; GCN-NEXT: s_add_u32 s17, s12, s13 ; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GCN-NEXT: s_addc_u32 s15, s15, s16 @@ -2942,29 +2942,29 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s12, s15, s12 ; GCN-NEXT: s_add_u32 s3, s3, s12 ; GCN-NEXT: s_addc_u32 s14, 0, s13 -; GCN-NEXT: s_add_i32 s17, s17, s3 +; GCN-NEXT: s_add_u32 s3, s17, s3 ; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 -; GCN-NEXT: s_addc_u32 s3, s15, s14 +; GCN-NEXT: s_addc_u32 s16, s15, s14 ; GCN-NEXT: s_ashr_i32 s12, s5, 31 ; GCN-NEXT: s_add_u32 s14, s4, s12 ; GCN-NEXT: s_mov_b32 s13, s12 ; GCN-NEXT: s_addc_u32 s15, s5, s12 ; GCN-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13] -; GCN-NEXT: s_mul_i32 s16, s14, s3 -; GCN-NEXT: s_mul_hi_u32 s18, s14, s17 -; GCN-NEXT: s_mul_hi_u32 s5, s14, s3 -; GCN-NEXT: s_add_u32 s16, s18, s16 +; GCN-NEXT: s_mul_i32 s17, s14, s16 +; GCN-NEXT: s_mul_hi_u32 s18, s14, s3 +; GCN-NEXT: s_mul_hi_u32 s5, s14, s16 +; GCN-NEXT: s_add_u32 s17, s18, s17 ; GCN-NEXT: s_addc_u32 s5, 0, s5 -; GCN-NEXT: s_mul_hi_u32 s19, s15, s17 -; GCN-NEXT: s_mul_i32 s17, s15, s17 -; GCN-NEXT: s_add_u32 s16, s16, s17 -; GCN-NEXT: s_mul_hi_u32 s18, s15, s3 -; GCN-NEXT: s_addc_u32 s5, s5, s19 -; GCN-NEXT: s_addc_u32 s16, s18, 0 +; GCN-NEXT: s_mul_hi_u32 s19, s15, s3 ; GCN-NEXT: s_mul_i32 s3, s15, s3 -; GCN-NEXT: s_add_u32 s3, s5, s3 -; GCN-NEXT: s_addc_u32 s5, 0, s16 +; GCN-NEXT: s_add_u32 s3, s17, s3 +; GCN-NEXT: s_mul_hi_u32 s18, s15, s16 +; GCN-NEXT: s_addc_u32 s3, s5, s19 +; GCN-NEXT: s_addc_u32 s5, s18, 0 +; GCN-NEXT: s_mul_i32 s16, s15, s16 +; GCN-NEXT: s_add_u32 s3, s3, s16 +; GCN-NEXT: s_addc_u32 s5, 0, s5 ; GCN-NEXT: s_mul_i32 s5, s10, s5 ; GCN-NEXT: s_mul_hi_u32 s16, s10, s3 ; GCN-NEXT: s_add_i32 s5, s16, s5 @@ -2972,11 +2972,11 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_i32 s5, s5, s16 ; GCN-NEXT: s_sub_i32 s18, s15, s5 ; GCN-NEXT: s_mul_i32 s3, s10, s3 -; GCN-NEXT: s_sub_i32 s3, s14, s3 +; GCN-NEXT: s_sub_u32 s3, s14, s3 ; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s14, s18, s11 -; GCN-NEXT: s_sub_i32 s20, s3, s10 +; GCN-NEXT: s_sub_u32 s20, s3, s10 ; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s21, s14, 0 @@ -2988,7 +2988,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cselect_b32 s22, s23, s22 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s14, s14, s11 -; GCN-NEXT: s_sub_i32 s23, s20, s10 +; GCN-NEXT: s_sub_u32 s23, s20, s10 ; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s14, s14, 0 @@ -3461,11 +3461,11 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: s_add_i32 s3, s3, s1 ; TONGA-NEXT: s_sub_i32 s1, s13, s3 ; TONGA-NEXT: v_readfirstlane_b32 s14, v0 -; TONGA-NEXT: s_sub_i32 s12, s12, s14 +; TONGA-NEXT: s_sub_u32 s12, s12, s14 ; TONGA-NEXT: s_cselect_b64 s[14:15], 1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, s7 -; TONGA-NEXT: s_sub_i32 s18, s12, s6 +; TONGA-NEXT: s_sub_u32 s18, s12, s6 ; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s19, s1, 0 @@ -3477,7 +3477,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: s_cselect_b32 s20, s21, s20 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, s7 -; TONGA-NEXT: s_sub_i32 s21, s18, s6 +; TONGA-NEXT: s_sub_u32 s21, s18, s6 ; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, 0 @@ -4965,7 +4965,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s23, s25, s23 ; GCN-NEXT: s_add_u32 s23, s26, s23 ; GCN-NEXT: s_addc_u32 s26, 0, s27 -; GCN-NEXT: s_add_i32 s27, s22, s23 +; GCN-NEXT: s_add_u32 s27, s22, s23 ; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 ; GCN-NEXT: s_addc_u32 s25, s25, s26 @@ -4989,29 +4989,29 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s22, s25, s22 ; GCN-NEXT: s_add_u32 s17, s17, s22 ; GCN-NEXT: s_addc_u32 s24, 0, s23 -; GCN-NEXT: s_add_i32 s27, s27, s17 +; GCN-NEXT: s_add_u32 s17, s27, s17 ; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 -; GCN-NEXT: s_addc_u32 s17, s25, s24 +; GCN-NEXT: s_addc_u32 s26, s25, s24 ; GCN-NEXT: s_ashr_i32 s22, s19, 31 ; GCN-NEXT: s_add_u32 s24, s18, s22 ; GCN-NEXT: s_mov_b32 s23, s22 ; GCN-NEXT: s_addc_u32 s25, s19, s22 ; GCN-NEXT: s_xor_b64 s[24:25], s[24:25], s[22:23] -; GCN-NEXT: s_mul_i32 s26, s24, s17 -; GCN-NEXT: s_mul_hi_u32 s28, s24, s27 -; GCN-NEXT: s_mul_hi_u32 s19, s24, s17 -; GCN-NEXT: s_add_u32 s26, s28, s26 +; GCN-NEXT: s_mul_i32 s27, s24, s26 +; GCN-NEXT: s_mul_hi_u32 s28, s24, s17 +; GCN-NEXT: s_mul_hi_u32 s19, s24, s26 +; GCN-NEXT: s_add_u32 s27, s28, s27 ; GCN-NEXT: s_addc_u32 s19, 0, s19 -; GCN-NEXT: s_mul_hi_u32 s29, s25, s27 -; GCN-NEXT: s_mul_i32 s27, s25, s27 -; GCN-NEXT: s_add_u32 s26, s26, s27 -; GCN-NEXT: s_mul_hi_u32 s28, s25, s17 -; GCN-NEXT: s_addc_u32 s19, s19, s29 -; GCN-NEXT: s_addc_u32 s26, s28, 0 +; GCN-NEXT: s_mul_hi_u32 s29, s25, s17 ; GCN-NEXT: s_mul_i32 s17, s25, s17 -; GCN-NEXT: s_add_u32 s17, s19, s17 -; GCN-NEXT: s_addc_u32 s19, 0, s26 +; GCN-NEXT: s_add_u32 s17, s27, s17 +; GCN-NEXT: s_mul_hi_u32 s28, s25, s26 +; GCN-NEXT: s_addc_u32 s17, s19, s29 +; GCN-NEXT: s_addc_u32 s19, s28, 0 +; GCN-NEXT: s_mul_i32 s26, s25, s26 +; GCN-NEXT: s_add_u32 s17, s17, s26 +; GCN-NEXT: s_addc_u32 s19, 0, s19 ; GCN-NEXT: s_mul_i32 s19, s6, s19 ; GCN-NEXT: s_mul_hi_u32 s26, s6, s17 ; GCN-NEXT: s_add_i32 s19, s26, s19 @@ -5019,11 +5019,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_i32 s19, s19, s26 ; GCN-NEXT: s_sub_i32 s28, s25, s19 ; GCN-NEXT: s_mul_i32 s17, s6, s17 -; GCN-NEXT: s_sub_i32 s17, s24, s17 +; GCN-NEXT: s_sub_u32 s17, s24, s17 ; GCN-NEXT: s_cselect_b64 s[26:27], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 ; GCN-NEXT: s_subb_u32 s24, s28, s7 -; GCN-NEXT: s_sub_i32 s30, s17, s6 +; GCN-NEXT: s_sub_u32 s30, s17, s6 ; GCN-NEXT: s_cselect_b64 s[28:29], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[28:29], 0 ; GCN-NEXT: s_subb_u32 s31, s24, 0 @@ -5035,7 +5035,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cselect_b32 s33, s34, s33 ; GCN-NEXT: s_cmp_lg_u64 s[28:29], 0 ; GCN-NEXT: s_subb_u32 s24, s24, s7 -; GCN-NEXT: s_sub_i32 s34, s30, s6 +; GCN-NEXT: s_sub_u32 s34, s30, s6 ; GCN-NEXT: s_cselect_b64 s[28:29], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[28:29], 0 ; GCN-NEXT: s_subb_u32 s24, s24, 0 @@ -5122,7 +5122,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s21, s23, s21 ; GCN-NEXT: s_add_u32 s21, s24, s21 ; GCN-NEXT: s_addc_u32 s24, 0, s25 -; GCN-NEXT: s_add_i32 s25, s20, s21 +; GCN-NEXT: s_add_u32 s25, s20, s21 ; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_addc_u32 s23, s23, s24 @@ -5146,29 +5146,29 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s20, s23, s20 ; GCN-NEXT: s_add_u32 s13, s13, s20 ; GCN-NEXT: s_addc_u32 s22, 0, s21 -; GCN-NEXT: s_add_i32 s25, s25, s13 +; GCN-NEXT: s_add_u32 s13, s25, s13 ; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 -; GCN-NEXT: s_addc_u32 s13, s23, s22 +; GCN-NEXT: s_addc_u32 s24, s23, s22 ; GCN-NEXT: s_ashr_i32 s20, s15, 31 ; GCN-NEXT: s_add_u32 s22, s14, s20 ; GCN-NEXT: s_mov_b32 s21, s20 ; GCN-NEXT: s_addc_u32 s23, s15, s20 ; GCN-NEXT: s_xor_b64 s[22:23], s[22:23], s[20:21] -; GCN-NEXT: s_mul_i32 s24, s22, s13 -; GCN-NEXT: s_mul_hi_u32 s26, s22, s25 -; GCN-NEXT: s_mul_hi_u32 s15, s22, s13 -; GCN-NEXT: s_add_u32 s24, s26, s24 +; GCN-NEXT: s_mul_i32 s25, s22, s24 +; GCN-NEXT: s_mul_hi_u32 s26, s22, s13 +; GCN-NEXT: s_mul_hi_u32 s15, s22, s24 +; GCN-NEXT: s_add_u32 s25, s26, s25 ; GCN-NEXT: s_addc_u32 s15, 0, s15 -; GCN-NEXT: s_mul_hi_u32 s27, s23, s25 -; GCN-NEXT: s_mul_i32 s25, s23, s25 -; GCN-NEXT: s_add_u32 s24, s24, s25 -; GCN-NEXT: s_mul_hi_u32 s26, s23, s13 -; GCN-NEXT: s_addc_u32 s15, s15, s27 -; GCN-NEXT: s_addc_u32 s24, s26, 0 +; GCN-NEXT: s_mul_hi_u32 s27, s23, s13 ; GCN-NEXT: s_mul_i32 s13, s23, s13 -; GCN-NEXT: s_add_u32 s13, s15, s13 -; GCN-NEXT: s_addc_u32 s15, 0, s24 +; GCN-NEXT: s_add_u32 s13, s25, s13 +; GCN-NEXT: s_mul_hi_u32 s26, s23, s24 +; GCN-NEXT: s_addc_u32 s13, s15, s27 +; GCN-NEXT: s_addc_u32 s15, s26, 0 +; GCN-NEXT: s_mul_i32 s24, s23, s24 +; GCN-NEXT: s_add_u32 s13, s13, s24 +; GCN-NEXT: s_addc_u32 s15, 0, s15 ; GCN-NEXT: s_mul_i32 s15, s18, s15 ; GCN-NEXT: s_mul_hi_u32 s24, s18, s13 ; GCN-NEXT: s_add_i32 s15, s24, s15 @@ -5176,11 +5176,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_i32 s15, s15, s24 ; GCN-NEXT: s_sub_i32 s26, s23, s15 ; GCN-NEXT: s_mul_i32 s13, s18, s13 -; GCN-NEXT: s_sub_i32 s13, s22, s13 +; GCN-NEXT: s_sub_u32 s13, s22, s13 ; GCN-NEXT: s_cselect_b64 s[24:25], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[24:25], 0 ; GCN-NEXT: s_subb_u32 s22, s26, s19 -; GCN-NEXT: s_sub_i32 s28, s13, s18 +; GCN-NEXT: s_sub_u32 s28, s13, s18 ; GCN-NEXT: s_cselect_b64 s[26:27], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 ; GCN-NEXT: s_subb_u32 s29, s22, 0 @@ -5192,7 +5192,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cselect_b32 s30, s31, s30 ; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 ; GCN-NEXT: s_subb_u32 s22, s22, s19 -; GCN-NEXT: s_sub_i32 s31, s28, s18 +; GCN-NEXT: s_sub_u32 s31, s28, s18 ; GCN-NEXT: s_cselect_b64 s[26:27], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 ; GCN-NEXT: s_subb_u32 s22, s22, 0 @@ -5288,7 +5288,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s17, s19, s17 ; GCN-NEXT: s_add_u32 s17, s20, s17 ; GCN-NEXT: s_addc_u32 s20, 0, s21 -; GCN-NEXT: s_add_i32 s21, s16, s17 +; GCN-NEXT: s_add_u32 s21, s16, s17 ; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_addc_u32 s19, s19, s20 @@ -5312,29 +5312,29 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s16, s19, s16 ; GCN-NEXT: s_add_u32 s9, s9, s16 ; GCN-NEXT: s_addc_u32 s18, 0, s17 -; GCN-NEXT: s_add_i32 s21, s21, s9 +; GCN-NEXT: s_add_u32 s9, s21, s9 ; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 -; GCN-NEXT: s_addc_u32 s9, s19, s18 +; GCN-NEXT: s_addc_u32 s20, s19, s18 ; GCN-NEXT: s_ashr_i32 s16, s11, 31 ; GCN-NEXT: s_add_u32 s18, s10, s16 ; GCN-NEXT: s_mov_b32 s17, s16 ; GCN-NEXT: s_addc_u32 s19, s11, s16 ; GCN-NEXT: s_xor_b64 s[18:19], s[18:19], s[16:17] -; GCN-NEXT: s_mul_i32 s20, s18, s9 -; GCN-NEXT: s_mul_hi_u32 s22, s18, s21 -; GCN-NEXT: s_mul_hi_u32 s11, s18, s9 -; GCN-NEXT: s_add_u32 s20, s22, s20 +; GCN-NEXT: s_mul_i32 s21, s18, s20 +; GCN-NEXT: s_mul_hi_u32 s22, s18, s9 +; GCN-NEXT: s_mul_hi_u32 s11, s18, s20 +; GCN-NEXT: s_add_u32 s21, s22, s21 ; GCN-NEXT: s_addc_u32 s11, 0, s11 -; GCN-NEXT: s_mul_hi_u32 s23, s19, s21 -; GCN-NEXT: s_mul_i32 s21, s19, s21 -; GCN-NEXT: s_add_u32 s20, s20, s21 -; GCN-NEXT: s_mul_hi_u32 s22, s19, s9 -; GCN-NEXT: s_addc_u32 s11, s11, s23 -; GCN-NEXT: s_addc_u32 s20, s22, 0 +; GCN-NEXT: s_mul_hi_u32 s23, s19, s9 ; GCN-NEXT: s_mul_i32 s9, s19, s9 -; GCN-NEXT: s_add_u32 s9, s11, s9 -; GCN-NEXT: s_addc_u32 s11, 0, s20 +; GCN-NEXT: s_add_u32 s9, s21, s9 +; GCN-NEXT: s_mul_hi_u32 s22, s19, s20 +; GCN-NEXT: s_addc_u32 s9, s11, s23 +; GCN-NEXT: s_addc_u32 s11, s22, 0 +; GCN-NEXT: s_mul_i32 s20, s19, s20 +; GCN-NEXT: s_add_u32 s9, s9, s20 +; GCN-NEXT: s_addc_u32 s11, 0, s11 ; GCN-NEXT: s_mul_i32 s11, s14, s11 ; GCN-NEXT: s_mul_hi_u32 s20, s14, s9 ; GCN-NEXT: s_add_i32 s11, s20, s11 @@ -5342,11 +5342,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_i32 s11, s11, s20 ; GCN-NEXT: s_sub_i32 s22, s19, s11 ; GCN-NEXT: s_mul_i32 s9, s14, s9 -; GCN-NEXT: s_sub_i32 s9, s18, s9 +; GCN-NEXT: s_sub_u32 s9, s18, s9 ; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_subb_u32 s18, s22, s15 -; GCN-NEXT: s_sub_i32 s24, s9, s14 +; GCN-NEXT: s_sub_u32 s24, s9, s14 ; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 ; GCN-NEXT: s_subb_u32 s25, s18, 0 @@ -5358,7 +5358,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cselect_b32 s26, s27, s26 ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 ; GCN-NEXT: s_subb_u32 s18, s18, s15 -; GCN-NEXT: s_sub_i32 s27, s24, s14 +; GCN-NEXT: s_sub_u32 s27, s24, s14 ; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 ; GCN-NEXT: s_subb_u32 s18, s18, 0 @@ -5451,7 +5451,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s13, s15, s13 ; GCN-NEXT: s_add_u32 s13, s16, s13 ; GCN-NEXT: s_addc_u32 s16, 0, s17 -; GCN-NEXT: s_add_i32 s17, s12, s13 +; GCN-NEXT: s_add_u32 s17, s12, s13 ; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GCN-NEXT: s_addc_u32 s15, s15, s16 @@ -5475,29 +5475,29 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_mul_i32 s12, s15, s12 ; GCN-NEXT: s_add_u32 s3, s3, s12 ; GCN-NEXT: s_addc_u32 s14, 0, s13 -; GCN-NEXT: s_add_i32 s17, s17, s3 +; GCN-NEXT: s_add_u32 s3, s17, s3 ; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 -; GCN-NEXT: s_addc_u32 s3, s15, s14 +; GCN-NEXT: s_addc_u32 s16, s15, s14 ; GCN-NEXT: s_ashr_i32 s12, s5, 31 ; GCN-NEXT: s_add_u32 s14, s4, s12 ; GCN-NEXT: s_mov_b32 s13, s12 ; GCN-NEXT: s_addc_u32 s15, s5, s12 ; GCN-NEXT: s_xor_b64 s[14:15], s[14:15], s[12:13] -; GCN-NEXT: s_mul_i32 s16, s14, s3 -; GCN-NEXT: s_mul_hi_u32 s18, s14, s17 -; GCN-NEXT: s_mul_hi_u32 s5, s14, s3 -; GCN-NEXT: s_add_u32 s16, s18, s16 +; GCN-NEXT: s_mul_i32 s17, s14, s16 +; GCN-NEXT: s_mul_hi_u32 s18, s14, s3 +; GCN-NEXT: s_mul_hi_u32 s5, s14, s16 +; GCN-NEXT: s_add_u32 s17, s18, s17 ; GCN-NEXT: s_addc_u32 s5, 0, s5 -; GCN-NEXT: s_mul_hi_u32 s19, s15, s17 -; GCN-NEXT: s_mul_i32 s17, s15, s17 -; GCN-NEXT: s_add_u32 s16, s16, s17 -; GCN-NEXT: s_mul_hi_u32 s18, s15, s3 -; GCN-NEXT: s_addc_u32 s5, s5, s19 -; GCN-NEXT: s_addc_u32 s16, s18, 0 +; GCN-NEXT: s_mul_hi_u32 s19, s15, s3 ; GCN-NEXT: s_mul_i32 s3, s15, s3 -; GCN-NEXT: s_add_u32 s3, s5, s3 -; GCN-NEXT: s_addc_u32 s5, 0, s16 +; GCN-NEXT: s_add_u32 s3, s17, s3 +; GCN-NEXT: s_mul_hi_u32 s18, s15, s16 +; GCN-NEXT: s_addc_u32 s3, s5, s19 +; GCN-NEXT: s_addc_u32 s5, s18, 0 +; GCN-NEXT: s_mul_i32 s16, s15, s16 +; GCN-NEXT: s_add_u32 s3, s3, s16 +; GCN-NEXT: s_addc_u32 s5, 0, s5 ; GCN-NEXT: s_mul_i32 s5, s10, s5 ; GCN-NEXT: s_mul_hi_u32 s16, s10, s3 ; GCN-NEXT: s_add_i32 s5, s16, s5 @@ -5505,11 +5505,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_i32 s5, s5, s16 ; GCN-NEXT: s_sub_i32 s18, s15, s5 ; GCN-NEXT: s_mul_i32 s3, s10, s3 -; GCN-NEXT: s_sub_i32 s3, s14, s3 +; GCN-NEXT: s_sub_u32 s3, s14, s3 ; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s14, s18, s11 -; GCN-NEXT: s_sub_i32 s20, s3, s10 +; GCN-NEXT: s_sub_u32 s20, s3, s10 ; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s21, s14, 0 @@ -5521,7 +5521,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cselect_b32 s22, s23, s22 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s14, s14, s11 -; GCN-NEXT: s_sub_i32 s23, s20, s10 +; GCN-NEXT: s_sub_u32 s23, s20, s10 ; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s14, s14, 0 @@ -6297,11 +6297,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: s_add_i32 s3, s3, s1 ; TONGA-NEXT: s_sub_i32 s1, s13, s3 ; TONGA-NEXT: v_readfirstlane_b32 s14, v8 -; TONGA-NEXT: s_sub_i32 s12, s12, s14 +; TONGA-NEXT: s_sub_u32 s12, s12, s14 ; TONGA-NEXT: s_cselect_b64 s[14:15], 1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, s7 -; TONGA-NEXT: s_sub_i32 s18, s12, s6 +; TONGA-NEXT: s_sub_u32 s18, s12, s6 ; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s19, s1, 0 @@ -6313,7 +6313,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: s_cselect_b32 s20, s21, s20 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, s7 -; TONGA-NEXT: s_sub_i32 s21, s18, s6 +; TONGA-NEXT: s_sub_u32 s21, s18, s6 ; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, 0 diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index d2a6c7d32b0a2..eb4cc9130776d 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -49,7 +49,7 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_mul_i32 s1, s12, s1 ; GCN-NEXT: s_add_u32 s1, s13, s1 ; GCN-NEXT: s_addc_u32 s13, 0, s14 -; GCN-NEXT: s_add_i32 s14, s0, s1 +; GCN-NEXT: s_add_u32 s14, s0, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s14 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 @@ -82,7 +82,7 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_mul_i32 s0, s12, s0 ; GCN-NEXT: s_add_u32 s0, s1, s0 ; GCN-NEXT: s_addc_u32 s10, 0, s10 -; GCN-NEXT: s_add_i32 s11, s14, s0 +; GCN-NEXT: s_add_u32 s11, s14, s0 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 @@ -118,12 +118,12 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_add_i32 s10, s5, s10 ; GCN-NEXT: s_sub_i32 s11, s7, s10 ; GCN-NEXT: s_mul_i32 s4, s8, s4 -; GCN-NEXT: s_sub_i32 s6, s6, s4 +; GCN-NEXT: s_sub_u32 s6, s6, s4 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s12, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s12, 0 ; GCN-NEXT: s_subb_u32 s11, s11, s9 -; GCN-NEXT: s_sub_i32 s13, s6, s8 +; GCN-NEXT: s_sub_u32 s13, s6, s8 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 @@ -136,7 +136,7 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_cselect_b32 s15, s15, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_subb_u32 s11, s11, s9 -; GCN-NEXT: s_sub_i32 s16, s13, s8 +; GCN-NEXT: s_sub_u32 s16, s13, s8 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 @@ -1009,7 +1009,7 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 % ; GCN-NEXT: s_mul_i32 s9, s12, s9 ; GCN-NEXT: s_add_u32 s9, s13, s9 ; GCN-NEXT: s_addc_u32 s13, 0, s14 -; GCN-NEXT: s_add_i32 s14, s8, s9 +; GCN-NEXT: s_add_u32 s14, s8, s9 ; GCN-NEXT: v_mov_b32_e32 v0, s14 ; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 @@ -1042,7 +1042,7 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 % ; GCN-NEXT: s_mul_i32 s8, s12, s8 ; GCN-NEXT: s_add_u32 s8, s9, s8 ; GCN-NEXT: s_addc_u32 s10, 0, s10 -; GCN-NEXT: s_add_i32 s11, s14, s8 +; GCN-NEXT: s_add_u32 s11, s14, s8 ; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GCN-NEXT: s_or_b32 s8, s8, s9 ; GCN-NEXT: s_cmp_lg_u32 s8, 0 @@ -1081,12 +1081,12 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 % ; GCN-NEXT: s_add_i32 s12, s11, s12 ; GCN-NEXT: s_sub_i32 s13, s7, s12 ; GCN-NEXT: s_mul_i32 s10, s4, s10 -; GCN-NEXT: s_sub_i32 s6, s6, s10 +; GCN-NEXT: s_sub_u32 s6, s6, s10 ; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GCN-NEXT: s_or_b32 s14, s10, s11 ; GCN-NEXT: s_cmp_lg_u32 s14, 0 ; GCN-NEXT: s_subb_u32 s13, s13, s5 -; GCN-NEXT: s_sub_i32 s15, s6, s4 +; GCN-NEXT: s_sub_u32 s15, s6, s4 ; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GCN-NEXT: s_or_b32 s10, s10, s11 ; GCN-NEXT: s_cmp_lg_u32 s10, 0 @@ -1099,7 +1099,7 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 % ; GCN-NEXT: s_cselect_b32 s17, s17, s11 ; GCN-NEXT: s_cmp_lg_u32 s10, 0 ; GCN-NEXT: s_subb_u32 s13, s13, s5 -; GCN-NEXT: s_sub_i32 s18, s15, s4 +; GCN-NEXT: s_sub_u32 s18, s15, s4 ; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 ; GCN-NEXT: s_or_b32 s10, s10, s11 ; GCN-NEXT: s_cmp_lg_u32 s10, 0 @@ -1358,7 +1358,7 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_mul_i32 s7, s9, s7 ; GCN-NEXT: s_add_u32 s7, s10, s7 ; GCN-NEXT: s_addc_u32 s10, 0, s11 -; GCN-NEXT: s_add_i32 s11, s6, s7 +; GCN-NEXT: s_add_u32 s11, s6, s7 ; GCN-NEXT: v_mov_b32_e32 v0, s11 ; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 @@ -1391,12 +1391,12 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_mul_i32 s6, s9, s6 ; GCN-NEXT: s_add_u32 s2, s2, s6 ; GCN-NEXT: s_addc_u32 s8, 0, s7 -; GCN-NEXT: s_add_i32 s11, s11, s2 +; GCN-NEXT: s_add_u32 s2, s11, s2 ; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 -; GCN-NEXT: s_or_b32 s2, s6, s7 -; GCN-NEXT: s_cmp_lg_u32 s2, 0 +; GCN-NEXT: s_or_b32 s6, s6, s7 +; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_addc_u32 s6, s9, s8 -; GCN-NEXT: v_mul_hi_u32 v1, s11, 24 +; GCN-NEXT: v_mul_hi_u32 v1, s2, 24 ; GCN-NEXT: v_mul_hi_u32 v0, s6, 24 ; GCN-NEXT: s_mul_i32 s6, s6, 24 ; GCN-NEXT: s_mov_b32 s2, -1 @@ -1411,12 +1411,12 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: v_readfirstlane_b32 s8, v0 ; GCN-NEXT: s_add_i32 s8, s8, s7 ; GCN-NEXT: s_sub_i32 s9, 0, s8 -; GCN-NEXT: s_sub_i32 s10, 24, s6 +; GCN-NEXT: s_sub_u32 s10, 24, s6 ; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GCN-NEXT: s_or_b32 s11, s6, s7 ; GCN-NEXT: s_cmp_lg_u32 s11, 0 ; GCN-NEXT: s_subb_u32 s9, s9, s5 -; GCN-NEXT: s_sub_i32 s12, s10, s4 +; GCN-NEXT: s_sub_u32 s12, s10, s4 ; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GCN-NEXT: s_or_b32 s6, s6, s7 ; GCN-NEXT: s_cmp_lg_u32 s6, 0 @@ -1429,7 +1429,7 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_cselect_b32 s14, s14, s7 ; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_subb_u32 s9, s9, s5 -; GCN-NEXT: s_sub_i32 s15, s12, s4 +; GCN-NEXT: s_sub_u32 s15, s12, s4 ; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 ; GCN-NEXT: s_or_b32 s6, s6, s7 ; GCN-NEXT: s_cmp_lg_u32 s6, 0 diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll index cacdee31e8099..1da8e3187e518 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -828,7 +828,7 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_mul_i32 s5, s9, s5 ; GCN-NEXT: s_add_u32 s5, s10, s5 ; GCN-NEXT: s_addc_u32 s10, 0, s11 -; GCN-NEXT: s_add_i32 s11, s4, s5 +; GCN-NEXT: s_add_u32 s11, s4, s5 ; GCN-NEXT: v_mov_b32_e32 v0, s11 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s6, v0 @@ -861,12 +861,12 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_mul_i32 s4, s9, s4 ; GCN-NEXT: s_add_u32 s4, s5, s4 ; GCN-NEXT: s_addc_u32 s6, 0, s6 -; GCN-NEXT: s_add_i32 s11, s11, s4 +; GCN-NEXT: s_add_u32 s8, s11, s4 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_addc_u32 s4, s9, s6 -; GCN-NEXT: v_mul_hi_u32 v1, s11, 24 +; GCN-NEXT: v_mul_hi_u32 v1, s8, 24 ; GCN-NEXT: v_mul_hi_u32 v0, s4, 24 ; GCN-NEXT: s_mul_i32 s4, s4, 24 ; GCN-NEXT: s_mov_b32 s6, -1 @@ -883,12 +883,12 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_add_i32 s9, s1, s0 ; GCN-NEXT: s_sub_i32 s10, 0, s9 ; GCN-NEXT: s_mul_i32 s0, s2, s8 -; GCN-NEXT: s_sub_i32 s11, 24, s0 +; GCN-NEXT: s_sub_u32 s11, 24, s0 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: s_or_b32 s12, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s12, 0 ; GCN-NEXT: s_subb_u32 s10, s10, s3 -; GCN-NEXT: s_sub_i32 s13, s11, s2 +; GCN-NEXT: s_sub_u32 s13, s11, s2 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll index c9915a82f5504..7413142e92139 100644 --- a/llvm/test/CodeGen/AMDGPU/urem64.ll +++ b/llvm/test/CodeGen/AMDGPU/urem64.ll @@ -49,7 +49,7 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y ; GCN-NEXT: s_mul_i32 s1, s12, s1 ; GCN-NEXT: s_add_u32 s1, s13, s1 ; GCN-NEXT: s_addc_u32 s13, 0, s14 -; GCN-NEXT: s_add_i32 s14, s0, s1 +; GCN-NEXT: s_add_u32 s14, s0, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s14 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 @@ -82,7 +82,7 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y ; GCN-NEXT: s_mul_i32 s0, s12, s0 ; GCN-NEXT: s_add_u32 s0, s1, s0 ; GCN-NEXT: s_addc_u32 s10, 0, s10 -; GCN-NEXT: s_add_i32 s11, s14, s0 +; GCN-NEXT: s_add_u32 s11, s14, s0 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 @@ -118,12 +118,12 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y ; GCN-NEXT: s_add_i32 s10, s5, s10 ; GCN-NEXT: s_sub_i32 s11, s7, s10 ; GCN-NEXT: s_mul_i32 s4, s8, s4 -; GCN-NEXT: s_sub_i32 s6, s6, s4 +; GCN-NEXT: s_sub_u32 s6, s6, s4 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s12, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s12, 0 ; GCN-NEXT: s_subb_u32 s11, s11, s9 -; GCN-NEXT: s_sub_i32 s13, s6, s8 +; GCN-NEXT: s_sub_u32 s13, s6, s8 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 @@ -136,7 +136,7 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y ; GCN-NEXT: s_cselect_b32 s15, s15, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_subb_u32 s11, s11, s9 -; GCN-NEXT: s_sub_i32 s16, s13, s8 +; GCN-NEXT: s_sub_u32 s16, s13, s8 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 @@ -846,7 +846,7 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_mul_i32 s5, s9, s5 ; GCN-NEXT: s_add_u32 s5, s10, s5 ; GCN-NEXT: s_addc_u32 s10, 0, s11 -; GCN-NEXT: s_add_i32 s11, s4, s5 +; GCN-NEXT: s_add_u32 s11, s4, s5 ; GCN-NEXT: v_mov_b32_e32 v0, s11 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s6, v0 @@ -879,12 +879,12 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_mul_i32 s4, s9, s4 ; GCN-NEXT: s_add_u32 s4, s5, s4 ; GCN-NEXT: s_addc_u32 s6, 0, s6 -; GCN-NEXT: s_add_i32 s11, s11, s4 +; GCN-NEXT: s_add_u32 s8, s11, s4 ; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_addc_u32 s4, s9, s6 -; GCN-NEXT: v_mul_hi_u32 v1, s11, 24 +; GCN-NEXT: v_mul_hi_u32 v1, s8, 24 ; GCN-NEXT: v_mul_hi_u32 v0, s4, 24 ; GCN-NEXT: s_mul_i32 s4, s4, 24 ; GCN-NEXT: s_mov_b32 s6, -1 @@ -901,12 +901,12 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_add_i32 s9, s1, s0 ; GCN-NEXT: s_sub_i32 s10, 0, s9 ; GCN-NEXT: s_mul_i32 s0, s2, s8 -; GCN-NEXT: s_sub_i32 s8, 24, s0 +; GCN-NEXT: s_sub_u32 s8, 24, s0 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: s_or_b32 s11, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s11, 0 ; GCN-NEXT: s_subb_u32 s10, s10, s3 -; GCN-NEXT: s_sub_i32 s12, s8, s2 +; GCN-NEXT: s_sub_u32 s12, s8, s2 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 @@ -919,7 +919,7 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_cselect_b32 s14, s14, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_subb_u32 s10, s10, s3 -; GCN-NEXT: s_sub_i32 s15, s12, s2 +; GCN-NEXT: s_sub_u32 s15, s12, s2 ; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll index 89f719da21ebf..96615d7209e47 100644 --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -773,7 +773,7 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1032-NEXT: s_addc_u32 s13, s17, 0 ; GFX1032-NEXT: s_add_u32 s11, s12, s11 ; GFX1032-NEXT: s_addc_u32 s12, 0, s13 -; GFX1032-NEXT: s_add_i32 s8, s8, s11 +; GFX1032-NEXT: s_add_u32 s8, s8, s11 ; GFX1032-NEXT: s_cselect_b32 s11, 1, 0 ; GFX1032-NEXT: s_mul_hi_u32 s13, s9, s8 ; GFX1032-NEXT: s_cmp_lg_u32 s11, 0 @@ -797,7 +797,7 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1032-NEXT: s_addc_u32 s11, s11, 0 ; GFX1032-NEXT: s_add_u32 s9, s10, s9 ; GFX1032-NEXT: s_addc_u32 s10, 0, s11 -; GFX1032-NEXT: s_add_i32 s8, s8, s9 +; GFX1032-NEXT: s_add_u32 s8, s8, s9 ; GFX1032-NEXT: s_cselect_b32 s9, 1, 0 ; GFX1032-NEXT: s_mul_hi_u32 s11, s2, s8 ; GFX1032-NEXT: s_cmp_lg_u32 s9, 0 @@ -822,11 +822,11 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1032-NEXT: s_mul_i32 s10, s0, s5 ; GFX1032-NEXT: s_add_i32 s9, s9, s11 ; GFX1032-NEXT: s_sub_i32 s11, s3, s9 -; GFX1032-NEXT: s_sub_i32 s10, s2, s10 +; GFX1032-NEXT: s_sub_u32 s10, s2, s10 ; GFX1032-NEXT: s_cselect_b32 s12, 1, 0 ; GFX1032-NEXT: s_cmp_lg_u32 s12, 0 ; GFX1032-NEXT: s_subb_u32 s11, s11, s1 -; GFX1032-NEXT: s_sub_i32 s13, s10, s0 +; GFX1032-NEXT: s_sub_u32 s13, s10, s0 ; GFX1032-NEXT: s_cselect_b32 s14, 1, 0 ; GFX1032-NEXT: s_cmp_lg_u32 s14, 0 ; GFX1032-NEXT: s_subb_u32 s11, s11, 0 @@ -933,7 +933,7 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1064-NEXT: s_addc_u32 s12, s16, 0 ; GFX1064-NEXT: s_add_u32 s5, s11, s5 ; GFX1064-NEXT: s_addc_u32 s11, 0, s12 -; GFX1064-NEXT: s_add_i32 s12, s4, s5 +; GFX1064-NEXT: s_add_u32 s12, s4, s5 ; GFX1064-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX1064-NEXT: s_mul_hi_u32 s13, s9, s12 ; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 @@ -957,16 +957,16 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1064-NEXT: s_addc_u32 s5, s10, 0 ; GFX1064-NEXT: s_add_u32 s4, s4, s9 ; GFX1064-NEXT: s_addc_u32 s9, 0, s5 -; GFX1064-NEXT: s_add_i32 s12, s12, s4 +; GFX1064-NEXT: s_add_u32 s10, s12, s4 ; GFX1064-NEXT: s_cselect_b64 s[4:5], 1, 0 -; GFX1064-NEXT: s_mul_hi_u32 s10, s2, s12 +; GFX1064-NEXT: s_mul_hi_u32 s11, s2, s10 ; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 -; GFX1064-NEXT: s_mul_hi_u32 s4, s3, s12 +; GFX1064-NEXT: s_mul_hi_u32 s4, s3, s10 ; GFX1064-NEXT: s_addc_u32 s5, s8, s9 -; GFX1064-NEXT: s_mul_i32 s8, s3, s12 -; GFX1064-NEXT: s_mul_i32 s11, s2, s5 +; GFX1064-NEXT: s_mul_i32 s8, s3, s10 +; GFX1064-NEXT: s_mul_i32 s10, s2, s5 ; GFX1064-NEXT: s_mul_hi_u32 s9, s2, s5 -; GFX1064-NEXT: s_add_u32 s10, s10, s11 +; GFX1064-NEXT: s_add_u32 s10, s11, s10 ; GFX1064-NEXT: s_addc_u32 s9, 0, s9 ; GFX1064-NEXT: s_mul_hi_u32 s12, s3, s5 ; GFX1064-NEXT: s_add_u32 s8, s10, s8 @@ -982,11 +982,11 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1064-NEXT: s_add_i32 s12, s4, s8 ; GFX1064-NEXT: s_mul_i32 s4, s0, s10 ; GFX1064-NEXT: s_sub_i32 s8, s3, s12 -; GFX1064-NEXT: s_sub_i32 s13, s2, s4 +; GFX1064-NEXT: s_sub_u32 s13, s2, s4 ; GFX1064-NEXT: s_cselect_b64 s[4:5], 1, 0 ; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX1064-NEXT: s_subb_u32 s14, s8, s1 -; GFX1064-NEXT: s_sub_i32 s15, s13, s0 +; GFX1064-NEXT: s_sub_u32 s15, s13, s0 ; GFX1064-NEXT: s_cselect_b64 s[8:9], 1, 0 ; GFX1064-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX1064-NEXT: s_subb_u32 s8, s14, 0 From 463769ed1abe1e8c9c6a64e44c221463533d1500 Mon Sep 17 00:00:00 2001 From: John Lu Date: Wed, 24 Sep 2025 15:21:21 -0500 Subject: [PATCH 6/9] Set all bits for wave mask Signed-off-by: John Lu --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +- .../AMDGPU/amdgpu-codegenprepare-idiv.ll | 108 +++++++++--------- .../test/CodeGen/AMDGPU/carryout-selection.ll | 52 ++++----- .../expand-scalar-carry-out-select-user.ll | 8 +- llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll | 2 +- llvm/test/CodeGen/AMDGPU/sdiv64.ll | 16 +-- llvm/test/CodeGen/AMDGPU/srem.ll | 88 +++++++------- llvm/test/CodeGen/AMDGPU/srem64.ll | 30 ++--- llvm/test/CodeGen/AMDGPU/udiv64.ll | 8 +- llvm/test/CodeGen/AMDGPU/urem64.ll | 20 ++-- llvm/test/CodeGen/AMDGPU/wave32.ll | 16 +-- 11 files changed, 175 insertions(+), 175 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index c669b0bfb2b50..16530087444d2 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -5972,7 +5972,7 @@ SITargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, unsigned SelOpc = Subtarget->isWave64() ? AMDGPU::S_CSELECT_B64 : AMDGPU::S_CSELECT_B32; - BuildMI(*BB, MI, DL, TII->get(SelOpc), Dest1.getReg()).addImm(1).addImm(0); + BuildMI(*BB, MI, DL, TII->get(SelOpc), Dest1.getReg()).addImm(-1).addImm(0); MI.eraseFromParent(); return BB; diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll index ed41b9ece116a..b69afb8e301bb 100644 --- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll +++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll @@ -7843,7 +7843,7 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_addc_u32 s15, 0, s16 ; GFX6-NEXT: s_add_u32 s16, s0, s1 ; GFX6-NEXT: v_mov_b32_e32 v0, s16 -; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s12, v0 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_cmp_lg_u32 s0, 0 @@ -7875,7 +7875,7 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_add_u32 s0, s1, s0 ; GFX6-NEXT: s_addc_u32 s12, 0, s12 ; GFX6-NEXT: s_add_u32 s15, s16, s0 -; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_cmp_lg_u32 s0, 0 ; GFX6-NEXT: s_addc_u32 s14, s14, s12 @@ -7916,12 +7916,12 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_sub_i32 s17, s7, s16 ; GFX6-NEXT: s_mul_i32 s4, s10, s14 ; GFX6-NEXT: s_sub_u32 s6, s6, s4 -; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX6-NEXT: s_or_b32 s18, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s18, 0 ; GFX6-NEXT: s_subb_u32 s17, s17, s11 ; GFX6-NEXT: s_sub_u32 s19, s6, s10 -; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX6-NEXT: s_or_b32 s4, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 ; GFX6-NEXT: s_subb_u32 s4, s17, 0 @@ -8005,7 +8005,7 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_add_u32 s5, s13, s5 ; GFX9-NEXT: s_addc_u32 s13, 0, s14 ; GFX9-NEXT: s_add_u32 s14, s4, s5 -; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s12, s12, s13 ; GFX9-NEXT: s_mul_i32 s4, s10, s12 @@ -8029,7 +8029,7 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_add_u32 s4, s10, s4 ; GFX9-NEXT: s_addc_u32 s10, 0, s5 ; GFX9-NEXT: s_add_u32 s11, s14, s4 -; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s10, s12, s10 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) @@ -8060,11 +8060,11 @@ define amdgpu_kernel void @sdiv_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_sub_i32 s12, s3, s16 ; GFX9-NEXT: s_mul_i32 s10, s8, s14 ; GFX9-NEXT: s_sub_u32 s2, s2, s10 -; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s17, s12, s9 ; GFX9-NEXT: s_sub_u32 s18, s2, s8 -; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_subb_u32 s12, s17, 0 ; GFX9-NEXT: s_cmp_ge_u32 s12, s9 @@ -8350,7 +8350,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_addc_u32 s17, 0, s18 ; GFX6-NEXT: s_add_u32 s18, s12, s13 ; GFX6-NEXT: v_mov_b32_e32 v0, s18 -; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s14, v0 ; GFX6-NEXT: s_or_b32 s12, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 @@ -8382,7 +8382,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_add_u32 s12, s13, s12 ; GFX6-NEXT: s_addc_u32 s14, 0, s14 ; GFX6-NEXT: s_add_u32 s15, s18, s12 -; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX6-NEXT: s_or_b32 s12, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_addc_u32 s14, s16, s14 @@ -8421,12 +8421,12 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_sub_i32 s19, s9, s18 ; GFX6-NEXT: s_mul_i32 s14, s6, s17 ; GFX6-NEXT: s_sub_u32 s8, s8, s14 -; GFX6-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[14:15], -1, 0 ; GFX6-NEXT: s_or_b32 s20, s14, s15 ; GFX6-NEXT: s_cmp_lg_u32 s20, 0 ; GFX6-NEXT: s_subb_u32 s19, s19, s7 ; GFX6-NEXT: s_sub_u32 s21, s8, s6 -; GFX6-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[14:15], -1, 0 ; GFX6-NEXT: s_or_b32 s14, s14, s15 ; GFX6-NEXT: s_cmp_lg_u32 s14, 0 ; GFX6-NEXT: s_subb_u32 s14, s19, 0 @@ -8505,7 +8505,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_addc_u32 s4, 0, s5 ; GFX6-NEXT: s_add_u32 s5, s2, s3 ; GFX6-NEXT: v_mov_b32_e32 v0, s5 -; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], -1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s12, v0 ; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 @@ -8537,7 +8537,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_add_u32 s2, s3, s2 ; GFX6-NEXT: s_addc_u32 s12, 0, s12 ; GFX6-NEXT: s_add_u32 s13, s5, s2 -; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], -1, 0 ; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_addc_u32 s12, s4, s12 @@ -8577,12 +8577,12 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_sub_i32 s19, s11, s18 ; GFX6-NEXT: s_mul_i32 s12, s8, s16 ; GFX6-NEXT: s_sub_u32 s10, s10, s12 -; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX6-NEXT: s_or_b32 s20, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s20, 0 ; GFX6-NEXT: s_subb_u32 s19, s19, s9 ; GFX6-NEXT: s_sub_u32 s21, s10, s8 -; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX6-NEXT: s_or_b32 s12, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_subb_u32 s12, s19, 0 @@ -8669,7 +8669,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_u32 s13, s17, s13 ; GFX9-NEXT: s_addc_u32 s17, 0, s18 ; GFX9-NEXT: s_add_u32 s18, s12, s13 -; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_addc_u32 s16, s16, s17 ; GFX9-NEXT: s_mul_i32 s12, s14, s16 @@ -8693,7 +8693,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_u32 s12, s14, s12 ; GFX9-NEXT: s_addc_u32 s14, 0, s13 ; GFX9-NEXT: s_add_u32 s15, s18, s12 -; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_addc_u32 s14, s16, s14 ; GFX9-NEXT: s_ashr_i32 s12, s9, 31 @@ -8723,11 +8723,11 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_sub_i32 s16, s9, s20 ; GFX9-NEXT: s_mul_i32 s14, s6, s18 ; GFX9-NEXT: s_sub_u32 s8, s8, s14 -; GFX9-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[14:15], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GFX9-NEXT: s_subb_u32 s21, s16, s7 ; GFX9-NEXT: s_sub_u32 s22, s8, s6 -; GFX9-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[16:17], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GFX9-NEXT: s_subb_u32 s16, s21, 0 ; GFX9-NEXT: s_cmp_ge_u32 s16, s7 @@ -8800,7 +8800,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_u32 s5, s5, s12 ; GFX9-NEXT: s_addc_u32 s12, 0, s16 ; GFX9-NEXT: s_add_u32 s16, s4, s5 -; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s12, s13, s12 ; GFX9-NEXT: s_mul_i32 s4, s8, s12 @@ -8824,7 +8824,7 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_u32 s4, s8, s4 ; GFX9-NEXT: s_addc_u32 s8, 0, s5 ; GFX9-NEXT: s_add_u32 s13, s16, s4 -; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s12, s12, s8 ; GFX9-NEXT: s_ashr_i32 s4, s11, 31 @@ -8854,11 +8854,11 @@ define amdgpu_kernel void @sdiv_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_sub_i32 s12, s9, s18 ; GFX9-NEXT: s_mul_i32 s10, s6, s16 ; GFX9-NEXT: s_sub_u32 s8, s8, s10 -; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s19, s12, s7 ; GFX9-NEXT: s_sub_u32 s20, s8, s6 -; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_subb_u32 s12, s19, 0 ; GFX9-NEXT: s_cmp_ge_u32 s12, s7 @@ -9111,7 +9111,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_addc_u32 s13, 0, s14 ; GFX6-NEXT: s_add_u32 s14, s0, s1 ; GFX6-NEXT: v_mov_b32_e32 v0, s14 -; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s10, v0 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_cmp_lg_u32 s0, 0 @@ -9143,7 +9143,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_add_u32 s0, s1, s0 ; GFX6-NEXT: s_addc_u32 s10, 0, s10 ; GFX6-NEXT: s_add_u32 s13, s14, s0 -; GFX6-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX6-NEXT: s_or_b32 s0, s0, s1 ; GFX6-NEXT: s_cmp_lg_u32 s0, 0 ; GFX6-NEXT: s_addc_u32 s12, s12, s10 @@ -9184,12 +9184,12 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_sub_i32 s14, s7, s13 ; GFX6-NEXT: s_mul_i32 s4, s8, s12 ; GFX6-NEXT: s_sub_u32 s6, s6, s4 -; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX6-NEXT: s_or_b32 s12, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_subb_u32 s14, s14, s9 ; GFX6-NEXT: s_sub_u32 s15, s6, s8 -; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX6-NEXT: s_or_b32 s4, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 ; GFX6-NEXT: s_subb_u32 s16, s14, 0 @@ -9202,7 +9202,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 ; GFX6-NEXT: s_subb_u32 s14, s14, s9 ; GFX6-NEXT: s_sub_u32 s18, s15, s8 -; GFX6-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX6-NEXT: s_or_b32 s4, s4, s5 ; GFX6-NEXT: s_cmp_lg_u32 s4, 0 ; GFX6-NEXT: s_subb_u32 s4, s14, 0 @@ -9275,7 +9275,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_add_u32 s5, s11, s5 ; GFX9-NEXT: s_addc_u32 s11, 0, s12 ; GFX9-NEXT: s_add_u32 s12, s4, s5 -; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s10, s10, s11 ; GFX9-NEXT: s_mul_i32 s4, s8, s10 @@ -9299,7 +9299,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_add_u32 s4, s8, s4 ; GFX9-NEXT: s_addc_u32 s8, 0, s5 ; GFX9-NEXT: s_add_u32 s9, s12, s4 -; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s8, s10, s8 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) @@ -9330,11 +9330,11 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_sub_i32 s10, s3, s12 ; GFX9-NEXT: s_mul_i32 s8, s6, s8 ; GFX9-NEXT: s_sub_u32 s2, s2, s8 -; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_subb_u32 s13, s10, s7 ; GFX9-NEXT: s_sub_u32 s14, s2, s6 -; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s15, s13, 0 ; GFX9-NEXT: s_cmp_ge_u32 s15, s7 @@ -9346,7 +9346,7 @@ define amdgpu_kernel void @srem_i64_pow2_shl_denom(ptr addrspace(1) %out, i64 %x ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s13, s13, s7 ; GFX9-NEXT: s_sub_u32 s17, s14, s6 -; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s10, s13, 0 ; GFX9-NEXT: s_cmp_lg_u32 s16, 0 @@ -9512,7 +9512,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_addc_u32 s15, 0, s16 ; GFX6-NEXT: s_add_u32 s16, s6, s7 ; GFX6-NEXT: v_mov_b32_e32 v0, s16 -; GFX6-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s12, v0 ; GFX6-NEXT: s_or_b32 s6, s6, s7 ; GFX6-NEXT: s_cmp_lg_u32 s6, 0 @@ -9544,7 +9544,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_add_u32 s6, s7, s6 ; GFX6-NEXT: s_addc_u32 s12, 0, s12 ; GFX6-NEXT: s_add_u32 s13, s16, s6 -; GFX6-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GFX6-NEXT: s_or_b32 s6, s6, s7 ; GFX6-NEXT: s_cmp_lg_u32 s6, 0 ; GFX6-NEXT: s_addc_u32 s12, s14, s12 @@ -9583,12 +9583,12 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_sub_i32 s15, s9, s14 ; GFX6-NEXT: s_mul_i32 s12, s2, s12 ; GFX6-NEXT: s_sub_u32 s8, s8, s12 -; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX6-NEXT: s_or_b32 s16, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_subb_u32 s15, s15, s3 ; GFX6-NEXT: s_sub_u32 s17, s8, s2 -; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX6-NEXT: s_or_b32 s12, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_subb_u32 s18, s15, 0 @@ -9601,7 +9601,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_subb_u32 s15, s15, s3 ; GFX6-NEXT: s_sub_u32 s20, s17, s2 -; GFX6-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX6-NEXT: s_or_b32 s12, s12, s13 ; GFX6-NEXT: s_cmp_lg_u32 s12, 0 ; GFX6-NEXT: s_subb_u32 s12, s15, 0 @@ -9669,7 +9669,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_addc_u32 s4, 0, s5 ; GFX6-NEXT: s_add_u32 s5, s2, s3 ; GFX6-NEXT: v_mov_b32_e32 v0, s5 -; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], -1, 0 ; GFX6-NEXT: v_mul_hi_u32 v0, s8, v0 ; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 @@ -9701,7 +9701,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_add_u32 s2, s3, s2 ; GFX6-NEXT: s_addc_u32 s8, 0, s8 ; GFX6-NEXT: s_add_u32 s14, s5, s2 -; GFX6-NEXT: s_cselect_b64 s[2:3], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[2:3], -1, 0 ; GFX6-NEXT: s_or_b32 s2, s2, s3 ; GFX6-NEXT: s_cmp_lg_u32 s2, 0 ; GFX6-NEXT: s_addc_u32 s15, s4, s8 @@ -9741,12 +9741,12 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_sub_i32 s15, s9, s14 ; GFX6-NEXT: s_mul_i32 s10, s6, s11 ; GFX6-NEXT: s_sub_u32 s8, s8, s10 -; GFX6-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX6-NEXT: s_or_b32 s16, s10, s11 ; GFX6-NEXT: s_cmp_lg_u32 s16, 0 ; GFX6-NEXT: s_subb_u32 s15, s15, s7 ; GFX6-NEXT: s_sub_u32 s17, s8, s6 -; GFX6-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX6-NEXT: s_or_b32 s10, s10, s11 ; GFX6-NEXT: s_cmp_lg_u32 s10, 0 ; GFX6-NEXT: s_subb_u32 s18, s15, 0 @@ -9759,7 +9759,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX6-NEXT: s_cmp_lg_u32 s10, 0 ; GFX6-NEXT: s_subb_u32 s15, s15, s7 ; GFX6-NEXT: s_sub_u32 s20, s17, s6 -; GFX6-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX6-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX6-NEXT: s_or_b32 s10, s10, s11 ; GFX6-NEXT: s_cmp_lg_u32 s10, 0 ; GFX6-NEXT: s_subb_u32 s10, s15, 0 @@ -9835,7 +9835,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_u32 s7, s15, s7 ; GFX9-NEXT: s_addc_u32 s15, 0, s16 ; GFX9-NEXT: s_add_u32 s16, s6, s7 -; GFX9-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX9-NEXT: s_addc_u32 s14, s14, s15 ; GFX9-NEXT: s_mul_i32 s6, s12, s14 @@ -9859,7 +9859,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_u32 s6, s12, s6 ; GFX9-NEXT: s_addc_u32 s12, 0, s7 ; GFX9-NEXT: s_add_u32 s13, s16, s6 -; GFX9-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX9-NEXT: s_addc_u32 s12, s14, s12 ; GFX9-NEXT: s_ashr_i32 s6, s9, 31 @@ -9889,11 +9889,11 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_sub_i32 s14, s9, s16 ; GFX9-NEXT: s_mul_i32 s12, s2, s12 ; GFX9-NEXT: s_sub_u32 s8, s8, s12 -; GFX9-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GFX9-NEXT: s_subb_u32 s17, s14, s3 ; GFX9-NEXT: s_sub_u32 s18, s8, s2 -; GFX9-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[14:15], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GFX9-NEXT: s_subb_u32 s19, s17, 0 ; GFX9-NEXT: s_cmp_ge_u32 s19, s3 @@ -9905,7 +9905,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GFX9-NEXT: s_subb_u32 s17, s17, s3 ; GFX9-NEXT: s_sub_u32 s21, s18, s2 -; GFX9-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[14:15], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GFX9-NEXT: s_subb_u32 s14, s17, 0 ; GFX9-NEXT: s_cmp_lg_u32 s20, 0 @@ -9967,7 +9967,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_u32 s5, s5, s8 ; GFX9-NEXT: s_addc_u32 s8, 0, s14 ; GFX9-NEXT: s_add_u32 s14, s4, s5 -; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s8, s9, s8 ; GFX9-NEXT: s_mul_i32 s4, s6, s8 @@ -9991,7 +9991,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_add_u32 s4, s6, s4 ; GFX9-NEXT: s_addc_u32 s6, 0, s5 ; GFX9-NEXT: s_add_u32 s9, s14, s4 -; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s8, s8, s6 ; GFX9-NEXT: s_ashr_i32 s4, s11, 31 @@ -10021,11 +10021,11 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_sub_i32 s10, s7, s14 ; GFX9-NEXT: s_mul_i32 s8, s2, s8 ; GFX9-NEXT: s_sub_u32 s6, s6, s8 -; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_subb_u32 s15, s10, s3 ; GFX9-NEXT: s_sub_u32 s16, s6, s2 -; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s17, s15, 0 ; GFX9-NEXT: s_cmp_ge_u32 s17, s3 @@ -10037,7 +10037,7 @@ define amdgpu_kernel void @srem_v2i64_pow2_shl_denom(ptr addrspace(1) %out, <2 x ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s15, s15, s3 ; GFX9-NEXT: s_sub_u32 s19, s16, s2 -; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s10, s15, 0 ; GFX9-NEXT: s_cmp_lg_u32 s18, 0 diff --git a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll index 7a6d0ecfee120..51652a09863e0 100644 --- a/llvm/test/CodeGen/AMDGPU/carryout-selection.ll +++ b/llvm/test/CodeGen/AMDGPU/carryout-selection.ll @@ -2216,11 +2216,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; VI-NEXT: s_sub_i32 s10, s3, s14 ; VI-NEXT: v_readfirstlane_b32 s8, v0 ; VI-NEXT: s_sub_u32 s15, s2, s8 -; VI-NEXT: s_cselect_b64 s[8:9], 1, 0 +; VI-NEXT: s_cselect_b64 s[8:9], -1, 0 ; VI-NEXT: s_cmp_lg_u64 s[8:9], 0 ; VI-NEXT: s_subb_u32 s16, s10, s5 ; VI-NEXT: s_sub_u32 s17, s15, s4 -; VI-NEXT: s_cselect_b64 s[10:11], 1, 0 +; VI-NEXT: s_cselect_b64 s[10:11], -1, 0 ; VI-NEXT: s_cmp_lg_u64 s[10:11], 0 ; VI-NEXT: s_subb_u32 s10, s16, 0 ; VI-NEXT: s_cmp_ge_u32 s10, s5 @@ -2330,7 +2330,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX9-NEXT: s_add_u32 s9, s13, s9 ; GFX9-NEXT: s_addc_u32 s13, 0, s14 ; GFX9-NEXT: s_add_u32 s14, s8, s9 -; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_addc_u32 s12, s12, s13 ; GFX9-NEXT: s_mul_i32 s8, s10, s12 @@ -2354,7 +2354,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX9-NEXT: s_add_u32 s8, s10, s8 ; GFX9-NEXT: s_addc_u32 s10, 0, s9 ; GFX9-NEXT: s_add_u32 s11, s14, s8 -; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_addc_u32 s8, s12, s10 ; GFX9-NEXT: s_mul_i32 s10, s2, s8 @@ -2379,11 +2379,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX9-NEXT: s_sub_i32 s10, s3, s14 ; GFX9-NEXT: s_mul_i32 s8, s6, s12 ; GFX9-NEXT: s_sub_u32 s15, s2, s8 -; GFX9-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX9-NEXT: s_subb_u32 s16, s10, s7 ; GFX9-NEXT: s_sub_u32 s17, s15, s6 -; GFX9-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GFX9-NEXT: s_subb_u32 s10, s16, 0 ; GFX9-NEXT: s_cmp_ge_u32 s10, s7 @@ -2489,7 +2489,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1010-NEXT: s_add_u32 s11, s12, s11 ; GFX1010-NEXT: s_addc_u32 s12, 0, s13 ; GFX1010-NEXT: s_add_u32 s8, s8, s11 -; GFX1010-NEXT: s_cselect_b32 s11, 1, 0 +; GFX1010-NEXT: s_cselect_b32 s11, -1, 0 ; GFX1010-NEXT: s_mul_hi_u32 s13, s9, s8 ; GFX1010-NEXT: s_cmp_lg_u32 s11, 0 ; GFX1010-NEXT: s_mul_i32 s11, s9, s8 @@ -2513,7 +2513,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1010-NEXT: s_add_u32 s9, s10, s9 ; GFX1010-NEXT: s_addc_u32 s10, 0, s11 ; GFX1010-NEXT: s_add_u32 s8, s8, s9 -; GFX1010-NEXT: s_cselect_b32 s9, 1, 0 +; GFX1010-NEXT: s_cselect_b32 s9, -1, 0 ; GFX1010-NEXT: s_mul_hi_u32 s11, s2, s8 ; GFX1010-NEXT: s_cmp_lg_u32 s9, 0 ; GFX1010-NEXT: s_mul_hi_u32 s9, s3, s8 @@ -2538,11 +2538,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1010-NEXT: s_add_i32 s9, s9, s11 ; GFX1010-NEXT: s_sub_i32 s11, s3, s9 ; GFX1010-NEXT: s_sub_u32 s10, s2, s10 -; GFX1010-NEXT: s_cselect_b32 s12, 1, 0 +; GFX1010-NEXT: s_cselect_b32 s12, -1, 0 ; GFX1010-NEXT: s_cmp_lg_u32 s12, 0 ; GFX1010-NEXT: s_subb_u32 s11, s11, s7 ; GFX1010-NEXT: s_sub_u32 s13, s10, s6 -; GFX1010-NEXT: s_cselect_b32 s14, 1, 0 +; GFX1010-NEXT: s_cselect_b32 s14, -1, 0 ; GFX1010-NEXT: s_cmp_lg_u32 s14, 0 ; GFX1010-NEXT: s_subb_u32 s11, s11, 0 ; GFX1010-NEXT: s_cmp_ge_u32 s11, s7 @@ -2649,7 +2649,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W32-NEXT: s_add_u32 s11, s12, s11 ; GFX1030W32-NEXT: s_addc_u32 s12, 0, s13 ; GFX1030W32-NEXT: s_add_u32 s8, s8, s11 -; GFX1030W32-NEXT: s_cselect_b32 s11, 1, 0 +; GFX1030W32-NEXT: s_cselect_b32 s11, -1, 0 ; GFX1030W32-NEXT: s_mul_hi_u32 s13, s9, s8 ; GFX1030W32-NEXT: s_cmp_lg_u32 s11, 0 ; GFX1030W32-NEXT: s_mul_i32 s11, s9, s8 @@ -2673,7 +2673,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W32-NEXT: s_add_u32 s9, s10, s9 ; GFX1030W32-NEXT: s_addc_u32 s10, 0, s11 ; GFX1030W32-NEXT: s_add_u32 s8, s8, s9 -; GFX1030W32-NEXT: s_cselect_b32 s9, 1, 0 +; GFX1030W32-NEXT: s_cselect_b32 s9, -1, 0 ; GFX1030W32-NEXT: s_mul_hi_u32 s11, s2, s8 ; GFX1030W32-NEXT: s_cmp_lg_u32 s9, 0 ; GFX1030W32-NEXT: s_mul_hi_u32 s9, s3, s8 @@ -2698,11 +2698,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W32-NEXT: s_add_i32 s9, s9, s11 ; GFX1030W32-NEXT: s_sub_i32 s11, s3, s9 ; GFX1030W32-NEXT: s_sub_u32 s10, s2, s10 -; GFX1030W32-NEXT: s_cselect_b32 s12, 1, 0 +; GFX1030W32-NEXT: s_cselect_b32 s12, -1, 0 ; GFX1030W32-NEXT: s_cmp_lg_u32 s12, 0 ; GFX1030W32-NEXT: s_subb_u32 s11, s11, s5 ; GFX1030W32-NEXT: s_sub_u32 s13, s10, s4 -; GFX1030W32-NEXT: s_cselect_b32 s14, 1, 0 +; GFX1030W32-NEXT: s_cselect_b32 s14, -1, 0 ; GFX1030W32-NEXT: s_cmp_lg_u32 s14, 0 ; GFX1030W32-NEXT: s_subb_u32 s11, s11, 0 ; GFX1030W32-NEXT: s_cmp_ge_u32 s11, s5 @@ -2809,7 +2809,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W64-NEXT: s_add_u32 s7, s11, s7 ; GFX1030W64-NEXT: s_addc_u32 s11, 0, s12 ; GFX1030W64-NEXT: s_add_u32 s12, s6, s7 -; GFX1030W64-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX1030W64-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GFX1030W64-NEXT: s_mul_hi_u32 s13, s9, s12 ; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX1030W64-NEXT: s_mul_i32 s6, s9, s12 @@ -2833,7 +2833,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W64-NEXT: s_add_u32 s6, s6, s9 ; GFX1030W64-NEXT: s_addc_u32 s9, 0, s7 ; GFX1030W64-NEXT: s_add_u32 s10, s12, s6 -; GFX1030W64-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX1030W64-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GFX1030W64-NEXT: s_mul_hi_u32 s11, s2, s10 ; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX1030W64-NEXT: s_mul_hi_u32 s6, s3, s10 @@ -2858,11 +2858,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1030W64-NEXT: s_mul_i32 s6, s4, s10 ; GFX1030W64-NEXT: s_sub_i32 s8, s3, s12 ; GFX1030W64-NEXT: s_sub_u32 s13, s2, s6 -; GFX1030W64-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GFX1030W64-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GFX1030W64-NEXT: s_cmp_lg_u64 s[6:7], 0 ; GFX1030W64-NEXT: s_subb_u32 s14, s8, s5 ; GFX1030W64-NEXT: s_sub_u32 s15, s13, s4 -; GFX1030W64-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX1030W64-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GFX1030W64-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX1030W64-NEXT: s_subb_u32 s8, s14, 0 ; GFX1030W64-NEXT: s_cmp_ge_u32 s8, s5 @@ -2974,7 +2974,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX11-NEXT: s_add_u32 s11, s12, s11 ; GFX11-NEXT: s_addc_u32 s12, 0, s13 ; GFX11-NEXT: s_add_u32 s8, s8, s11 -; GFX11-NEXT: s_cselect_b32 s11, 1, 0 +; GFX11-NEXT: s_cselect_b32 s11, -1, 0 ; GFX11-NEXT: s_mul_hi_u32 s13, s9, s8 ; GFX11-NEXT: s_cmp_lg_u32 s11, 0 ; GFX11-NEXT: s_mul_i32 s11, s9, s8 @@ -2998,7 +2998,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX11-NEXT: s_add_u32 s9, s10, s9 ; GFX11-NEXT: s_addc_u32 s10, 0, s11 ; GFX11-NEXT: s_add_u32 s8, s8, s9 -; GFX11-NEXT: s_cselect_b32 s9, 1, 0 +; GFX11-NEXT: s_cselect_b32 s9, -1, 0 ; GFX11-NEXT: s_mul_hi_u32 s11, s2, s8 ; GFX11-NEXT: s_cmp_lg_u32 s9, 0 ; GFX11-NEXT: s_mul_hi_u32 s9, s3, s8 @@ -3024,11 +3024,11 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_sub_i32 s11, s3, s9 ; GFX11-NEXT: s_sub_u32 s10, s2, s10 -; GFX11-NEXT: s_cselect_b32 s12, 1, 0 +; GFX11-NEXT: s_cselect_b32 s12, -1, 0 ; GFX11-NEXT: s_cmp_lg_u32 s12, 0 ; GFX11-NEXT: s_subb_u32 s11, s11, s5 ; GFX11-NEXT: s_sub_u32 s13, s10, s4 -; GFX11-NEXT: s_cselect_b32 s14, 1, 0 +; GFX11-NEXT: s_cselect_b32 s14, -1, 0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_cmp_lg_u32 s14, 0 ; GFX11-NEXT: s_subb_u32 s11, s11, 0 @@ -3141,7 +3141,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_add_nc_u64 s[12:13], s[6:7], s[12:13] ; GFX1250-NEXT: s_add_co_u32 s8, s8, s12 -; GFX1250-NEXT: s_cselect_b32 s6, 1, 0 +; GFX1250-NEXT: s_cselect_b32 s6, -1, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_cmp_lg_u32 s6, 0 ; GFX1250-NEXT: s_add_co_ci_u32 s9, s9, s13 @@ -3161,7 +3161,7 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_add_nc_u64 s[10:11], s[6:7], s[10:11] ; GFX1250-NEXT: s_add_co_u32 s8, s8, s10 -; GFX1250-NEXT: s_cselect_b32 s10, 1, 0 +; GFX1250-NEXT: s_cselect_b32 s10, -1, 0 ; GFX1250-NEXT: s_mul_hi_u32 s6, s2, s8 ; GFX1250-NEXT: s_cmp_lg_u32 s10, 0 ; GFX1250-NEXT: s_mul_hi_u32 s12, s3, s8 @@ -3183,12 +3183,12 @@ define amdgpu_kernel void @sudiv64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GFX1250-NEXT: s_mul_u64 s[8:9], s[4:5], s[10:11] ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-NEXT: s_sub_co_u32 s6, s2, s8 -; GFX1250-NEXT: s_cselect_b32 s8, 1, 0 +; GFX1250-NEXT: s_cselect_b32 s8, -1, 0 ; GFX1250-NEXT: s_sub_co_i32 s12, s3, s9 ; GFX1250-NEXT: s_cmp_lg_u32 s8, 0 ; GFX1250-NEXT: s_sub_co_ci_u32 s12, s12, s5 ; GFX1250-NEXT: s_sub_co_u32 s13, s6, s4 -; GFX1250-NEXT: s_cselect_b32 s14, 1, 0 +; GFX1250-NEXT: s_cselect_b32 s14, -1, 0 ; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-NEXT: s_cmp_lg_u32 s14, 0 ; GFX1250-NEXT: s_sub_co_ci_u32 s12, s12, 0 diff --git a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll index 897232d1756de..79b492e7a6cb5 100644 --- a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll +++ b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll @@ -12,7 +12,7 @@ define i32 @s_add_co_select_user() { ; GFX7-NEXT: s_load_dword s6, s[4:5], 0x0 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_add_u32 s7, s6, s6 -; GFX7-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX7-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX7-NEXT: s_or_b32 s4, s4, s5 ; GFX7-NEXT: s_cmp_lg_u32 s4, 0 ; GFX7-NEXT: s_addc_u32 s8, s6, 0 @@ -31,7 +31,7 @@ define i32 @s_add_co_select_user() { ; GFX9-NEXT: s_load_dword s6, s[4:5], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_add_u32 s7, s6, s6 -; GFX9-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX9-NEXT: s_addc_u32 s8, s6, 0 ; GFX9-NEXT: s_cselect_b64 s[4:5], -1, 0 @@ -49,7 +49,7 @@ define i32 @s_add_co_select_user() { ; GFX10-NEXT: s_load_dword s4, s[4:5], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_add_u32 s5, s4, s4 -; GFX10-NEXT: s_cselect_b32 s6, 1, 0 +; GFX10-NEXT: s_cselect_b32 s6, -1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s6, 0 ; GFX10-NEXT: s_addc_u32 s6, s4, 0 ; GFX10-NEXT: s_cselect_b32 s7, -1, 0 @@ -67,7 +67,7 @@ define i32 @s_add_co_select_user() { ; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_add_u32 s1, s0, s0 -; GFX11-NEXT: s_cselect_b32 s2, 1, 0 +; GFX11-NEXT: s_cselect_b32 s2, -1, 0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_cmp_lg_u32 s2, 0 ; GFX11-NEXT: s_addc_u32 s2, s0, 0 diff --git a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll index ebcd84782a3dc..134729ead3aa0 100644 --- a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll +++ b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll @@ -12,7 +12,7 @@ define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0) { ; CHECK-LABEL: s_uaddo_pseudo: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_add_u32 s0, s0, 1 -; CHECK-NEXT: s_cselect_b64 s[0:1], 1, 0 +; CHECK-NEXT: s_cselect_b64 s[0:1], -1, 0 ; CHECK-NEXT: s_cmp_lg_u64 s[0:1], 0 ; CHECK-NEXT: s_addc_u32 s0, 1, 0 ; CHECK-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index 6e712fae961aa..ddec6af0af69e 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -56,7 +56,7 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_addc_u32 s15, 0, s16 ; GCN-NEXT: s_add_u32 s16, s0, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s16 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s12, v0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 @@ -88,7 +88,7 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_add_u32 s0, s1, s0 ; GCN-NEXT: s_addc_u32 s12, 0, s12 ; GCN-NEXT: s_add_u32 s15, s16, s0 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_addc_u32 s14, s14, s12 @@ -129,12 +129,12 @@ define amdgpu_kernel void @s_test_sdiv(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_sub_i32 s17, s7, s16 ; GCN-NEXT: s_mul_i32 s4, s10, s14 ; GCN-NEXT: s_sub_u32 s6, s6, s4 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s18, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s18, 0 ; GCN-NEXT: s_subb_u32 s17, s17, s11 ; GCN-NEXT: s_sub_u32 s19, s6, s10 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_subb_u32 s4, s17, 0 @@ -1192,7 +1192,7 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_addc_u32 s12, 0, s13 ; GCN-NEXT: s_add_u32 s13, s8, s9 ; GCN-NEXT: v_mov_b32_e32 v0, s13 -; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 ; GCN-NEXT: s_or_b32 s8, s8, s9 ; GCN-NEXT: s_cmp_lg_u32 s8, 0 @@ -1224,7 +1224,7 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_add_u32 s2, s2, s8 ; GCN-NEXT: s_addc_u32 s10, 0, s9 ; GCN-NEXT: s_add_u32 s2, s13, s2 -; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GCN-NEXT: s_or_b32 s8, s8, s9 ; GCN-NEXT: s_cmp_lg_u32 s8, 0 ; GCN-NEXT: s_addc_u32 s8, s11, s10 @@ -1244,12 +1244,12 @@ define amdgpu_kernel void @s_test_sdiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_sub_i32 s12, 0, s11 ; GCN-NEXT: s_mul_i32 s8, s6, s10 ; GCN-NEXT: s_sub_u32 s13, 24, s8 -; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GCN-NEXT: s_or_b32 s14, s8, s9 ; GCN-NEXT: s_cmp_lg_u32 s14, 0 ; GCN-NEXT: s_subb_u32 s12, s12, s7 ; GCN-NEXT: s_sub_u32 s15, s13, s6 -; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GCN-NEXT: s_or_b32 s8, s8, s9 ; GCN-NEXT: s_cmp_lg_u32 s8, 0 ; GCN-NEXT: s_subb_u32 s8, s12, 0 diff --git a/llvm/test/CodeGen/AMDGPU/srem.ll b/llvm/test/CodeGen/AMDGPU/srem.ll index 964af8ab47c82..5944342b2642a 100644 --- a/llvm/test/CodeGen/AMDGPU/srem.ll +++ b/llvm/test/CodeGen/AMDGPU/srem.ll @@ -1545,7 +1545,7 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GCN-NEXT: s_add_u32 s11, s14, s11 ; GCN-NEXT: s_addc_u32 s14, 0, s15 ; GCN-NEXT: s_add_u32 s15, s10, s11 -; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GCN-NEXT: s_addc_u32 s13, s13, s14 ; GCN-NEXT: s_mul_i32 s10, s3, s13 @@ -1569,7 +1569,7 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GCN-NEXT: s_add_u32 s3, s3, s10 ; GCN-NEXT: s_addc_u32 s12, 0, s11 ; GCN-NEXT: s_add_u32 s3, s15, s3 -; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[10:11], 0 ; GCN-NEXT: s_addc_u32 s14, s13, s12 ; GCN-NEXT: s_ashr_i32 s10, s5, 31 @@ -1599,11 +1599,11 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GCN-NEXT: s_sub_i32 s16, s13, s5 ; GCN-NEXT: s_mul_i32 s3, s8, s3 ; GCN-NEXT: s_sub_u32 s3, s12, s3 -; GCN-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GCN-NEXT: s_cselect_b64 s[14:15], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GCN-NEXT: s_subb_u32 s12, s16, s9 ; GCN-NEXT: s_sub_u32 s18, s3, s8 -; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cselect_b64 s[16:17], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s19, s12, 0 ; GCN-NEXT: s_cmp_ge_u32 s19, s9 @@ -1615,7 +1615,7 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s12, s12, s9 ; GCN-NEXT: s_sub_u32 s21, s18, s8 -; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cselect_b64 s[16:17], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s12, s12, 0 ; GCN-NEXT: s_cmp_lg_u32 s20, 0 @@ -1930,11 +1930,11 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; TONGA-NEXT: s_sub_i32 s3, s13, s5 ; TONGA-NEXT: v_readfirstlane_b32 s14, v0 ; TONGA-NEXT: s_sub_u32 s12, s12, s14 -; TONGA-NEXT: s_cselect_b64 s[14:15], 1, 0 +; TONGA-NEXT: s_cselect_b64 s[14:15], -1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 ; TONGA-NEXT: s_subb_u32 s3, s3, s7 ; TONGA-NEXT: s_sub_u32 s18, s12, s6 -; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cselect_b64 s[16:17], -1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s19, s3, 0 ; TONGA-NEXT: s_cmp_ge_u32 s19, s7 @@ -1946,7 +1946,7 @@ define amdgpu_kernel void @srem_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s3, s3, s7 ; TONGA-NEXT: s_sub_u32 s21, s18, s6 -; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cselect_b64 s[16:17], -1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s3, s3, 0 ; TONGA-NEXT: s_cmp_lg_u32 s20, 0 @@ -2762,7 +2762,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s15, s18, s15 ; GCN-NEXT: s_addc_u32 s18, 0, s19 ; GCN-NEXT: s_add_u32 s19, s14, s15 -; GCN-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GCN-NEXT: s_cselect_b64 s[14:15], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GCN-NEXT: s_addc_u32 s17, s17, s18 ; GCN-NEXT: s_mul_i32 s14, s9, s17 @@ -2786,7 +2786,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s9, s9, s14 ; GCN-NEXT: s_addc_u32 s16, 0, s15 ; GCN-NEXT: s_add_u32 s9, s19, s9 -; GCN-NEXT: s_cselect_b64 s[14:15], 1, 0 +; GCN-NEXT: s_cselect_b64 s[14:15], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[14:15], 0 ; GCN-NEXT: s_addc_u32 s18, s17, s16 ; GCN-NEXT: s_ashr_i32 s14, s11, 31 @@ -2816,11 +2816,11 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_sub_i32 s20, s17, s11 ; GCN-NEXT: s_mul_i32 s9, s6, s9 ; GCN-NEXT: s_sub_u32 s9, s16, s9 -; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cselect_b64 s[18:19], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s16, s20, s7 ; GCN-NEXT: s_sub_u32 s22, s9, s6 -; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cselect_b64 s[20:21], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_subb_u32 s23, s16, 0 ; GCN-NEXT: s_cmp_ge_u32 s23, s7 @@ -2832,7 +2832,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_subb_u32 s16, s16, s7 ; GCN-NEXT: s_sub_u32 s25, s22, s6 -; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cselect_b64 s[20:21], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_subb_u32 s16, s16, 0 ; GCN-NEXT: s_cmp_lg_u32 s24, 0 @@ -2919,7 +2919,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s13, s16, s13 ; GCN-NEXT: s_addc_u32 s16, 0, s17 ; GCN-NEXT: s_add_u32 s17, s12, s13 -; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GCN-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GCN-NEXT: s_addc_u32 s15, s15, s16 ; GCN-NEXT: s_mul_i32 s12, s3, s15 @@ -2943,7 +2943,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s3, s3, s12 ; GCN-NEXT: s_addc_u32 s14, 0, s13 ; GCN-NEXT: s_add_u32 s3, s17, s3 -; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GCN-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GCN-NEXT: s_addc_u32 s16, s15, s14 ; GCN-NEXT: s_ashr_i32 s12, s5, 31 @@ -2973,11 +2973,11 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_sub_i32 s18, s15, s5 ; GCN-NEXT: s_mul_i32 s3, s10, s3 ; GCN-NEXT: s_sub_u32 s3, s14, s3 -; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cselect_b64 s[16:17], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s14, s18, s11 ; GCN-NEXT: s_sub_u32 s20, s3, s10 -; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cselect_b64 s[18:19], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s21, s14, 0 ; GCN-NEXT: s_cmp_ge_u32 s21, s11 @@ -2989,7 +2989,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s14, s14, s11 ; GCN-NEXT: s_sub_u32 s23, s20, s10 -; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cselect_b64 s[18:19], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s14, s14, 0 ; GCN-NEXT: s_cmp_lg_u32 s22, 0 @@ -3462,11 +3462,11 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: s_sub_i32 s1, s13, s3 ; TONGA-NEXT: v_readfirstlane_b32 s14, v0 ; TONGA-NEXT: s_sub_u32 s12, s12, s14 -; TONGA-NEXT: s_cselect_b64 s[14:15], 1, 0 +; TONGA-NEXT: s_cselect_b64 s[14:15], -1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, s7 ; TONGA-NEXT: s_sub_u32 s18, s12, s6 -; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cselect_b64 s[16:17], -1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s19, s1, 0 ; TONGA-NEXT: s_cmp_ge_u32 s19, s7 @@ -3478,7 +3478,7 @@ define amdgpu_kernel void @srem_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, s7 ; TONGA-NEXT: s_sub_u32 s21, s18, s6 -; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cselect_b64 s[16:17], -1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, 0 ; TONGA-NEXT: s_cmp_lg_u32 s20, 0 @@ -4966,7 +4966,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s23, s26, s23 ; GCN-NEXT: s_addc_u32 s26, 0, s27 ; GCN-NEXT: s_add_u32 s27, s22, s23 -; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 +; GCN-NEXT: s_cselect_b64 s[22:23], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 ; GCN-NEXT: s_addc_u32 s25, s25, s26 ; GCN-NEXT: s_mul_i32 s22, s17, s25 @@ -4990,7 +4990,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s17, s17, s22 ; GCN-NEXT: s_addc_u32 s24, 0, s23 ; GCN-NEXT: s_add_u32 s17, s27, s17 -; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 +; GCN-NEXT: s_cselect_b64 s[22:23], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 ; GCN-NEXT: s_addc_u32 s26, s25, s24 ; GCN-NEXT: s_ashr_i32 s22, s19, 31 @@ -5020,11 +5020,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_sub_i32 s28, s25, s19 ; GCN-NEXT: s_mul_i32 s17, s6, s17 ; GCN-NEXT: s_sub_u32 s17, s24, s17 -; GCN-NEXT: s_cselect_b64 s[26:27], 1, 0 +; GCN-NEXT: s_cselect_b64 s[26:27], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 ; GCN-NEXT: s_subb_u32 s24, s28, s7 ; GCN-NEXT: s_sub_u32 s30, s17, s6 -; GCN-NEXT: s_cselect_b64 s[28:29], 1, 0 +; GCN-NEXT: s_cselect_b64 s[28:29], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[28:29], 0 ; GCN-NEXT: s_subb_u32 s31, s24, 0 ; GCN-NEXT: s_cmp_ge_u32 s31, s7 @@ -5036,7 +5036,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cmp_lg_u64 s[28:29], 0 ; GCN-NEXT: s_subb_u32 s24, s24, s7 ; GCN-NEXT: s_sub_u32 s34, s30, s6 -; GCN-NEXT: s_cselect_b64 s[28:29], 1, 0 +; GCN-NEXT: s_cselect_b64 s[28:29], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[28:29], 0 ; GCN-NEXT: s_subb_u32 s24, s24, 0 ; GCN-NEXT: s_cmp_lg_u32 s33, 0 @@ -5123,7 +5123,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s21, s24, s21 ; GCN-NEXT: s_addc_u32 s24, 0, s25 ; GCN-NEXT: s_add_u32 s25, s20, s21 -; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cselect_b64 s[20:21], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_addc_u32 s23, s23, s24 ; GCN-NEXT: s_mul_i32 s20, s13, s23 @@ -5147,7 +5147,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s13, s13, s20 ; GCN-NEXT: s_addc_u32 s22, 0, s21 ; GCN-NEXT: s_add_u32 s13, s25, s13 -; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cselect_b64 s[20:21], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_addc_u32 s24, s23, s22 ; GCN-NEXT: s_ashr_i32 s20, s15, 31 @@ -5177,11 +5177,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_sub_i32 s26, s23, s15 ; GCN-NEXT: s_mul_i32 s13, s18, s13 ; GCN-NEXT: s_sub_u32 s13, s22, s13 -; GCN-NEXT: s_cselect_b64 s[24:25], 1, 0 +; GCN-NEXT: s_cselect_b64 s[24:25], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[24:25], 0 ; GCN-NEXT: s_subb_u32 s22, s26, s19 ; GCN-NEXT: s_sub_u32 s28, s13, s18 -; GCN-NEXT: s_cselect_b64 s[26:27], 1, 0 +; GCN-NEXT: s_cselect_b64 s[26:27], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 ; GCN-NEXT: s_subb_u32 s29, s22, 0 ; GCN-NEXT: s_cmp_ge_u32 s29, s19 @@ -5193,7 +5193,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 ; GCN-NEXT: s_subb_u32 s22, s22, s19 ; GCN-NEXT: s_sub_u32 s31, s28, s18 -; GCN-NEXT: s_cselect_b64 s[26:27], 1, 0 +; GCN-NEXT: s_cselect_b64 s[26:27], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[26:27], 0 ; GCN-NEXT: s_subb_u32 s22, s22, 0 ; GCN-NEXT: s_cmp_lg_u32 s30, 0 @@ -5289,7 +5289,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s17, s20, s17 ; GCN-NEXT: s_addc_u32 s20, 0, s21 ; GCN-NEXT: s_add_u32 s21, s16, s17 -; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cselect_b64 s[16:17], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_addc_u32 s19, s19, s20 ; GCN-NEXT: s_mul_i32 s16, s9, s19 @@ -5313,7 +5313,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s9, s9, s16 ; GCN-NEXT: s_addc_u32 s18, 0, s17 ; GCN-NEXT: s_add_u32 s9, s21, s9 -; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cselect_b64 s[16:17], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_addc_u32 s20, s19, s18 ; GCN-NEXT: s_ashr_i32 s16, s11, 31 @@ -5343,11 +5343,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_sub_i32 s22, s19, s11 ; GCN-NEXT: s_mul_i32 s9, s14, s9 ; GCN-NEXT: s_sub_u32 s9, s18, s9 -; GCN-NEXT: s_cselect_b64 s[20:21], 1, 0 +; GCN-NEXT: s_cselect_b64 s[20:21], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[20:21], 0 ; GCN-NEXT: s_subb_u32 s18, s22, s15 ; GCN-NEXT: s_sub_u32 s24, s9, s14 -; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 +; GCN-NEXT: s_cselect_b64 s[22:23], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 ; GCN-NEXT: s_subb_u32 s25, s18, 0 ; GCN-NEXT: s_cmp_ge_u32 s25, s15 @@ -5359,7 +5359,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 ; GCN-NEXT: s_subb_u32 s18, s18, s15 ; GCN-NEXT: s_sub_u32 s27, s24, s14 -; GCN-NEXT: s_cselect_b64 s[22:23], 1, 0 +; GCN-NEXT: s_cselect_b64 s[22:23], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[22:23], 0 ; GCN-NEXT: s_subb_u32 s18, s18, 0 ; GCN-NEXT: s_cmp_lg_u32 s26, 0 @@ -5452,7 +5452,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s13, s16, s13 ; GCN-NEXT: s_addc_u32 s16, 0, s17 ; GCN-NEXT: s_add_u32 s17, s12, s13 -; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GCN-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GCN-NEXT: s_addc_u32 s15, s15, s16 ; GCN-NEXT: s_mul_i32 s12, s3, s15 @@ -5476,7 +5476,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s3, s3, s12 ; GCN-NEXT: s_addc_u32 s14, 0, s13 ; GCN-NEXT: s_add_u32 s3, s17, s3 -; GCN-NEXT: s_cselect_b64 s[12:13], 1, 0 +; GCN-NEXT: s_cselect_b64 s[12:13], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[12:13], 0 ; GCN-NEXT: s_addc_u32 s16, s15, s14 ; GCN-NEXT: s_ashr_i32 s12, s5, 31 @@ -5506,11 +5506,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_sub_i32 s18, s15, s5 ; GCN-NEXT: s_mul_i32 s3, s10, s3 ; GCN-NEXT: s_sub_u32 s3, s14, s3 -; GCN-NEXT: s_cselect_b64 s[16:17], 1, 0 +; GCN-NEXT: s_cselect_b64 s[16:17], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[16:17], 0 ; GCN-NEXT: s_subb_u32 s14, s18, s11 ; GCN-NEXT: s_sub_u32 s20, s3, s10 -; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cselect_b64 s[18:19], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s21, s14, 0 ; GCN-NEXT: s_cmp_ge_u32 s21, s11 @@ -5522,7 +5522,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s14, s14, s11 ; GCN-NEXT: s_sub_u32 s23, s20, s10 -; GCN-NEXT: s_cselect_b64 s[18:19], 1, 0 +; GCN-NEXT: s_cselect_b64 s[18:19], -1, 0 ; GCN-NEXT: s_cmp_lg_u64 s[18:19], 0 ; GCN-NEXT: s_subb_u32 s14, s14, 0 ; GCN-NEXT: s_cmp_lg_u32 s22, 0 @@ -6298,11 +6298,11 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: s_sub_i32 s1, s13, s3 ; TONGA-NEXT: v_readfirstlane_b32 s14, v8 ; TONGA-NEXT: s_sub_u32 s12, s12, s14 -; TONGA-NEXT: s_cselect_b64 s[14:15], 1, 0 +; TONGA-NEXT: s_cselect_b64 s[14:15], -1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[14:15], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, s7 ; TONGA-NEXT: s_sub_u32 s18, s12, s6 -; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cselect_b64 s[16:17], -1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s19, s1, 0 ; TONGA-NEXT: s_cmp_ge_u32 s19, s7 @@ -6314,7 +6314,7 @@ define amdgpu_kernel void @srem_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %i ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, s7 ; TONGA-NEXT: s_sub_u32 s21, s18, s6 -; TONGA-NEXT: s_cselect_b64 s[16:17], 1, 0 +; TONGA-NEXT: s_cselect_b64 s[16:17], -1, 0 ; TONGA-NEXT: s_cmp_lg_u64 s[16:17], 0 ; TONGA-NEXT: s_subb_u32 s1, s1, 0 ; TONGA-NEXT: s_cmp_lg_u32 s20, 0 diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index eb4cc9130776d..2d95875cad882 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -51,7 +51,7 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_addc_u32 s13, 0, s14 ; GCN-NEXT: s_add_u32 s14, s0, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s14 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 @@ -83,7 +83,7 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_add_u32 s0, s1, s0 ; GCN-NEXT: s_addc_u32 s10, 0, s10 ; GCN-NEXT: s_add_u32 s11, s14, s0 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_addc_u32 s1, s12, s10 @@ -119,12 +119,12 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_sub_i32 s11, s7, s10 ; GCN-NEXT: s_mul_i32 s4, s8, s4 ; GCN-NEXT: s_sub_u32 s6, s6, s4 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s12, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s12, 0 ; GCN-NEXT: s_subb_u32 s11, s11, s9 ; GCN-NEXT: s_sub_u32 s13, s6, s8 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_subb_u32 s14, s11, 0 @@ -137,7 +137,7 @@ define amdgpu_kernel void @s_test_srem(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_subb_u32 s11, s11, s9 ; GCN-NEXT: s_sub_u32 s16, s13, s8 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_subb_u32 s4, s11, 0 @@ -1011,7 +1011,7 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 % ; GCN-NEXT: s_addc_u32 s13, 0, s14 ; GCN-NEXT: s_add_u32 s14, s8, s9 ; GCN-NEXT: v_mov_b32_e32 v0, s14 -; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 ; GCN-NEXT: s_or_b32 s8, s8, s9 ; GCN-NEXT: s_cmp_lg_u32 s8, 0 @@ -1043,7 +1043,7 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 % ; GCN-NEXT: s_add_u32 s8, s9, s8 ; GCN-NEXT: s_addc_u32 s10, 0, s10 ; GCN-NEXT: s_add_u32 s11, s14, s8 -; GCN-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GCN-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GCN-NEXT: s_or_b32 s8, s8, s9 ; GCN-NEXT: s_cmp_lg_u32 s8, 0 ; GCN-NEXT: s_addc_u32 s10, s12, s10 @@ -1082,12 +1082,12 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 % ; GCN-NEXT: s_sub_i32 s13, s7, s12 ; GCN-NEXT: s_mul_i32 s10, s4, s10 ; GCN-NEXT: s_sub_u32 s6, s6, s10 -; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GCN-NEXT: s_or_b32 s14, s10, s11 ; GCN-NEXT: s_cmp_lg_u32 s14, 0 ; GCN-NEXT: s_subb_u32 s13, s13, s5 ; GCN-NEXT: s_sub_u32 s15, s6, s4 -; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GCN-NEXT: s_or_b32 s10, s10, s11 ; GCN-NEXT: s_cmp_lg_u32 s10, 0 ; GCN-NEXT: s_subb_u32 s16, s13, 0 @@ -1100,7 +1100,7 @@ define amdgpu_kernel void @s_test_srem33_64(ptr addrspace(1) %out, i64 %x, i64 % ; GCN-NEXT: s_cmp_lg_u32 s10, 0 ; GCN-NEXT: s_subb_u32 s13, s13, s5 ; GCN-NEXT: s_sub_u32 s18, s15, s4 -; GCN-NEXT: s_cselect_b64 s[10:11], 1, 0 +; GCN-NEXT: s_cselect_b64 s[10:11], -1, 0 ; GCN-NEXT: s_or_b32 s10, s10, s11 ; GCN-NEXT: s_cmp_lg_u32 s10, 0 ; GCN-NEXT: s_subb_u32 s10, s13, 0 @@ -1360,7 +1360,7 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_addc_u32 s10, 0, s11 ; GCN-NEXT: s_add_u32 s11, s6, s7 ; GCN-NEXT: v_mov_b32_e32 v0, s11 -; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 ; GCN-NEXT: s_or_b32 s6, s6, s7 ; GCN-NEXT: s_cmp_lg_u32 s6, 0 @@ -1392,7 +1392,7 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_add_u32 s2, s2, s6 ; GCN-NEXT: s_addc_u32 s8, 0, s7 ; GCN-NEXT: s_add_u32 s2, s11, s2 -; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GCN-NEXT: s_or_b32 s6, s6, s7 ; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_addc_u32 s6, s9, s8 @@ -1412,12 +1412,12 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_add_i32 s8, s8, s7 ; GCN-NEXT: s_sub_i32 s9, 0, s8 ; GCN-NEXT: s_sub_u32 s10, 24, s6 -; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GCN-NEXT: s_or_b32 s11, s6, s7 ; GCN-NEXT: s_cmp_lg_u32 s11, 0 ; GCN-NEXT: s_subb_u32 s9, s9, s5 ; GCN-NEXT: s_sub_u32 s12, s10, s4 -; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GCN-NEXT: s_or_b32 s6, s6, s7 ; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_subb_u32 s13, s9, 0 @@ -1430,7 +1430,7 @@ define amdgpu_kernel void @s_test_srem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_subb_u32 s9, s9, s5 ; GCN-NEXT: s_sub_u32 s15, s12, s4 -; GCN-NEXT: s_cselect_b64 s[6:7], 1, 0 +; GCN-NEXT: s_cselect_b64 s[6:7], -1, 0 ; GCN-NEXT: s_or_b32 s6, s6, s7 ; GCN-NEXT: s_cmp_lg_u32 s6, 0 ; GCN-NEXT: s_subb_u32 s6, s9, 0 diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll index 1da8e3187e518..dc11e81476a7e 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -830,7 +830,7 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_addc_u32 s10, 0, s11 ; GCN-NEXT: s_add_u32 s11, s4, s5 ; GCN-NEXT: v_mov_b32_e32 v0, s11 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s6, v0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 @@ -862,7 +862,7 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_add_u32 s4, s5, s4 ; GCN-NEXT: s_addc_u32 s6, 0, s6 ; GCN-NEXT: s_add_u32 s8, s11, s4 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_addc_u32 s4, s9, s6 @@ -884,12 +884,12 @@ define amdgpu_kernel void @s_test_udiv_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_sub_i32 s10, 0, s9 ; GCN-NEXT: s_mul_i32 s0, s2, s8 ; GCN-NEXT: s_sub_u32 s11, 24, s0 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: s_or_b32 s12, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s12, 0 ; GCN-NEXT: s_subb_u32 s10, s10, s3 ; GCN-NEXT: s_sub_u32 s13, s11, s2 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_subb_u32 s0, s10, 0 diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll index 7413142e92139..dc25caadb99a9 100644 --- a/llvm/test/CodeGen/AMDGPU/urem64.ll +++ b/llvm/test/CodeGen/AMDGPU/urem64.ll @@ -51,7 +51,7 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y ; GCN-NEXT: s_addc_u32 s13, 0, s14 ; GCN-NEXT: s_add_u32 s14, s0, s1 ; GCN-NEXT: v_mov_b32_e32 v0, s14 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s10, v0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 @@ -83,7 +83,7 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y ; GCN-NEXT: s_add_u32 s0, s1, s0 ; GCN-NEXT: s_addc_u32 s10, 0, s10 ; GCN-NEXT: s_add_u32 s11, s14, s0 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_addc_u32 s1, s12, s10 @@ -119,12 +119,12 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y ; GCN-NEXT: s_sub_i32 s11, s7, s10 ; GCN-NEXT: s_mul_i32 s4, s8, s4 ; GCN-NEXT: s_sub_u32 s6, s6, s4 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s12, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s12, 0 ; GCN-NEXT: s_subb_u32 s11, s11, s9 ; GCN-NEXT: s_sub_u32 s13, s6, s8 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_subb_u32 s14, s11, 0 @@ -137,7 +137,7 @@ define amdgpu_kernel void @s_test_urem_i64(ptr addrspace(1) %out, i64 %x, i64 %y ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_subb_u32 s11, s11, s9 ; GCN-NEXT: s_sub_u32 s16, s13, s8 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_subb_u32 s4, s11, 0 @@ -848,7 +848,7 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_addc_u32 s10, 0, s11 ; GCN-NEXT: s_add_u32 s11, s4, s5 ; GCN-NEXT: v_mov_b32_e32 v0, s11 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: v_mul_hi_u32 v0, s6, v0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 @@ -880,7 +880,7 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_add_u32 s4, s5, s4 ; GCN-NEXT: s_addc_u32 s6, 0, s6 ; GCN-NEXT: s_add_u32 s8, s11, s4 -; GCN-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GCN-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GCN-NEXT: s_or_b32 s4, s4, s5 ; GCN-NEXT: s_cmp_lg_u32 s4, 0 ; GCN-NEXT: s_addc_u32 s4, s9, s6 @@ -902,12 +902,12 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_sub_i32 s10, 0, s9 ; GCN-NEXT: s_mul_i32 s0, s2, s8 ; GCN-NEXT: s_sub_u32 s8, 24, s0 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: s_or_b32 s11, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s11, 0 ; GCN-NEXT: s_subb_u32 s10, s10, s3 ; GCN-NEXT: s_sub_u32 s12, s8, s2 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_subb_u32 s13, s10, 0 @@ -920,7 +920,7 @@ define amdgpu_kernel void @s_test_urem_k_num_i64(ptr addrspace(1) %out, i64 %x) ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_subb_u32 s10, s10, s3 ; GCN-NEXT: s_sub_u32 s15, s12, s2 -; GCN-NEXT: s_cselect_b64 s[0:1], 1, 0 +; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_subb_u32 s0, s10, 0 diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll index 96615d7209e47..75db3879e7b03 100644 --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -774,7 +774,7 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1032-NEXT: s_add_u32 s11, s12, s11 ; GFX1032-NEXT: s_addc_u32 s12, 0, s13 ; GFX1032-NEXT: s_add_u32 s8, s8, s11 -; GFX1032-NEXT: s_cselect_b32 s11, 1, 0 +; GFX1032-NEXT: s_cselect_b32 s11, -1, 0 ; GFX1032-NEXT: s_mul_hi_u32 s13, s9, s8 ; GFX1032-NEXT: s_cmp_lg_u32 s11, 0 ; GFX1032-NEXT: s_mul_i32 s11, s9, s8 @@ -798,7 +798,7 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1032-NEXT: s_add_u32 s9, s10, s9 ; GFX1032-NEXT: s_addc_u32 s10, 0, s11 ; GFX1032-NEXT: s_add_u32 s8, s8, s9 -; GFX1032-NEXT: s_cselect_b32 s9, 1, 0 +; GFX1032-NEXT: s_cselect_b32 s9, -1, 0 ; GFX1032-NEXT: s_mul_hi_u32 s11, s2, s8 ; GFX1032-NEXT: s_cmp_lg_u32 s9, 0 ; GFX1032-NEXT: s_mul_hi_u32 s9, s3, s8 @@ -823,11 +823,11 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1032-NEXT: s_add_i32 s9, s9, s11 ; GFX1032-NEXT: s_sub_i32 s11, s3, s9 ; GFX1032-NEXT: s_sub_u32 s10, s2, s10 -; GFX1032-NEXT: s_cselect_b32 s12, 1, 0 +; GFX1032-NEXT: s_cselect_b32 s12, -1, 0 ; GFX1032-NEXT: s_cmp_lg_u32 s12, 0 ; GFX1032-NEXT: s_subb_u32 s11, s11, s1 ; GFX1032-NEXT: s_sub_u32 s13, s10, s0 -; GFX1032-NEXT: s_cselect_b32 s14, 1, 0 +; GFX1032-NEXT: s_cselect_b32 s14, -1, 0 ; GFX1032-NEXT: s_cmp_lg_u32 s14, 0 ; GFX1032-NEXT: s_subb_u32 s11, s11, 0 ; GFX1032-NEXT: s_cmp_ge_u32 s11, s1 @@ -934,7 +934,7 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1064-NEXT: s_add_u32 s5, s11, s5 ; GFX1064-NEXT: s_addc_u32 s11, 0, s12 ; GFX1064-NEXT: s_add_u32 s12, s4, s5 -; GFX1064-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX1064-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX1064-NEXT: s_mul_hi_u32 s13, s9, s12 ; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX1064-NEXT: s_mul_i32 s4, s9, s12 @@ -958,7 +958,7 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1064-NEXT: s_add_u32 s4, s4, s9 ; GFX1064-NEXT: s_addc_u32 s9, 0, s5 ; GFX1064-NEXT: s_add_u32 s10, s12, s4 -; GFX1064-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX1064-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX1064-NEXT: s_mul_hi_u32 s11, s2, s10 ; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX1064-NEXT: s_mul_hi_u32 s4, s3, s10 @@ -983,11 +983,11 @@ define amdgpu_kernel void @test_udiv64(ptr addrspace(1) %arg) #0 { ; GFX1064-NEXT: s_mul_i32 s4, s0, s10 ; GFX1064-NEXT: s_sub_i32 s8, s3, s12 ; GFX1064-NEXT: s_sub_u32 s13, s2, s4 -; GFX1064-NEXT: s_cselect_b64 s[4:5], 1, 0 +; GFX1064-NEXT: s_cselect_b64 s[4:5], -1, 0 ; GFX1064-NEXT: s_cmp_lg_u64 s[4:5], 0 ; GFX1064-NEXT: s_subb_u32 s14, s8, s1 ; GFX1064-NEXT: s_sub_u32 s15, s13, s0 -; GFX1064-NEXT: s_cselect_b64 s[8:9], 1, 0 +; GFX1064-NEXT: s_cselect_b64 s[8:9], -1, 0 ; GFX1064-NEXT: s_cmp_lg_u64 s[8:9], 0 ; GFX1064-NEXT: s_subb_u32 s8, s14, 0 ; GFX1064-NEXT: s_cmp_ge_u32 s8, s1 From a1c7c6fe5ca07c007cdd0d528905acf0911ad380 Mon Sep 17 00:00:00 2001 From: John Lu Date: Thu, 25 Sep 2025 09:15:04 -0500 Subject: [PATCH 7/9] Use same subtarget. Test sub. Signed-off-by: John Lu --- llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll index 134729ead3aa0..a828ee0a7883c 100644 --- a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll +++ b/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 -; RUN: llc -mtriple=amdgcn-amd-amdpal -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN-ISEL %s +; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -stop-after=amdgpu-isel < %s | FileCheck -check-prefixes=GCN-ISEL %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s ; Ensure that S_UADDO_PSEUDO is selected when carryout user is S_ADD_CO_PSEUDO @@ -22,5 +22,25 @@ define amdgpu_ps i32 @s_uaddo_pseudo(i32 inreg %val0) { %result = add i32 %zext_carryout, 1 ret i32 %result } + +; GCN-ISEL-LABEL: name: s_usubo_pseudo +; GCN-ISEL-LABEL: body: +; GCN-ISEL: S_USUBO_PSEUDO +; GCN-ISEL: S_SUB_CO_PSEUDO + +define amdgpu_ps i32 @s_usubo_pseudo(i32 inreg %val0, i32 inreg %val1) { +; CHECK-LABEL: s_usubo_pseudo: +; CHECK: ; %bb.0: +; CHECK-NEXT: s_sub_u32 s0, s0, 1 +; CHECK-NEXT: s_cselect_b64 s[2:3], -1, 0 +; CHECK-NEXT: s_cmp_lg_u64 s[2:3], 0 +; CHECK-NEXT: s_subb_u32 s0, s1, 0 +; CHECK-NEXT: ; return to shader part epilog + %pair = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %val0, i32 1) + %carryout = extractvalue { i32, i1 } %pair, 1 + %zext_carryout = zext i1 %carryout to i32 + %result = sub i32 %val1, %zext_carryout + ret i32 %result +} ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; GCN-ISEL: {{.*}} From d9e3a34f8059ad154354d470b539733be344128f Mon Sep 17 00:00:00 2001 From: John Lu Date: Thu, 25 Sep 2025 09:41:09 -0500 Subject: [PATCH 8/9] Rename testcase Signed-off-by: John Lu --- .../CodeGen/AMDGPU/{s_uaddo_pseudo.ll => s_uaddo_usubo_pseudo.ll} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename llvm/test/CodeGen/AMDGPU/{s_uaddo_pseudo.ll => s_uaddo_usubo_pseudo.ll} (100%) diff --git a/llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll b/llvm/test/CodeGen/AMDGPU/s_uaddo_usubo_pseudo.ll similarity index 100% rename from llvm/test/CodeGen/AMDGPU/s_uaddo_pseudo.ll rename to llvm/test/CodeGen/AMDGPU/s_uaddo_usubo_pseudo.ll From e4fabc65c78e912d958dcd1ceadaf52da1106944 Mon Sep 17 00:00:00 2001 From: John Lu Date: Thu, 25 Sep 2025 11:23:13 -0500 Subject: [PATCH 9/9] Update testcase Signed-off-by: John Lu --- .../AMDGPU/expand-scalar-carry-out-select-user.ll | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll index 79b492e7a6cb5..d8a5e7fa3b029 100644 --- a/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll +++ b/llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll @@ -101,7 +101,8 @@ define amdgpu_kernel void @s_add_co_br_user(i32 %i) { ; GFX7-NEXT: s_lshr_b32 flat_scratch_hi, s12, 8 ; GFX7-NEXT: s_mov_b32 flat_scratch_lo, s13 ; GFX7-NEXT: s_waitcnt lgkmcnt(0) -; GFX7-NEXT: v_add_i32_e64 v0, s[0:1], s2, s2 +; GFX7-NEXT: s_add_u32 s0, s2, s2 +; GFX7-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX7-NEXT: s_or_b32 s0, s0, s1 ; GFX7-NEXT: s_cmp_lg_u32 s0, 0 ; GFX7-NEXT: s_addc_u32 s0, s2, 0 @@ -126,7 +127,8 @@ define amdgpu_kernel void @s_add_co_br_user(i32 %i) { ; GFX9: ; %bb.0: ; %bb ; GFX9-NEXT: s_load_dword s2, s[8:9], 0x0 ; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e64 v0, s[0:1], s2, s2 +; GFX9-NEXT: s_add_u32 s0, s2, s2 +; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 ; GFX9-NEXT: s_cmp_lg_u64 s[0:1], 0 ; GFX9-NEXT: s_addc_u32 s0, s2, 0 ; GFX9-NEXT: s_cselect_b64 s[0:1], -1, 0 @@ -150,7 +152,8 @@ define amdgpu_kernel void @s_add_co_br_user(i32 %i) { ; GFX10: ; %bb.0: ; %bb ; GFX10-NEXT: s_load_dword s0, s[8:9], 0x0 ; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s1, s0, s0 +; GFX10-NEXT: s_add_u32 s1, s0, s0 +; GFX10-NEXT: s_cselect_b32 s1, -1, 0 ; GFX10-NEXT: s_cmp_lg_u32 s1, 0 ; GFX10-NEXT: s_addc_u32 s0, s0, 0 ; GFX10-NEXT: s_cselect_b32 s0, -1, 0 @@ -174,11 +177,12 @@ define amdgpu_kernel void @s_add_co_br_user(i32 %i) { ; GFX11: ; %bb.0: ; %bb ; GFX11-NEXT: s_load_b32 s0, s[4:5], 0x0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s1, s0, s0 +; GFX11-NEXT: s_add_u32 s1, s0, s0 +; GFX11-NEXT: s_cselect_b32 s1, -1, 0 +; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_cmp_lg_u32 s1, 0 ; GFX11-NEXT: s_addc_u32 s0, s0, 0 ; GFX11-NEXT: s_cselect_b32 s0, -1, 0 -; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0 ; GFX11-NEXT: s_cbranch_vccnz .LBB1_2 ; GFX11-NEXT: ; %bb.1: ; %bb0