[IR] Fix a few implicit conversions from TypeSize to uint64_t. NFC #159894
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@llvm/pr-subscribers-tablegen @llvm/pr-subscribers-llvm-ir Author: Craig Topper (topperc) ChangesFull diff: https://github.com/llvm/llvm-project/pull/159894.diff 8 Files Affected:
diff --git a/llvm/include/llvm/Analysis/MemoryLocation.h b/llvm/include/llvm/Analysis/MemoryLocation.h
index 360d945939c39..e69bf6373bc96 100644
--- a/llvm/include/llvm/Analysis/MemoryLocation.h
+++ b/llvm/include/llvm/Analysis/MemoryLocation.h
@@ -146,7 +146,8 @@ class LocationSize {
if (isScalable() || Other.isScalable())
return afterPointer();
- return upperBound(std::max(getValue(), Other.getValue()));
+ return upperBound(
+ std::max(getValue().getFixedValue(), Other.getValue().getFixedValue()));
}
bool hasValue() const {
diff --git a/llvm/include/llvm/CodeGenTypes/MachineValueType.h b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
index 321fb6b601868..e4114ae957c70 100644
--- a/llvm/include/llvm/CodeGenTypes/MachineValueType.h
+++ b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
@@ -202,7 +202,7 @@ namespace llvm {
/// bitwidth.
MVT changeVectorElementTypeToInteger() const {
MVT EltTy = getVectorElementType();
- MVT IntTy = MVT::getIntegerVT(EltTy.getSizeInBits());
+ MVT IntTy = MVT::getIntegerVT(EltTy.getFixedSizeInBits());
MVT VecTy = MVT::getVectorVT(IntTy, getVectorElementCount());
assert(VecTy.SimpleTy != MVT::INVALID_SIMPLE_VALUE_TYPE &&
"Simple vector VT not representable by simple integer vector VT!");
@@ -224,7 +224,7 @@ namespace llvm {
MVT changeTypeToInteger() {
if (isVector())
return changeVectorElementTypeToInteger();
- return MVT::getIntegerVT(getSizeInBits());
+ return MVT::getIntegerVT(getFixedSizeInBits());
}
/// Return a VT for a vector type with the same element type but
diff --git a/llvm/include/llvm/IR/DerivedTypes.h b/llvm/include/llvm/IR/DerivedTypes.h
index 29b34cfe33964..b22177c9e6c2d 100644
--- a/llvm/include/llvm/IR/DerivedTypes.h
+++ b/llvm/include/llvm/IR/DerivedTypes.h
@@ -479,7 +479,8 @@ class VectorType : public Type {
/// the input type, and the element type is an integer type of the same width
/// as the input element type.
static VectorType *getInteger(VectorType *VTy) {
- unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();
+ unsigned EltBits =
+ VTy->getElementType()->getPrimitiveSizeInBits().getFixedValue();
assert(EltBits && "Element size must be of a non-zero size");
Type *EltTy = IntegerType::get(VTy->getContext(), EltBits);
return VectorType::get(EltTy, VTy->getElementCount());
@@ -510,7 +511,8 @@ class VectorType : public Type {
llvm_unreachable("Cannot create narrower fp vector element type");
}
} else {
- unsigned EltBits = VTy->getElementType()->getPrimitiveSizeInBits();
+ unsigned EltBits =
+ VTy->getElementType()->getPrimitiveSizeInBits().getFixedValue();
assert((EltBits & 1) == 0 &&
"Cannot truncate vector element with odd bit-width");
EltTy = IntegerType::get(VTy->getContext(), EltBits / 2);
diff --git a/llvm/lib/IR/Constants.cpp b/llvm/lib/IR/Constants.cpp
index c7e3113a54f22..2c2950c70d346 100644
--- a/llvm/lib/IR/Constants.cpp
+++ b/llvm/lib/IR/Constants.cpp
@@ -2864,7 +2864,7 @@ uint64_t ConstantDataSequential::getNumElements() const {
}
uint64_t ConstantDataSequential::getElementByteSize() const {
- return getElementType()->getPrimitiveSizeInBits() / 8;
+ return getElementType()->getPrimitiveSizeInBits().getFixedValue() / 8;
}
/// Return the start of the specified element.
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index 601f2e5192d0d..daebf447a2107 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -3234,8 +3234,12 @@ CastInst::getCastOpcode(
}
// Get the bit sizes, we'll need these
- unsigned SrcBits = SrcTy->getPrimitiveSizeInBits(); // 0 for ptr
- unsigned DestBits = DestTy->getPrimitiveSizeInBits(); // 0 for ptr
+ // FIXME: This doesn't work for scalable vector types with different element
+ // counts that don't call getElementType above.
+ unsigned SrcBits =
+ SrcTy->getPrimitiveSizeInBits().getFixedValue(); // 0 for ptr
+ unsigned DestBits =
+ DestTy->getPrimitiveSizeInBits().getFixedValue(); // 0 for ptr
// Run through the possibilities ...
if (DestTy->isIntegerTy()) { // Casting to integral
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 17cbfa2458375..9bde965d660a4 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -4411,7 +4411,7 @@ void Verifier::visitNoaliasAddrspaceMetadata(Instruction &I, MDNode *Range,
}
void Verifier::checkAtomicMemAccessSize(Type *Ty, const Instruction *I) {
- unsigned Size = DL.getTypeSizeInBits(Ty);
+ unsigned Size = DL.getTypeSizeInBits(Ty).getFixedValue();
Check(Size >= 8, "atomic memory access' size must be byte-sized", Ty, I);
Check(!(Size & (Size - 1)),
"atomic memory access' operand must have a power-of-two size", Ty, I);
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index 57dc1b38b8ec3..123881e276584 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -2435,8 +2435,8 @@ bool llvm::replaceAllDbgUsesWith(Instruction &From, Value &To,
// Handle integer-to-integer widening and narrowing.
// FIXME: Use DW_OP_convert when it's available everywhere.
if (FromTy->isIntegerTy() && ToTy->isIntegerTy()) {
- uint64_t FromBits = FromTy->getPrimitiveSizeInBits();
- uint64_t ToBits = ToTy->getPrimitiveSizeInBits();
+ uint64_t FromBits = FromTy->getIntegerBitWidth();
+ uint64_t ToBits = ToTy->getIntegerBitWidth();
assert(FromBits != ToBits && "Unexpected no-op conversion");
// When the width of the result grows, assume that a debugger will only
diff --git a/llvm/utils/TableGen/Common/DAGISelMatcher.h b/llvm/utils/TableGen/Common/DAGISelMatcher.h
index b11c1366ef5f0..f87de757f4f8b 100644
--- a/llvm/utils/TableGen/Common/DAGISelMatcher.h
+++ b/llvm/utils/TableGen/Common/DAGISelMatcher.h
@@ -838,8 +838,9 @@ class EmitIntegerMatcher : public Matcher {
public:
EmitIntegerMatcher(int64_t val, MVT::SimpleValueType vt, unsigned resultNo)
- : Matcher(EmitInteger), Val(SignExtend64(val, MVT(vt).getSizeInBits())),
- VT(vt), ResultNo(resultNo) {}
+ : Matcher(EmitInteger),
+ Val(SignExtend64(val, MVT(vt).getFixedSizeInBits())), VT(vt),
+ ResultNo(resultNo) {}
int64_t getValue() const { return Val; }
MVT::SimpleValueType getVT() const { return VT; }
|
Contributor
|
Is the plan here to also eventually get rid of the implicit conversion similar to the plan for conversions from |
Collaborator
Author
Yes. See #159290 |
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/27/builds/16365 Here is the relevant piece of the build log for the reference |
Collaborator
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/18/builds/21355 Here is the relevant piece of the build log for the reference |
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