From 21ad7e2a427e054b24df7d924c02bbe453e980fe Mon Sep 17 00:00:00 2001 From: Roman Belenov Date: Mon, 22 Sep 2025 11:59:39 +0300 Subject: [PATCH 1/8] Enable latency instrument on RISC V --- .../Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 8 ++-- .../RISCV/SiFiveX280/latency-instrument.s | 44 +++++++++++++++++++ 2 files changed, 49 insertions(+), 3 deletions(-) create mode 100644 llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index ae44306170758..9b6f3504cf7ff 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -86,7 +86,8 @@ uint8_t RISCVSEWInstrument::getSEW() const { bool RISCVInstrumentManager::supportsInstrumentType( llvm::StringRef Type) const { return Type == RISCVLMULInstrument::DESC_NAME || - Type == RISCVSEWInstrument::DESC_NAME; + Type == RISCVSEWInstrument::DESC_NAME || + InstrumentManager::supportsInstrumentType(Type);; } UniqueInstrument @@ -110,8 +111,9 @@ RISCVInstrumentManager::createInstrument(llvm::StringRef Desc, return std::make_unique(Data); } - LLVM_DEBUG(dbgs() << "RVCB: Unknown instrumentation Desc: " << Desc << '\n'); - return nullptr; + LLVM_DEBUG(dbgs() << "RVCB: Creating default instrument for Desc: " + << Desc << '\n'); + return InstrumentManager::createInstrument(Desc, Data); } SmallVector diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s new file mode 100644 index 0000000000000..0ac183be85d54 --- /dev/null +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s @@ -0,0 +1,44 @@ +# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s + +# LLVM-MCA-LATENCY 100 +add a0, a0, a0 + +# CHECK: Iterations: 1 +# CHECK-NEXT: Instructions: 1 +# CHECK-NEXT: Total Cycles: 101 +# CHECK-NEXT: Total uOps: 1 + +# CHECK: Dispatch Width: 2 +# CHECK-NEXT: uOps Per Cycle: 0.01 +# CHECK-NEXT: IPC: 0.01 +# CHECK-NEXT: Block RThroughput: 0.5 + +# CHECK: Instruction Info: +# CHECK-NEXT: [1]: #uOps +# CHECK-NEXT: [2]: Latency +# CHECK-NEXT: [3]: RThroughput +# CHECK-NEXT: [4]: MayLoad +# CHECK-NEXT: [5]: MayStore +# CHECK-NEXT: [6]: HasSideEffects (U) + +# CHECK: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-NEXT: 1 3 0.50 add a0, a0, a0 + +# CHECK: Resources: +# CHECK-NEXT: [0] - VLEN512SiFive7FDiv +# CHECK-NEXT: [1] - VLEN512SiFive7IDiv +# CHECK-NEXT: [2] - VLEN512SiFive7PipeA +# CHECK-NEXT: [3] - VLEN512SiFive7PipeB +# CHECK-NEXT: [4] - VLEN512SiFive7VA +# CHECK-NEXT: [5] - VLEN512SiFive7VCQ +# CHECK-NEXT: [6] - VLEN512SiFive7VL +# CHECK-NEXT: [7] - VLEN512SiFive7VS + +# CHECK: Resource pressure per iteration: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] +# CHECK-NEXT: - - - 1.00 - - - - + +# CHECK: Resource pressure by instruction: +# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: +# CHECK-NEXT: - - - 1.00 - - - - add a0, a0, a0 From f8db7885a9cf75e887031188d312068bce573f82 Mon Sep 17 00:00:00 2001 From: Roman Belenov Date: Mon, 22 Sep 2025 13:24:52 +0300 Subject: [PATCH 2/8] Fixed formatting --- llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index 9b6f3504cf7ff..5b40f99917404 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -87,7 +87,7 @@ bool RISCVInstrumentManager::supportsInstrumentType( llvm::StringRef Type) const { return Type == RISCVLMULInstrument::DESC_NAME || Type == RISCVSEWInstrument::DESC_NAME || - InstrumentManager::supportsInstrumentType(Type);; + InstrumentManager::supportsInstrumentType(Type); } UniqueInstrument @@ -95,8 +95,8 @@ RISCVInstrumentManager::createInstrument(llvm::StringRef Desc, llvm::StringRef Data) { if (Desc == RISCVLMULInstrument::DESC_NAME) { if (!RISCVLMULInstrument::isDataValid(Data)) { - LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": " - << Data << '\n'); + LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc + << ": " << Data << '\n'); return nullptr; } return std::make_unique(Data); From b8085e1a1680bb61d17c1e72b46d4c48f1df9f47 Mon Sep 17 00:00:00 2001 From: Roman Belenov Date: Mon, 22 Sep 2025 13:31:15 +0300 Subject: [PATCH 3/8] Fixed formatting --- llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index 5b40f99917404..319bbe96ab076 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -95,8 +95,8 @@ RISCVInstrumentManager::createInstrument(llvm::StringRef Desc, llvm::StringRef Data) { if (Desc == RISCVLMULInstrument::DESC_NAME) { if (!RISCVLMULInstrument::isDataValid(Data)) { - LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc - << ": " << Data << '\n'); + LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": " + << Data << '\n'); return nullptr; } return std::make_unique(Data); @@ -111,8 +111,8 @@ RISCVInstrumentManager::createInstrument(llvm::StringRef Desc, return std::make_unique(Data); } - LLVM_DEBUG(dbgs() << "RVCB: Creating default instrument for Desc: " - << Desc << '\n'); + LLVM_DEBUG(dbgs() << "RVCB: Creating default instrument for Desc: " << Desc + << '\n'); return InstrumentManager::createInstrument(Desc, Data); } From 818c140b4fc2c28c1c955fea224ca7336198767a Mon Sep 17 00:00:00 2001 From: Roman Belenov Date: Tue, 23 Sep 2025 09:01:11 +0300 Subject: [PATCH 4/8] Switched to LDBG() --- .../Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 37 +++++++++---------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index 319bbe96ab076..d754eb6829c6f 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -95,8 +95,8 @@ RISCVInstrumentManager::createInstrument(llvm::StringRef Desc, llvm::StringRef Data) { if (Desc == RISCVLMULInstrument::DESC_NAME) { if (!RISCVLMULInstrument::isDataValid(Data)) { - LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": " - << Data << '\n'); + LDBG() << "RVCB: Bad data for instrument kind " << Desc << ": " << Data + << '\n'; return nullptr; } return std::make_unique(Data); @@ -104,15 +104,14 @@ RISCVInstrumentManager::createInstrument(llvm::StringRef Desc, if (Desc == RISCVSEWInstrument::DESC_NAME) { if (!RISCVSEWInstrument::isDataValid(Data)) { - LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": " - << Data << '\n'); + LDBG() << "RVCB: Bad data for instrument kind " << Desc << ": " << Data + << '\n'; return nullptr; } return std::make_unique(Data); } - LLVM_DEBUG(dbgs() << "RVCB: Creating default instrument for Desc: " << Desc - << '\n'); + LDBG() << "RVCB: Creating default instrument for Desc: " << Desc << '\n'; return InstrumentManager::createInstrument(Desc, Data); } @@ -120,8 +119,8 @@ SmallVector RISCVInstrumentManager::createInstruments(const MCInst &Inst) { if (Inst.getOpcode() == RISCV::VSETVLI || Inst.getOpcode() == RISCV::VSETIVLI) { - LLVM_DEBUG(dbgs() << "RVCB: Found VSETVLI and creating instrument for it: " - << Inst << "\n"); + LDBG() << "RVCB: Found VSETVLI and creating instrument for it: " << Inst + << "\n"); unsigned VTypeI = Inst.getOperand(2).getImm(); RISCVVType::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI); @@ -252,8 +251,7 @@ unsigned RISCVInstrumentManager::getSchedClassID( // Need LMUL or LMUL, SEW in order to override opcode. If no LMUL is provided, // then no option to override. if (!LI) { - LLVM_DEBUG( - dbgs() << "RVCB: Did not use instrumentation to override Opcode.\n"); + LDBG() << "RVCB: Did not use instrumentation to override Opcode.\n"; return SchedClassID; } uint8_t LMUL = LI->getLMUL(); @@ -315,22 +313,21 @@ unsigned RISCVInstrumentManager::getSchedClassID( // Not a RVV instr if (!VPOpcode) { - LLVM_DEBUG( - dbgs() << "RVCB: Could not find PseudoInstruction for Opcode " - << MCII.getName(Opcode) - << ", LMUL=" << (LI ? LI->getData() : "Unspecified") - << ", SEW=" << (SI ? SI->getData() : "Unspecified") + LDBG() << "RVCB: Could not find PseudoInstruction for Opcode " + << MCII.getName(Opcode) << ", LMUL=" << (LI ? LI->getData() : "Unspecified") + << ", SEW=" << (SI ? SI->getData() : + "Unspecified") << ". Ignoring instrumentation and using original SchedClassID=" - << SchedClassID << '\n'); + << SchedClassID << '\n'; return SchedClassID; } // Override using pseudo - LLVM_DEBUG(dbgs() << "RVCB: Found Pseudo Instruction for Opcode " - << MCII.getName(Opcode) << ", LMUL=" << LI->getData() - << ", SEW=" << (SI ? SI->getData() : "Unspecified") + LDBG() << "RVCB: Found Pseudo Instruction for Opcode " << MCII.getName(Opcode) + << ", LMUL=" << LI->getData() << ", SEW=" << (SI ? SI->getData() : + "Unspecified") << ". Overriding original SchedClassID=" << SchedClassID - << " with " << MCII.getName(*VPOpcode) << '\n'); + << " with " << MCII.getName(*VPOpcode) << '\n'; return MCII.get(*VPOpcode).getSchedClass(); } From a8c75e69d457cd66094c9b095e5c017da9be2e1f Mon Sep 17 00:00:00 2001 From: Roman Belenov Date: Tue, 23 Sep 2025 09:05:59 +0300 Subject: [PATCH 5/8] Added timeline to ensure specific instructuion execution is tested --- .../RISCV/SiFiveX280/latency-instrument.s | 25 +++++++++++++++---- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s index 0ac183be85d54..376038b2d3037 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveX280/latency-instrument.s @@ -1,17 +1,17 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 --timeline -iterations=1 < %s | FileCheck %s -# LLVM-MCA-LATENCY 100 +# LLVM-MCA-LATENCY 20 add a0, a0, a0 # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 1 -# CHECK-NEXT: Total Cycles: 101 +# CHECK-NEXT: Total Cycles: 21 # CHECK-NEXT: Total uOps: 1 # CHECK: Dispatch Width: 2 -# CHECK-NEXT: uOps Per Cycle: 0.01 -# CHECK-NEXT: IPC: 0.01 +# CHECK-NEXT: uOps Per Cycle: 0.05 +# CHECK-NEXT: IPC: 0.05 # CHECK-NEXT: Block RThroughput: 0.5 # CHECK: Instruction Info: @@ -42,3 +42,18 @@ add a0, a0, a0 # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: - - - 1.00 - - - - add a0, a0, a0 + +# CHECK: Timeline view: +# CHECK-NEXT: 0123456789 +# CHECK-NEXT: Index 0123456789 0 + +# CHECK: [0,0] DeeeeeeeeeeeeeeeeeeeE add a0, a0, a0 + +# CHECK: Average Wait times (based on the timeline view): +# CHECK-NEXT: [0]: Executions +# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue +# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage + +# CHECK: [0] [1] [2] [3] +# CHECK-NEXT: 0. 1 0.0 0.0 0.0 add a0, a0, a0 From 286518b98c8cd139510f86030fcdbc42f579ee73 Mon Sep 17 00:00:00 2001 From: Roman Belenov Date: Tue, 23 Sep 2025 09:14:23 +0300 Subject: [PATCH 6/8] Fixed formatting --- .../Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index d754eb6829c6f..07c528c3b5164 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -314,20 +314,20 @@ unsigned RISCVInstrumentManager::getSchedClassID( // Not a RVV instr if (!VPOpcode) { LDBG() << "RVCB: Could not find PseudoInstruction for Opcode " - << MCII.getName(Opcode) << ", LMUL=" << (LI ? LI->getData() : "Unspecified") - << ", SEW=" << (SI ? SI->getData() : - "Unspecified") - << ". Ignoring instrumentation and using original SchedClassID=" - << SchedClassID << '\n'; + << MCII.getName(Opcode) + << ", LMUL=" << (LI ? LI->getData() : "Unspecified") + << ", SEW=" << (SI ? SI->getData() : "Unspecified") + << ". Ignoring instrumentation and using original SchedClassID=" + << SchedClassID << '\n'; return SchedClassID; } // Override using pseudo LDBG() << "RVCB: Found Pseudo Instruction for Opcode " << MCII.getName(Opcode) - << ", LMUL=" << LI->getData() << ", SEW=" << (SI ? SI->getData() : - "Unspecified") - << ". Overriding original SchedClassID=" << SchedClassID - << " with " << MCII.getName(*VPOpcode) << '\n'; + << ", LMUL=" << LI->getData() + << ", SEW=" << (SI ? SI->getData() : "Unspecified") + << ". Overriding original SchedClassID=" << SchedClassID << " with " + << MCII.getName(*VPOpcode) << '\n'; return MCII.get(*VPOpcode).getSchedClass(); } From 28b6bb0fc7cda57f75e21969738b6c1e680fe91c Mon Sep 17 00:00:00 2001 From: Roman Belenov Date: Tue, 23 Sep 2025 09:47:37 +0300 Subject: [PATCH 7/8] Added missing include --- llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index 07c528c3b5164..cbeb242ef305f 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -18,6 +18,7 @@ #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/DebugLog.h" #define DEBUG_TYPE "llvm-mca-riscv-custombehaviour" From 3b8fa32173e12f17ec14e312d39d909feb29e405 Mon Sep 17 00:00:00 2001 From: Roman Belenov Date: Tue, 23 Sep 2025 10:08:02 +0300 Subject: [PATCH 8/8] Erroneous brace removed --- llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index cbeb242ef305f..50730c697989d 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -121,7 +121,7 @@ RISCVInstrumentManager::createInstruments(const MCInst &Inst) { if (Inst.getOpcode() == RISCV::VSETVLI || Inst.getOpcode() == RISCV::VSETIVLI) { LDBG() << "RVCB: Found VSETVLI and creating instrument for it: " << Inst - << "\n"); + << "\n"; unsigned VTypeI = Inst.getOperand(2).getImm(); RISCVVType::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI);